A method for identifying a lithography defect hot spot pattern and a graphic structure

Abstract

The present invention provides a method for identifying hot spot patterns of lithography defects, including: determining a layer to be identified in a layout, i.e., the layer where a target pattern is located; presetting a width range and identifying an initial edge; presetting a first spacing range and a second spacing range; identifying a first spacer region and a second spacer region; identifying a first edge and a second edge; and identifying a polygon region in the initial polygon where one side contour edge is the first edge and the other side contour edge is the second edge as the target pattern, i.e., the hot spot pattern of the lithography defect. It can quickly and accurately identify the lithography defect pattern, which is beneficial to improving the production process and the steps are simple. The present invention also provides a hot spot pattern structure of the lithography defect, which is obtained by the method for identifying the hot spot pattern of the lithography defect of the present invention and can quickly identify whether a pattern has a risk of causing lithography defects.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor design and manufacturing, and in particular relates to a method for identifying a photolithography defect hotspot pattern and a pattern structure. Background Art

[0002] As the technology nodes of integrated circuit production process continue to advance, the design of integrated circuits has become more and more complex. The wavelength of the mainstream photolithography process currently used in integrated circuit production has been maintained at 193nm. When the wavelength of the exposure machine is not updated, the size of the exposure pattern continues to shrink, which will produce many photolithography patterns that meet the design rules but have poor actual process windows, generally referred to as photolithography defect hotspot patterns. The processing methods for photolithography defect hotspot patterns include optimizing the original layout design before tape-out, and performing special process processing on the detected photolithography process hotspots.

[0003] A lithography defect hotspot pattern generally refers to a pattern or pattern combination in a layout that has certain geometric features and feature sizes within a certain range that are prone to causing lithography defects; in actual manufacturing production, due to different processing methods of different manufacturers, lithography defect hotspot patterns may not actually cause lithography defects, that is, for different manufacturers, the lithography defect hotspot patterns that actually cause lithography defects may be different. It is of great practical significance to quickly and accurately locate lithography defect hotspot patterns in a large amount of layout data in advance and to guide manufacturers in design and production. The inability to effectively and conveniently identify the hotspot pattern is very unfavorable for the further improvement of lithography technology and design. Summary of the invention

[0004] The present invention is based on all or part of the problems of the above-mentioned prior art. All explanations or definitions of the terms and related technical principles involved in the following description of this application are merely illustrative and not restrictive.

[0005] A method for identifying a lithography defect hot spot pattern provided by the present invention on the one hand includes: Step S1. Obtain layout information and determine the layer to be identified in the layout, that is, the layer where the target pattern is located; Step S2. Preset a width range, and set the width of the pattern perpendicular to the pattern direction as the line width; Identify the pattern with the line width within the width range as the initial polygon, and identify the contour edge along the pattern direction in the initial polygon as the initial edge; Step S3. Preset a first spacing range and a second spacing range; Identify the interval area with the spacing between adjacent patterns within the first spacing range as the first interval area, and identify the interval area with the spacing between adjacent patterns within the second spacing range as the second interval area; Step S4. Identify the edge in the initial edge that contacts the first interval area as the first edge, and the edge that contacts the second interval area as the second edge; Step S5. Identify the polygon area in the initial polygon that satisfies that one side contour edge is the first edge and the other side contour edge is the second edge as plg_out; The plg_out is the identified target pattern, that is, the lithography defect hot spot pattern.

[0006] In one implementation, the "spacing between adjacent patterns" in Step S3 refers to the spacing between the initial polygon and its adjacent pattern.

[0007] In one implementation, the first interval area and / or the second interval area is a polygon, and the polygon can be a rectangle or a polygon area that can be cut into several rectangles.

[0008] The layer to be identified is one or more of a polysilicon layer, a metal layer, or an active region layer.

[0009] In the layer to be identified in the layout, all the contour edges of the patterns are edges along the pattern direction or edges perpendicular to the pattern direction.

[0010] All the contour edges of the target pattern plg_out along the pattern direction are identified as edge_out, which is used to provide information about the identified target pattern.

[0011] A lithography defect hot spot pattern structure provided by the present invention on the other hand is obtained by identifying with a method for identifying a lithography defect hot spot pattern of the present invention, and includes: a layer and a lithography defect hot spot pattern on the layer.

[0012] The layer includes one or more of a polysilicon layer, a metal layer, and an active region layer.

[0013] The lithography defect hot spot pattern is a polygon pattern, denoted as plg_out; the width of the pattern perpendicular to the pattern direction is defined as the line width; the line width of the plg_out meets a preset width range, and the distances between the two contour edges along the pattern direction of the plg_out and the adjacent patterns respectively meet the following conditions: the distance between the plg_out and one adjacent pattern is within a preset first distance range, and the distance between the plg_out and the other adjacent pattern is within a preset second distance range.

[0014] The contour edges of the polygon pattern and / or the adjacent patterns are all edges along the pattern direction or edges perpendicular to the pattern direction.

[0015] The present invention has the following beneficial effects: (1) According to a method for identifying a lithography defect hot spot pattern of the present invention, the initial edge, the first edge, and the second edge can be quickly identified through a preset range, and then the target pattern can be intuitively and accurately identified as a lithography defect pattern, which is beneficial to improving the production process, with simple steps and high efficiency. (2) According to a lithography defect hot spot pattern structure involved in the present invention, obtained through the identification method of the present invention, it is beneficial to identify whether a pattern has a risk of causing lithography defects during production. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a lithography defect hot spot pattern in Embodiment 1 of the present invention.

[0017] Figure 2 It is a schematic diagram of the method for identifying a lithography defect hot spot pattern in Embodiment 1 of the present invention.

[0018] Figure 3 It is a schematic diagram of the initial edge in Embodiment 1 of the present invention.

[0019] Figure 4 It is a schematic diagram of the first distance range and the second distance range in Embodiment 3 of the present invention.

[0020] Figure 5 It is a schematic diagram of the first spacer and the second spacer in Embodiment 3 of the present invention.

[0021] Figure 6 It is a schematic diagram of the first edge and the second edge in Embodiment 3 of the present invention.

[0022] Figure 7 It is a schematic diagram of the target pattern in Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings.

[0024] The embodiments disclosed by the present invention will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not used to limit the protection scope of the present invention. In the following embodiments, the operations of the embodiments are depicted in a specific order. The description of these orders is for better understanding of the details in the embodiments to comprehensively understand the present invention, but the description of these orders does not necessarily correspond one-to-one with the methods of the present invention, nor can the scope of the present invention be limited thereby.

[0025] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible operation processes of the methods according to the embodiments of the present invention. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in an interleaved manner, depending on the purpose to be achieved by the steps involved. In addition, each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and manual operations. Some commonly used English nouns or letters used by the present invention for the convenience of clear narration are only for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0026] Embodiment 1

[0027] For the convenience of description, in the following narration, the first direction Y is along the graphic trend in the accompanying drawings, and the direction perpendicular to the graphic trend is the second direction X. It should be noted that in actual situations, the graphic trend involved in the present invention changes with the graphics. For the same graphic along its trend, it may extend along the horizontal direction at one time and along the vertical direction at another time. The first direction Y and the second direction X are only for schematic purposes in cooperation with the accompanying drawings and are not actually fixed and unchangeable, and the graphic trend of the present invention cannot be limited thereby. As Figure 1 shown, the graphic width of the polygon M in the second direction X is the line width LW; other adjacent graphics N are provided at preset intervals S1 and S2 from the two side contour edges of the polygon graphic M in the second direction X respectively.

[0028] In this embodiment, as Figure 2 shown, and with reference to Figure 3, A method for identifying lithography defect hot spot patterns, comprising: Step S1. Obtain layout information and determine the layer to be identified in the layout, i.e., the layer where the target pattern is located. Step S2. Preset a width range, identify polygons with a line width LW within the width range as initial polygons, denoted as Fit_width_p, and identify the contour edges along the first direction Y as initial edges, denoted as Fit_width_e; Step S3. Preset a first spacing range and a second spacing range; identify the interval regions with the spacing between adjacent patterns within the first spacing range as the first interval regions, and identify the interval regions with the spacing between adjacent patterns within the second spacing range as the second interval regions; Step S4. Identify the edges in the initial edges that are in contact with the first interval region as the first edges, and the edges in contact with the second interval region as the second edges; Step S5. Identify the polygon region on the initial polygon Fit_width_p that satisfies one side contour edge being the first edge and the other side contour edge being the second edge as plg_out; the plg_out is the identified target pattern, i.e., the lithography defect hot spot pattern. Figure 1 Merely as an example, the polygon M can be any pattern in the layout. In the method for identifying lithography defect hot spot patterns of this embodiment, steps S2 and S3 can be executed substantially in parallel, and sometimes can also be executed alternately. In step S3, all the interval regions between adjacent patterns are judged and identified, and then all the first and second interval regions are identified. Step S4 further identifies based on the results obtained in steps S2 and S3.

[0029] The layer to be identified is any one of the polysilicon layer, metal layer or active region layer. All the edges of the target pattern plg_out along the pattern direction are identified as edge_out, which is used to provide information about the identified target pattern. At the same time, it is also identified which side contour edge of the initial polygon Fit_width_p in the second direction X the edge_out is, to avoid false alarms when the unilateral condition is repeatedly input.

[0030] Embodiment Two

[0031] The main difference between this embodiment and the first embodiment is that step S2 is executed before step S3. The initial polygon is first identified through step S2, recorded as Fit_width_p, and its contour edge along the first direction Y is identified as the initial edge, recorded as Fit_width_e; then step S3 is executed. The spacing between adjacent graphics in step S3 refers to the spacing between the initial polygon Fit_width_p and its adjacent graphics. The area between the initial polygon and other adjacent graphics that S1 or S2 meets the first spacing range is identified as the first spacing area; the area between the initial polygon and other adjacent graphics that S1 or S2 meets the second spacing range is identified as the second spacing area. That is, step S3 is only performed on the graphics adjacent to the identified initial polygon Fit_width_p, rather than all graphics in the layout.

[0032] Embodiment 3

[0033] Combined with reference Figures 4 to 7 In the third embodiment, based on the first embodiment, the first spacing range is recorded as LeftSpace and the second spacing range is recorded as RightSpace, which are different. In this embodiment, the area between other adjacent graphics of interval S1 or S2 that meet the first spacing range LeftSpace and the initial polygon Fit_width_p is identified as the first spacing area, recorded as Fit_LS; the area between other adjacent graphics of S1 or S2 that meet the second spacing range RightSpace and the initial polygon is identified as the second spacing area, recorded as Fit_RS. The line segment in the Fit_width_e that contacts the Fit_LS is identified as the first side Fit_width_e_LS, and the line segment in the Fit_width_e that contacts the Fit_RS is identified as the second side Fit_width_e_RS. The polygonal area in the Fit_width_p that meets the requirement that one side belongs to Fit_width_e_RS and the other side belongs to Fit_width_e_LS is identified as plg_out. In this embodiment, edge_out is used to provide information of the identified target graphic. The figures take plg_out as a rectangle as an example, but the possible shapes of plg_out in the present invention cannot be limited by this. Fit_LS and Fit_RS are rectangles and may also include multiple rectangular areas. The possible area shapes of the first spacer and the second spacer cannot be limited by the examples in the figures.

[0034] It should be noted that the above examples are only specific embodiments of the present invention. Obviously, the present invention is not limited to the above examples, and many variations are possible. All variations that can be directly derived or associated with the contents disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

[0035] The above embodiments are preferred cases of the present invention and are not used to limit the protection scope of the present invention. For the sake of clarity, many implementation details are described together in the above narrative. However, it should be understood that these implementation details are not used to limit the present invention.

[0036] The technical solutions among some practices described in the embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

Claims

1. A method for identifying a hot spot pattern of lithography defects, characterized in that: Including: Step S1. Obtain layout information and determine the layer to be recognized in the layout, i.e., the layer where the target pattern is located; Step S2. Preset a width range. Set the width of the pattern perpendicular to the pattern direction as the line width; Recognize the pattern with the line width within the width range as the initial polygon, and recognize the contour edge along the pattern direction in the initial polygon as the initial edge; Step S3. Preset a first spacing range and a second spacing range; Recognize the interval area with the spacing between adjacent patterns within the first spacing range as the first interval area, and recognize the interval area with the spacing between adjacent patterns within the second spacing range as the second interval area; Step S4. Recognize the edge in the initial edge that contacts the first interval area as the first edge, and recognize the edge that contacts the second interval area as the second edge; Step S5. Recognize the polygon area in the initial polygon that satisfies that one side contour edge is the first edge and the other side contour edge is the second edge as plg_out; The plg_out is the recognized target pattern, i.e., the lithography defect hot spot pattern.

2. The recognition method of a lithography defect hot spot pattern according to claim 1, wherein: In step S3, the "spacing between adjacent patterns" refers to the spacing between the initial polygon and its adjacent pattern.

3. The identification method of a lithography defect hot spot pattern according to claim 1, characterized in that: The first interval area and / or the second interval area is a polygon.

4. The recognition method of a lithography defect hot spot pattern according to claim 1, characterized in that: The layer to be recognized is one or more of the polysilicon layer, metal layer, or active region layer.

5. The method for identifying a lithography defect hot spot pattern according to claim 1, wherein: In the layer to be recognized in the layout, all the contour edges of the patterns are the edges along the pattern direction or the edges perpendicular to the pattern direction.

6. The method for identifying a hot spot pattern of a lithography defect according to claim 1, wherein: All the contour edges of the target pattern plg_out along the pattern direction are recognized as edge_out, which is used to provide information about the recognized target pattern.

7. A lithography defect hot spot pattern structure, characterized in that: Obtained by the recognition method of a lithography defect hot spot pattern according to any one of claims 1-6, including: a layer and a lithography defect hot spot pattern on the layer.

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