Semiconductor structure and manufacturing method thereof

Abstract

The present invention discloses a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure includes a substrate having a first region and a second region around the first region; at least one first fin structure arranged in the first region; at least one second fin structure arranged in the second region; a first isolation trench arranged in the first region and adjacent to the at least one first fin structure; a first trench isolation layer arranged in the first isolation trench; a second isolation trench arranged around the first region and located between the at least one first fin structure and the at least one second fin structure, wherein the bottom surface of the second isolation trench has a step difference; and a second trench isolation layer arranged in the second isolation trench.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In advanced semiconductor manufacturing processes, SiGe epitaxial layers are typically formed on the drain and source regions of PMOS transistors to improve device performance. However, in very fine-pitch integrated circuits, such as static random access memory (SRAM) macros, two adjacent pull-up transistors (PL transistors) within an SRAM cell may experience SiGe bridges, leading to short circuits. Summary of the Invention

[0003] The main purpose of the present invention is to provide an improved semiconductor structure and a method for manufacturing the same to address the above-mentioned deficiencies and shortcomings of the prior art.

[0004] On the one hand, the present invention provides a semiconductor structure, comprising a substrate having a first region and a second region around the first region; at least one first fin structure arranged in the first region; at least one second fin structure arranged in the second region; a first isolation trench arranged in the first region and adjacent to the at least one first fin structure; a first trench isolation layer arranged in the first isolation trench; a second isolation trench arranged around the first region and located between the at least one first fin structure and the at least one second fin structure, wherein the bottom surface of the second isolation trench has a step difference; and a second trench isolation layer arranged in the second isolation trench.

[0005] According to an embodiment of the present invention, the bottom surface includes a first surface in the first area and a second surface in the second area, wherein the first surface is lower than the second surface.

[0006] According to an embodiment of the present invention, a top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

[0007] According to an embodiment of the present invention, the first region is a PMOS region, and the second region is an NMOS region.

[0008] According to an embodiment of the present invention, the second area surrounds the first area.

[0009] According to an embodiment of the present invention, a top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure.

[0010] According to an embodiment of the present invention, the semiconductor structure further includes: a first gate, disposed on the at least one first fin structure; a first source region, disposed on the at least one first fin structure and adjacent to the first gate; and a first drain region, disposed on the at least one first fin structure and adjacent to the first gate.

[0011] According to an embodiment of the present invention, the first source region and the first drain region include a SiGe epitaxial layer.

[0012] According to an embodiment of the present invention, the semiconductor structure further includes: a second gate, disposed on the at least one second fin structure; a second source region, disposed on the at least one second fin structure and adjacent to the second gate; and a second drain region, disposed on the at least one second fin structure and adjacent to the second gate.

[0013] According to an embodiment of the present invention, the second source region and the second drain region include a SiP epitaxial layer.

[0014] Another aspect of the present invention provides a method for forming a semiconductor structure. First, a substrate is provided, having a first region and a second region surrounding the first region. Next, the substrate is etched to form a groove in the first region. A trench isolation process is then performed to form a first isolation trench in the first region, at least one first fin structure in the first region, a second isolation trench surrounding the first region, at least one second fin structure in the second region, a first trench isolation layer in the first isolation trench, and a second trench isolation layer in the second isolation trench, wherein the second isolation trench is located between the at least one first fin structure and the at least one second fin structure, and the bottom surface of the second isolation trench has a step height difference.

[0015] According to an embodiment of the present invention, the bottom surface includes a first surface in the first area and a second surface in the second area, wherein the first surface is lower than the second surface.

[0016] According to an embodiment of the present invention, a top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

[0017] According to an embodiment of the present invention, the first region is a PMOS (P-type metal oxide semiconductor transistor) region, and the second region is an NMOS (N-type metal oxide semiconductor transistor) region.

[0018] According to an embodiment of the present invention, the second area surrounds the first area.

[0019] According to an embodiment of the present invention, a top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure.

[0020] According to an embodiment of the present invention, the method further includes: forming a first gate on the at least one first fin structure; forming a first source region adjacent to the first gate on the at least one first fin structure; and forming a first drain region adjacent to the first gate on the at least one first fin structure.

[0021] According to an embodiment of the present invention, the method further includes: forming a SiGe epitaxial layer on the first source region and the first drain region.

[0022] According to an embodiment of the present invention, the method further includes: forming a second gate on the at least one second fin structure; forming a second source region adjacent to the second gate on the at least one second fin structure; and forming a second drain region adjacent to the second gate on the at least one second fin structure.

[0023] According to an embodiment of the present invention, the method further includes: forming a SiP epitaxial layer on the second source region and the second drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A top view of a semiconductor structure according to an embodiment of the present invention;

[0025] Figure 2 To follow Figure 1 A schematic cross-sectional view shown along the median tangent line II';

[0026] Figures 3 to 15 A schematic diagram of a method for forming a semiconductor structure.

[0027] Description of main component symbols

[0028] 1 Semiconductor structure

[0029] 100 base

[0030] 102 insulation layer

[0031] 110 Shallow Trench Isolation Area

[0032] AA1~AA4 active area

[0033] DD1 first drain region

[0034] DD2 Second drain region

[0035] F1 first fin structure

[0036] F2 second fin structure

[0037] FST1, FST2 top surface

[0038] G1~G4 gate

[0039] GOX1, GOX2 gate oxide layer

[0040] H-step drop

[0041] h height

[0042] ht height difference

[0043] HM Covering Layer

[0044] IM1 first trench isolation layer

[0045] IM2 Second trench isolation layer

[0046] PL1, PL2 PMOS pull-up transistors

[0047] POL Polysilicon Layer

[0048] RA groove

[0049] RE1, RE2 depression area

[0050] RH step height

[0051] R1 First Area

[0052] R2 Second Area

[0053] S bottom

[0054] S1 First Surface

[0055] S2 Second Surface

[0056] SD1 first source region

[0057] SD2 second source region

[0058] SG1, SG2 SiGe epitaxial layer

[0059] SPE SiP epitaxial layer

[0060] ST1, ST2 top surface

[0061] T1 first isolation trench

[0062] T2 Second isolation trench

[0063] W Distance DETAILED DESCRIPTION

[0064] Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that describes specific examples of the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable one skilled in the art to implement them.

[0065] Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments contained therein are to be defined by the appended claims.

[0066] See also Figure 1 and Figure 2 ,in Figure 1 FIG1 is a top view of a semiconductor structure according to an embodiment of the present invention. Figure 2 To follow Figure 1 The cross-sectional view shown by the midline II'. Figure 1 and Figure 2 As shown, the semiconductor structure 1 includes a substrate 100, such as a silicon substrate, having a first region R1 and a second region R2 surrounding the first region R1. According to an embodiment of the present invention, the second region R2 may surround the first region R1.

[0067] According to an embodiment of the present invention, the semiconductor structure 1 may be, for example, part of a static random access memory, wherein the first region R1 may be the area indicated by the dashed line. For example, the first region R1 includes at least two PMOS pull-up transistors PL1 and PL2. According to an embodiment of the present invention, the first region R1 may be a PMOS region, i.e., only PMOS transistors are disposed in the first region R1, and the second region R2 may be an NMOS region, i.e., only NMOS transistors are disposed in the second region R2.

[0068] exist Figure 1 In the diagram, only four active regions AA1-AA4 extending along the reference Y-axis and four gates G1-G4 extending along the reference X-axis are illustrated. According to an embodiment of the present invention, gate G1 spans active region AA2, forming a PMOS pull-up transistor PL1, while gate G2 spans active region AA3, forming a PMOS pull-up transistor PL2. Between active regions AA1-AA4 lies shallow trench isolation (STI) region 110.

[0069] like Figure 2As shown, the semiconductor structure 1 includes at least one first fin structure F1 disposed within a first region R1, and at least one second fin structure F2 disposed within a second region R2. A first isolation trench T1 is disposed within the first region R1, adjacent to the first fin structure F1. A first trench isolation layer IM1, such as a silicon oxide layer, is disposed within the first isolation trench T1. A second isolation trench T2 is disposed around the first region R1. The second isolation trench T2 is located between the first fin structure F1 and the second fin structure F2. A second trench isolation layer IM2, such as a silicon oxide layer, is disposed within the second isolation trench T2.

[0070] According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2 has a step height H. According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2 includes a first surface S1 within the first region R1 and a second surface S2 within the second region R2, and the first surface S1 is lower than the second surface S2, thereby forming the step height H at the junction of the first region R1 and the second region R2. According to an embodiment of the present invention, for example, the step height H is approximately 30 to 100 angstroms, but is not limited thereto.

[0071] According to an embodiment of the present invention, a top surface ST1 of the first trench isolation layer IM1 is coplanar with a top surface ST2 of the second trench isolation layer IM2. According to an embodiment of the present invention, a top surface FST1 of the first fin structure F1 is lower than a top surface FST2 of the second fin structure F2.

[0072] According to an embodiment of the present invention, Figure 1 As shown, the gate G1 of the semiconductor structure 1 can be disposed on the first fin structure F1. According to an embodiment of the present invention, a first source region SD1 adjacent to the gate G1 is further disposed on the first fin structure F1. For example, P + According to an embodiment of the present invention, a first drain region DD1 adjacent to the gate G1 is further provided on the first fin structure F1. For example, P + doped region. The gate G1, the first source region SD1, and the first drain region DD1 can constitute a PMOS pull-up transistor PL1. According to an embodiment of the present invention, the first source region SD1 and the first drain region DD1 include a SiGe epitaxial layer SG1, whose height h above the top surface ST1 of the first trench isolation layer IM1 is approximately between 5 and 25 nm, but is not limited thereto. The distance W between the SiGe epitaxial layer SG1 and the adjacent SiGe epitaxial layer SG2 on the top surface ST1 of the first trench isolation layer IM1 is at least 20 nm, for example, between 20 and 60 nm. Therefore, the semiconductor structure 1 of the present invention can effectively avoid the short circuit problem caused by SiGe bridging.

[0073] According to an embodiment of the present invention, the gate G2 of the semiconductor structure 1 may be disposed on the second fin structure F2. According to an embodiment of the present invention, a second source region SD2 adjacent to the gate G2 is further disposed on the second fin structure F2. + According to an embodiment of the present invention, a second drain region DD2 adjacent to the gate G2 is further provided on the second fin structure F2. For example, N + The gate G2, the second source region SD2 and the second drain region DD2 may form an NMOS transistor. According to an embodiment of the present invention, the second source region SD2 and the second drain region DD2 include a SiP epitaxial layer SPE.

[0074] Figures 3 to 15 A method for forming a semiconductor structure is illustrated. Figure 3 As shown, a substrate 100, such as a silicon substrate, is first provided, having a first region R1 and a second region R2 surrounding the first region R1. According to an embodiment of the present invention, the second region R2 may surround the first region R1. According to an embodiment of the present invention, the first region R1 may be a PMOS region, that is, only PMOS transistors are disposed in the first region R1, and the second region R2 may be an NMOS region, that is, only NMOS transistors are disposed in the second region R2.

[0075] Next, using photolithography and etching processes, the substrate 100 is etched only in the first region R1 to form a recess RA in the first region R1 and a step height RH at the junction of the first region R1 and the second region R2. According to an embodiment of the present invention, the step height RH is, for example, approximately 30 to 100 angstroms, but is not limited thereto. Next, a capping layer HM is deposited over the entire surface of the substrate 100. The capping layer HM may comprise, but is not limited to, a silicon nitride layer.

[0076] Next, proceed Figures 4 to 8 The trench isolation manufacturing process is shown in FIG. Figure 4 As shown, photolithography and etching processes are performed to etch predetermined areas of the capping layer HM and substrate 100, forming a first isolation trench T1 within the first region R1 and a second isolation trench T2 around the first region R1. Simultaneously, at least one first fin structure F1 is formed within the first region R1, and at least one second fin structure F2 is formed within the second region R2, with the second isolation trench T2 located between the first fin structure F1 and the second fin structure F2. According to an embodiment of the present invention, the top surface FST1 of the first fin structure F1 is approximately 30 to 100 angstroms lower than the top surface FST2 of the second fin structure F2.

[0077] According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2 has a step height H. According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2 includes a first surface S1 within the first region R1 and a second surface S2 within the second region R2, and the first surface S1 is lower than the second surface S2, thereby forming the step height H at the junction of the first region R1 and the second region R2. According to an embodiment of the present invention, for example, the step height H is approximately 30 to 100 angstroms, but is not limited thereto.

[0078] like Figure 5 As shown, a chemical vapor deposition process is then performed to deposit an insulating layer 102, such as a silicon oxide layer, on the entire substrate 100. According to an embodiment of the present invention, the insulating layer 102 covers the capping layer HM and fills the first isolation trench T1 and the second isolation trench T2.

[0079] like Figure 6 As shown, the insulating layer 102 is then planarized by a process such as chemical mechanical polishing (CMP) until the top surface of the capping layer HM in the second region R2 is exposed. Meanwhile, the top surface of the capping layer HM in the first region R1 may still be covered by the insulating layer 102.

[0080] like Figure 7 As shown, an etch-back process is then performed to etch away the insulating layer 102 to a predetermined thickness using dry or wet etching, exposing the top surface of the cap layer HM in the first region R1. This forms a first trench isolation layer IM1 in the first isolation trench T1, and a second trench isolation layer IM2 in the second isolation trench T2. According to an embodiment of the present invention, a top surface ST1 of the first trench isolation layer IM1 and a top surface ST2 of the second trench isolation layer IM2 are coplanar.

[0081] like Figure 8 As shown, the capping layer HM is then removed using an etching method, such as a wet etching method, to expose the top surface FST1 of the first fin structure F1 and the top surface FST2 of the second fin structure F2. According to an embodiment of the present invention, the top surface ST1 of the first trench isolation layer IM1 and the top surface ST2 of the second trench isolation layer IM2 are higher than the top surface FST2 of the second fin structure F2, and the top surface FST2 of the second fin structure F2 is higher than the top surface FST1 of the first fin structure F1. The height difference ht between the top surface FST2 of the second fin structure F2 and the top surface FST1 of the first fin structure F1 is approximately 30 to 100 angstroms, but is not limited thereto.

[0082] like Figure 9As shown, an ion implantation process is then performed to form an ion well, such as a P-type well or an N-type well (not shown) in the substrate 100. Next, a cleaning process is performed. The above-mentioned cleaning process will consume part of the thickness of the first trench isolation layer IM1 and the second trench isolation layer IM2, so that the top surface ST1 of the first trench isolation layer IM1 and the top surface ST2 of the second trench isolation layer IM2 will be close to the top surface FST2 of the second fin structure F2, but still higher than the top surface FST1 of the first fin structure F1. According to an embodiment of the present invention, the height difference ht between the top surface ST1 of the first trench isolation layer IM1 and the top surface FST1 of the first fin structure F1 is approximately 30 to 100 angstroms, but is not limited thereto. In addition, after the above-mentioned cleaning process, the upper corners of the first trench isolation layer IM1 will be rounded.

[0083] like Figure 10 As shown, an oxidation process is then performed to form a gate oxide layer GOX1 and a gate oxide layer GOX2 on the top surface ST1 of the first trench isolation layer IM1 and the top surface ST2 of the second trench isolation layer IM2, respectively. According to an embodiment of the present invention, the gate oxide layer GOX1 and the gate oxide layer GOX2 may include silicon oxide layers, but are not limited thereto.

[0084] like Figure 11 As shown, a polysilicon layer POL is then deposited all over the substrate 100 .

[0085] like Figure 12 As shown, the polysilicon layer POL is patterned by photolithography and etching processes, and a gate G1 is formed on the first fin structure F1, and a gate G2 is formed on the second fin structure F2 (as shown in FIG. Figure 1 Since the polysilicon layer POL has been removed in this cross section, only the outline of the gate G2 is shown in dashed lines for illustration. Subsequently, spacers (not shown) can be formed on the gates G1 and G2.

[0086] like Figure 13 As shown, a recessed region RE1 and a recessed region RE2 adjacent to the gate G1 (not shown) are then formed on the first fin structure F1 of the first region R1. The method for forming the recessed region RE1 and the recessed region RE2 on the first fin structure F1 can utilize wet etching, but is not limited thereto. According to an embodiment of the present invention, the recessed region RE1 and the recessed region RE2 are separated by the first trench isolation layer IM1. According to an embodiment of the present invention, at this time, the top surface ST1 of the first trench isolation layer IM1 and the top surface ST2 of the second trench isolation layer IM2 are still coplanar.

[0087] like Figure 14As shown, an epitaxial fabrication process is then performed to form a SiGe epitaxial layer SG1 and a SiGe epitaxial layer SG2 in the recessed region RE1 and the recessed region RE2 of the first region R1, respectively. For example, the SiGe epitaxial layer SG1 and the SiGe epitaxial layer SG2 can be formed by methods such as metal organic vapor phase epitaxy, but are not limited thereto. When performing the above-mentioned epitaxial fabrication process, the second region R2 can be covered. The distance W between the SiGe epitaxial layer SG1 and the adjacent SiGe epitaxial layer SG2 on the top surface ST1 of the first trench isolation layer IM1 is at least 20 nm, for example, between 20 and 60 nm. Therefore, the semiconductor structure 1 of the present invention can effectively avoid the short circuit problem caused by SiGe bridging.

[0088] like Figure 15 As shown, an epitaxial growth process is finally performed to form a SiP epitaxial layer SPE on the second fin structure F2 in the second region R2.

[0089] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure, characterized in that Include: a substrate having a first region and a second region surrounding the first region; at least one first fin-shaped structure disposed in the first region; at least one second fin-shaped structure disposed in the second region; a first isolation trench disposed in the first region and adjacent to the at least one first fin structure; a first trench isolation layer, disposed in the first isolation trench; a second isolation trench disposed around the first region and between the at least one first fin structure and the at least one second fin structure, wherein a bottom surface of the second isolation trench has a step height; as well as a second trench isolation layer, disposed in the second isolation trench; The bottom surface includes a first surface within the first region and a second surface within the second region, wherein the first surface is lower than the second surface.

2. The semiconductor structure according to claim 1, wherein A top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

3. The semiconductor structure according to claim 1, wherein The first region is a PMOS region, and the second region is an NMOS region.

4. The semiconductor structure according to claim 1, wherein The second area surrounds the first area.

5. The semiconductor structure according to claim 1, wherein A top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure. The semiconductor structure according to claim 1 , wherein: Also includes: a first gate, disposed on the at least one first fin-shaped structure; a first source region, disposed on the at least one first fin structure and adjacent to the first gate; as well as A first drain region is disposed on the at least one first fin structure and is adjacent to the first gate.

7. The semiconductor structure according to claim 6, wherein: The first source region and the first drain region include SiGe epitaxial layers.

8. The semiconductor structure according to claim 1, wherein Also includes: a second gate, disposed on the at least one second fin-shaped structure; a second source region, disposed on the at least one second fin structure and adjacent to the second gate; as well as The second drain region is disposed on the at least one second fin structure and is adjacent to the second gate.

9. The semiconductor structure according to claim 8, wherein The second source region and the second drain region include a SiP epitaxial layer.

10. A method of forming a semiconductor structure, comprising: providing a substrate having a first region and a second region surrounding the first region; etching the substrate to form a groove in the first region; as well as A trench isolation fabrication process is performed to form a first isolation trench in the first region, at least one first fin structure in the first region, a second isolation trench around the first region, at least one second fin structure in the second region, a first trench isolation layer in the first isolation trench, and a second trench isolation layer in the second isolation trench, wherein the second isolation trench is located between the at least one first fin structure and the at least one second fin structure, and wherein a bottom surface of the second isolation trench has a step height. The bottom surface includes a first surface within the first region and a second surface within the second region, wherein the first surface is lower than the second surface.

11. The method according to claim 10, wherein: A top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

12. The method according to claim 10, wherein: The first region is a PMOS region, and the second region is an NMOS region.

13. The method according to claim 10, wherein: The second area surrounds the first area.

14. The method according to claim 10, wherein: A top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure.

15. The method according to claim 10, wherein Also includes: forming a first gate on the at least one first fin structure; forming a first source region adjacent to the first gate on the at least one first fin structure; and A first drain region adjacent to the first gate is formed on the at least one first fin structure.

16. The method according to claim 15, wherein Also includes: A SiGe epitaxial layer is formed on the first source region and the first drain region.

17. The method according to claim 10, wherein Also includes: forming a second gate on the at least one second fin structure; forming a second source region adjacent to the second gate on the at least one second fin structure; and A second drain region adjacent to the second gate is formed on the at least one second fin structure.

18. The method according to claim 17, wherein Also includes: A SiP epitaxial layer is formed on the second source region and the second drain region.

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