High dynamic range image sensor, pixel unit, electronic information device

Abstract

The embodiment of the present invention discloses a high dynamic range image sensor, a pixel unit, and an electronic information device. The image sensor includes: a reset transistor; a source follower transistor; an overflow drain; a first photodiode; a first transfer transistor; a first floating diffusion region; a second photodiode; a second transfer transistor; a second floating diffusion region; the first photodiode and the second photodiode have different full well capacities; the first photodiode and the second photodiode share an overflow drain; and the source output signal of the source follower transistor. The embodiment of the present invention is different from the existing 4T pixel structure design, and adopts a 3T pixel structure design and photodiodes with different full well capacities share an overflow drain, and adds three switching transistors and three corresponding capacitors. Through the switching transistor, the capacitors are selectively turned on or off, thereby realizing a high dynamic range image sensor with multi-level conversion gain.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a high dynamic image sensor and a pixel unit. Background Art

[0002] In different real-life scenarios, the intensity of light varies greatly. Especially for monitoring, vehicle-mounted and other scenarios, changes in light and darkness are very common. In order to adapt to different scenarios, the image sensors used in these scenarios need to have a sufficiently large dynamic range to record as many image details as possible. The design requirements of high dynamic range (HDR) for sensor pixels are different at different brightness levels. At high brightness, recording details requires the pixel's photodiode (PD) to have as large a full-well capacity (FWC, Full-well Capacitance) as possible. At low brightness, the capacitance of the floating diffusion (FD, Floating Diffusion) needs to be as small as possible to obtain the largest possible conversion gain in order to improve the sensor's signal-to-noise ratio. There is a contradiction between the two in design. An overly small floating diffusion cannot fully read out all the electrons of the large full-well capacity PD under high light, resulting in a residual image (Lag) phenomenon. Therefore, some people have proposed to use two pixels with different FWCs to combine their outputs. Large pixels have high FWC, which is suitable for low-light scenes; small pixels have low FWC, which is suitable for strong-light scenes. The images obtained by the two pixels of different sizes are combined together, and a higher dynamic range than the individual single-pixel images is obtained by changing the effective capacitance of the floating diffusion area.

[0003] Existing variable conversion gain sensors often use a dual conversion gain (DCG) design. This design introduces an external capacitor and adds a control switch (commonly using a metal oxide semiconductor field effect transistor, or MOSFET, as a switch). When a high exposure signal needs to be read, the switch is turned on to connect the FD to the capacitor to help extract the charge; when a lower signal strength needs to be read, the switch is turned off to reduce the effective capacitance of the floating diffusion area, thereby obtaining a higher conversion gain and improving the readout signal-to-noise ratio. The image data of two different exposure levels is output by the large and small pixel arrays alone, and then combined with the DCG technology, the high conversion gain (HCG, HighConversion Gain) and low conversion gain (LCG, Low Conversion Gain) are matched in the large and small pixels respectively to widen the corresponding image data to a suitable data range. This further increases the brightness separation of the image data and saves more image details. By integrating the two images through the algorithm, a single-frame HDR image is formed.

[0004] With the improvement of image sensor manufacturing technology, the FWC of pixels is also gradually increasing, which puts forward higher ratio requirements for the conversion gain gear. The electrical signal strength of image sensors with large and small pixels in strong light and dark light may differ by dozens of times. If only the DCG solution is used, the size of the external capacitor must be dozens of times the FD capacitance value. This brings huge challenges to the circuit design of image sensors. At the same time, the two gears with huge differences cannot provide the best conversion gain in the entire light intensity range, resulting in loss of image details in medium light intensity scenes. Summary of the invention

[0005] In view of the problems existing in the prior art, image sensors with large and small pixels need to be designed with more conversion gain levels. An embodiment of the present invention provides a high dynamic image sensor, including:

[0006] reset transistor; source follower transistor; overflow drain;

[0007] a first photodiode; a first transfer transistor; a first floating diffusion region;

[0008] a second photodiode; a second transfer transistor; a second floating diffusion region;

[0009] The first photodiode and the second photodiode have different full well capacities;

[0010] The first photodiode and the second photodiode share one overflow drain;

[0011] The source of the source follower transistor outputs a signal.

[0012] In some embodiments, the first transfer transistor and the second transfer transistor employ vertical transfer gates.

[0013] In some embodiments, the method further includes: at least three transistors and three corresponding capacitors to achieve multiple conversion gains.

[0014] In some embodiments, the three transistors include a first transistor, a second transistor, and a third transistor; a first end of the first transistor is connected to the first floating diffusion region; a second end of the first transistor is connected to the second floating diffusion region and to a first end of the first capacitor; a second end of the first capacitor is grounded;

[0015] The first end of the second transistor is connected to the second floating diffusion area; the second end of the second transistor is connected to the first end of the second capacitor; the second end of the second capacitor is grounded;

[0016] The first end of the third transistor is connected to the second end of the second transistor; the second end of the third transistor is connected to the first end of the third capacitor; the second end of the third capacitor is grounded;

[0017] The first end of the reset transistor is connected to the second end of the third transistor, and the second end of the reset transistor is connected to a power supply.

[0018] In some embodiments, for the first floating diffusion area or the second floating diffusion area, the gates of the first transistor, the second transistor, the third transistor and the reset transistor are controlled so that the first floating diffusion area or the second floating diffusion area obtains a first, second, third or fourth conversion gain.

[0019] In some embodiments, for the first floating diffusion area, the third transistor and the reset transistor are kept turned on, so that the first transistor provides a reset function for the first floating diffusion area, and when the first transistor is turned off, a first conversion gain is obtained; when the first transistor and the second transistor are turned off and the first transistor is turned on, a second conversion gain is obtained; when the third transistor is turned off and the first transistor and the second transistor are turned on, a third conversion gain is obtained; when the first transistor, the second transistor and the third transistor are turned on, a fourth conversion gain is obtained.

[0020] In some embodiments, for the second floating diffusion area, the reset transistor is kept turned on so that the third transistor provides a reset function for the second floating diffusion area, and when the first transistor and the second transistor are turned off, a first conversion gain is obtained; when the second transistor and the third transistor are turned off and the first transistor is turned on, a second conversion gain is obtained; when the third transistor is turned off and the first transistor and the second transistor are turned on, a third conversion gain is obtained; when the first transistor, the second transistor and the third transistor are turned on, a fourth conversion gain is obtained.

[0021] Another aspect of an embodiment of the present invention provides a pixel unit of a high dynamic image sensor, comprising: a reset transistor; a source follower transistor; a first photodiode; a first transfer transistor; a first floating diffusion area; a second photodiode; a second transfer transistor; a second floating diffusion area; a first transistor, a second transistor, and a third transistor; a first capacitor, a second capacitor, and a third capacitor; a first active area and a second active area; wherein the first photodiode and the second photodiode are arranged diagonally; the first active area and the second active area are arranged on both sides of the first photodiode and the second photodiode respectively; the reset transistor, the second transistor, and the third transistor are arranged in the first active area; the source follower transistor is arranged in the second active area; the source follower transistor is a fin field effect transistor; and the first transistor is arranged between the first photodiode and the second photodiode.

[0022] Another aspect of the embodiments of the present invention further provides an electronic information device including the high dynamic image sensor.

[0023] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0024] The embodiment of the present invention introduces two photodiodes PD with different FWC and a quad conversion gain (QCG, Quad Conversion Gain) design in the pixel design of a high dynamic image sensor. In the case of high exposure, a large PD is used to output the signal. At this time, the transistors corresponding to all capacitors should be turned on to provide the maximum effective capacitance and obtain the minimum conversion gain. In the case of low exposure, a small PD is used to output the signal. At this time, all capacitor switches should be turned off to provide the minimum effective capacitance and obtain the maximum conversion gain. The conversion gain circuit includes three capacitors with capacitances of different sizes in stages, and three transistors serving as switches for the three capacitors respectively. By performing different switch configurations on the three switches, capacitors with capacitances of different sizes can be added to the floating diffusion areas FD corresponding to different photodiodes PD, and the conversion gain can be switched between four different gears. This allows the image sensor to have a larger dynamic range.

[0025] The embodiment of the present invention is different from the existing 4T pixel structure design. It adopts a 3T pixel structure design and photodiodes with different full well capacities share an overflow drain, and adds three switching transistors and three corresponding capacitors. Through the switching transistors, the capacitors are selectively opened or closed, thereby realizing a high dynamic range image sensor with multi-level conversion gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A schematic diagram of the structure of a high dynamic image sensor pixel unit with multiple conversion gains according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a graph showing the relationship between the pixel signal and the number of readout electrons during readout of an exemplary dual conversion gain image sensor pixel;

[0028] Figure 3 A curve showing the relationship between a pixel signal and the number of readout electrons during the readout period of a high dynamic image sensor pixel with multiple conversion gains according to an exemplary embodiment of the present invention;

[0029] Figure 4 An exemplary layout design diagram of a high dynamic image sensor pixel unit with multiple conversion gains is provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0031] As shown in the present invention and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements.

[0032] Figure 1 The diagram is a circuit diagram of a high dynamic image sensor pixel unit with multiple conversion gains according to an exemplary embodiment of the present invention.

[0033] like Figure 1 As shown, the high dynamic image sensor pixel unit includes: a reset transistor RST, a source follower transistor SF, an overflow drain (OFD, over flow diffusion, Figure 1), a first photodiode PD0, a first transfer transistor TX0; a first floating diffusion area FD0; a second photodiode PD1; a second transfer transistor TX1; a second floating diffusion area FD1, a first transistor QCG0 and a corresponding capacitor C0, a second transistor QCG1 and a corresponding capacitor C1, a third transistor QCG2 and a corresponding capacitor C2. Among them, the first photodiode PD0 and the second photodiode PD1 have different sensitivities. For example, the photosensitivity areas of the first photodiode PD0 and the second photodiode PD1 may be different. The first photodiode PD0 and the second photodiode PD1 share an overflow drain. The overflow drain may be disposed between the first photodiode PD0 and the second photodiode PD1. The source output signal PXD of the source follower transistor SF.

[0034] A first end of the first transistor QCG0 is connected to the first floating diffusion area FD0 ; a second end of the first transistor QCG0 is connected to the second floating diffusion area FD1 and to a first end of the first capacitor C0 ; a second end of the first capacitor C0 is grounded.

[0035] A first end of the second transistor QCG1 is connected to the second floating diffusion region FD1 ; a second end of the second transistor QCG1 is connected to a first end of the second capacitor C1 ; and a second end of the second capacitor C1 is grounded.

[0036] A first end of the third transistor QCG2 is connected to a second end of the second transistor QCG1 ; a second end of the third transistor QCG2 is connected to a first end of the third capacitor C2 ; and a second end of the third capacitor C2 is grounded.

[0037] A first end of the reset transistor RST is connected to a second end of the third transistor QCG2 , and a second end of the reset transistor RST is connected to a power source VDD.

[0038] For the first floating diffusion area FD0 or the second floating diffusion area FD1, the gates of the first transistor QCG0, the second transistor QCG1, the third transistor QCG2 and the reset transistor RST are controlled so that the first floating diffusion area FD0 or the second floating diffusion area FD1 obtains the first, second, third or fourth conversion gain.

[0039] For the first floating diffusion area FD0, the third transistor QCG2 and the reset transistor RST are kept turned on, so that the first transistor QCG0 provides a reset function for the first floating diffusion area FD0, and when the first transistor QCG0 is turned off, a first conversion gain is obtained; when the first transistor QCG0 and the second transistor QCG1 are turned off, and the first transistor QCG0 is turned on, a second conversion gain is obtained; when the third transistor QCG2 is turned off, and the first transistor QCG0 and the second transistor QCG1 are turned on, a third conversion gain is obtained; when the first transistor QCG0, the second transistor QCG1 and the third transistor QCG2 are turned on, a fourth conversion gain is obtained.

[0040] For the second floating diffusion area FD1, the reset transistor RST is kept turned on so that the third transistor QCG2 provides a reset function for the second floating diffusion area FD1. When the first transistor QCG0 and the second transistor QCG1 are turned off, the first conversion gain is obtained; when the second transistor QCG1 and the third transistor QCG2 are turned off and the first transistor QCG0 is turned on, the second conversion gain is obtained; when the third transistor QCG2 is turned off and the first transistor QCG0 and the second transistor QCG1 are turned on, the third conversion gain is obtained; when the first transistor QCG0, the second transistor QCG1 and the third transistor QCG2 are turned on, the fourth conversion gain is obtained.

[0041] In some embodiments, the first transfer transistor TX0 and the second transfer transistor TX1 use a vertical transfer gate (VTG).

[0042] It should be noted that the embodiment of the present invention adopts a 3T structure design, specifically adopting a design in which the reset transistor RST, the transfer transistor TX (for example, the first transfer transistor TX0, the second transfer transistor TX1), the source follower transistor SF, and two photodiodes PD (for example, the first photodiode PD0, the second photodiode PD1) share an overflow drain, and the pixel signal PXD is directly output from the source of the source follower transistor SF. The existing image sensor adopts a 4T structure design, and the pixel signal is output from one end of the row selection transistor SEL. Therefore, the pixel unit of the embodiment of the present invention is different from the existing 4T structure design.

[0043] Figure 2 FIG. 4 is a graph showing the relationship between the pixel signal and the number of readout electrons during the readout period of an exemplary dual conversion gain image sensor pixel.

[0044] Figure 3 The figure is a curve showing the relationship between the pixel signal and the number of readout electrons during the readout period of a high dynamic image sensor pixel with multiple conversion gains according to an embodiment of the present invention.

[0045] Figure 2 and Figure 3 The corresponding readout signal intensity (digital number, DN) distributions within the same readout FWC range using the DCG scheme and the QCG scheme are shown respectively.

[0046] exist Figure 3 In the case of a signal in PD0 or PD1 that causes the readout signal to overflow, a lower conversion gain will be used automatically. For pixel designs with large FWC, in order to cover the entire FWC range, the low conversion gain needs to be set relatively small. Therefore, after entering the Gain 2 range, the rate at which DN increases with the number of electrons will decrease significantly. For example, in Figure 2 In the image, when the darkest and brightest light intensity distributions in an image correspond to points A and B in the figure, the brightness in the image is only distinguished by (NM) levels. Figure 3 When the QCG solution is used for reading, a conversion gain switch will occur at points A and B. Therefore, for the same brightness range, the corresponding brightness level can reach (DNsat-S) + (TP). Because the same FWC range is to be covered, it is assumed that Gain 2 in the DCG solution is equal to Gain 4 in the QCG solution. Since the slope of the Gain 3 curve in the QCG solution is obviously higher than that of Gain 2 in the DCG solution, for the same brightness range A~B, the DN value difference between point A and the gain conversion point C in the QCG solution is obviously greater than that in the DCG solution. Therefore, the image output by the QCG solution will contain more detailed brightness distinctions within the medium light intensity range and have more image details.

[0047] Figure 4 The present invention is a schematic diagram of a layout design of a high dynamic image sensor pixel unit with multiple conversion gains according to an embodiment of the present invention.

[0048] The pixel unit of an embodiment of the present invention includes a reset transistor RST, a source follower transistor SF, a first photodiode PD0, a first transfer transistor TX0, a first floating diffusion area FD0, a second photodiode PD1, a second transfer transistor TX1, a second floating diffusion area FD1, a first transistor QCG0, a second transistor QCG1, a third transistor QCG2, a first capacitor C0, a second capacitor C1, a third capacitor C2, a first active area AA1 and a second active area AA2.

[0049] The first photodiode PD0 and the second photodiode PD1 are arranged diagonally. The first active area AA1 and the second active area AA2 are arranged on both sides of the first photodiode PD0 and the second photodiode PD1, respectively. Specifically, the first active area AA1 is arranged in the upper left corner area of ​​the first photodiode PD0 and the second photodiode PD1; the second active area AA1 is arranged in the lower right corner area of ​​the first photodiode PD0 and the second photodiode PD1.

[0050] The reset transistor RST, the second transistor QCG1 and the third transistor QC2 are arranged in the first active area AA1; the source follower transistor SF is arranged in the second active area AA2; and the first transistor QCG0 is arranged between the first photodiode PD0 and the second photodiode PD1.

[0051] In some embodiments, the first capacitor C0 , the second capacitor C1 , or the third capacitor C2 may be a metal line capacitor or a metal-insulator-metal (MIM) capacitor.

[0052] In some embodiments, the source follower transistor SF may be a fin field effect transistor (FinFET).

[0053] It should be noted that the drawings are simplified and in non-precise proportions, and are only used to conveniently and clearly assist in explaining some embodiments of the present invention.

[0054] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in any way. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. The words first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A high dynamic range image sensor, characterized in that: include: Reset transistor; Source follower transistor; Overflow drain; a first photodiode; a first transfer transistor; a first floating diffusion region; a second photodiode; a second transfer transistor; a second floating diffusion region; The first photodiode and the second photodiode have different full well capacities; The first photodiode and the second photodiode share one overflow drain; The source of the source follower transistor outputs a signal.

2. The high dynamic range image sensor according to claim 1, wherein: The first transfer transistor and the second transfer transistor employ vertical transfer gates.

3. The high dynamic range image sensor according to claim 2, wherein: Also includes: The invention comprises at least three transistors and three corresponding capacitors to realize multiple conversion gains.

4. The high dynamic range image sensor according to claim 3, wherein: The three transistors include a first transistor, a second transistor and a third transistor; The first end of the first transistor is connected to the first floating diffusion area; the second end of the first transistor is connected to the second floating diffusion area and to the first end of the first capacitor; the second end of the first capacitor is grounded; The first end of the second transistor is connected to the second floating diffusion area; the second end of the second transistor is connected to the first end of the second capacitor; the second end of the second capacitor is grounded; The first end of the third transistor is connected to the second end of the second transistor; the second end of the third transistor is connected to the first end of the third capacitor; the second end of the third capacitor is grounded; The first end of the reset transistor is connected to the second end of the third transistor, and the second end of the reset transistor is connected to a power supply.

5. The high dynamic range image sensor according to claim 4, wherein: For the first floating diffusion area or the second floating diffusion area, the gates of the first transistor, the second transistor, the third transistor and the reset transistor are controlled so that the first floating diffusion area or the second floating diffusion area obtains a first, second, third or fourth conversion gain.

6. The high dynamic range image sensor according to claim 5, wherein: For the first floating diffusion region, Keeping the third transistor turned on and the reset transistor turned on, so that the first transistor provides a reset function for the first floating diffusion area, and when the first transistor is turned off, a first conversion gain is obtained; When the first transistor and the second transistor are turned off and the first transistor is turned on, a second conversion gain is obtained; When the third transistor is turned off, and the first transistor and the second transistor are turned on, a third conversion gain is obtained; When the first transistor, the second transistor, and the third transistor are turned on, a fourth conversion gain is obtained.

7. The high dynamic range image sensor according to claim 5, wherein: For the second floating diffusion region, Keeping the reset transistor turned on, so that the third transistor provides a reset function for the second floating diffusion area, and obtaining a first conversion gain when the first transistor and the second transistor are turned off; When the second transistor and the third transistor are turned off and the first transistor is turned on, a second conversion gain is obtained; When the third transistor is turned off, and the first transistor and the second transistor are turned on, a third conversion gain is obtained; When the first transistor, the second transistor, and the third transistor are turned on, a fourth conversion gain is obtained.

8. A pixel unit of a high dynamic range image sensor, characterized in that: The pixel unit comprises: Reset transistor; Source follower transistor; a first photodiode; a first transfer transistor; a first floating diffusion region; a second photodiode; a second transfer transistor; a second floating diffusion region; a first transistor, a second transistor, and a third transistor; a first capacitor, a second capacitor, and a third capacitor; a first active region and a second active region; wherein the first photodiode and the second photodiode are arranged diagonally; The first active region and the second active region are arranged on both sides of the first photodiode and the second photodiode respectively; The reset transistor, the second transistor and the third transistor are arranged in the first active area; The source follower transistor is arranged in the second active area; the source follower transistor is a fin field effect transistor; The first transistor is arranged between the first photodiode and the second photodiode; The first photodiode and the second photodiode have different full well capacities; The first photodiode and the second photodiode share an overflow drain; The source of the source follower transistor outputs a signal.

9. An electronic information device, characterized in that: Comprising the high dynamic range image sensor as claimed in any one of claims 1 to 7.

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