Method and control circuit for operating at least one power transistor to be switched on

Abstract

A method for steering at least one power transistor (T1, T2) to be switched on is provided. The method comprises applying a supply voltage (Vsup) to a first power transistor (T1), charging the first power transistor (T1) with a gate charging current (Ig), determining a switching-related transistor parameter of the first power transistor (T1) in response to the gate charging current (Ig), matching a steering profile for switching the first power transistor (T1) in accordance with the determined transistor parameter of the first power transistor (T1), and steering the first power transistor (T1) in accordance with the matched steering profile. Furthermore, a steering circuit for steering at least one power transistor (T1, T2) to be switched on is provided.

Description

Technical Field

[0001] The present invention relates to a method for controlling at least one power transistor to be switched and a control circuit for controlling at least one power transistor to be switched. Background Technology

[0002] If two power transistors operate, for example, in a half-bridge configuration and periodically turn on and off in opposite directions, switching losses are generated in one of the transistors depending on the direction of the flowing current. These losses, in addition to conduction losses and ohmic losses in the on-state, can significantly contribute to the total power loss.

[0003] To minimize switching losses in power transistors, efforts are made to switch the transistors as quickly as possible (i.e., turn them on and off with high du / dt). The available switching speed depends on a multitude of transistor parameters, such as the ratio of Vdsmax to the supply voltage, the parasitic inductance of the structure, and the inherent characteristics of the power transistor. Furthermore, the available switching speed can also depend on the characteristics of the control circuitry itself.

[0004] Many control circuits (also known as drive circuits or gate drive circuits) in production operate as the voltage source for the switch and adjust the gate charging current through an external resistor. Typically, two separate resistors are also provided for the charging current or the discharging current.

[0005] The new generation of existing control circuitry offers the possibility of adjusting the gate charging current via internal, programmable current sources. Depending on the number of programmable current sources and the phase controlled by the timer, the gate current used to achieve Vth, di / dt, du / dt, and charging to Vgsmax can be adjusted independently. This enables so-called gate shaping, thereby achieving improved switching behavior and reducing switching losses by matching the control parameters with edge conditions such as temperature, charging current, and transistor parameters.

[0006] When using existing voltage source drivers, the resistors must be selected for the worst-case scenario of the power transistor (e.g., cold temperatures, fast corners, maximum charging current) so that Vdsmax is not exceeded by dynamic voltage spikes caused by parasitic wire inductance at any operating point. Therefore, significantly higher switching losses must be accepted for all other operating points.

[0007] When using a current source driver, while it is possible to match the controlled current profile to the corresponding temperature and load current, the transistor distribution parameters are completely unknown in the application. This means that the circuit must be laid out on a "fast-turnaround" basis for the corresponding temperature, and for nominal or slow transistors, poor effective coefficients must be accepted despite temperature matching. However, improvements have been made compared to drivers that use resistor matching, as compensation for temperature behavior and load current behavior can, in principle, be achieved. Summary of the Invention

[0008] The method for controlling at least one power transistor to be switched according to the present invention essentially comprises the following steps: In step a), a supply voltage is applied to a first power transistor. In a further step b), the first power transistor is charged with a gate charging current. In a further step c), transistor parameters related to the switching of the first power transistor are determined in response to the gate charging current. In a further step d), an ansteuer profile for switching the first power transistor is matched according to the determined transistor parameters of the first power transistor. In a further step e), the first power transistor is controlled according to the matched ansteuer profile.

[0009] The power transistor is preferably an IGBT transistor or a SiC transistor, but the invention is not limited thereto. The control profile can be, for example, a gate charge current-time curve. Such a curve can be, for example, simulated or, however, a time-discrete sequence of gate current values ​​as a function of time. This control profile is variably adjustable over a time interval and can be matched based on separately measured transistor parameters. Switch-related transistor parameters are, for example, threshold voltage, transconductance gm = di / dt, capacitance Cgd, Cgs, Cds, or the corresponding gate charge, but the invention is not limited thereto.

[0010] The method according to the invention has the advantage of providing self-identification of individual transistor parameters. Furthermore, the invention is based on the understanding that the dispersion of the aforementioned transistor parameters (i.e., threshold voltage Vth, transconductance gm=di / dt, and capacitances Cgd, Cgs, Cds) can be compensated for by matching the control profile of the control circuit. Based on this, a matched, calibrated control profile can then be generated, which is adapted to the individual, measured transistor parameters. The control calibration can be calculated individually for each power transistor. Thus, even for nominal or slow-speed transistors (so-called slow rotation), switching losses can be reduced. For example, the matched control profile can make the first power transistor match the desired reference switching behavior. In the case of periodic switching with other power transistors, switching losses can thus be minimized: each individual power transistor matches the desired reference switching behavior. This synchronizes the switching behavior and reduces switching losses in such parallel operation.

[0011] Preferably, prior to step e), steps a) to c) are repeated for the second power transistor, which is electrically connected in parallel or series with the first power transistor. Here, step d) includes matching the control profiles of the first and second power transistors according to the determined transistor parameters of the first and second power transistors, and step e) includes controlling the second power transistor according to the control profile matched for this purpose. Thus, for example, two periodically, synchronously, or parallelly switched power transistors (such as, for example, two mutually oppositely switched power transistors) can be made symmetrical in their switching behavior. Here, in particular, this can be done directly relative to each other without reference switching behavior, since the matching of control profiles is based on the parameters of the two transistors. This also reduces switching losses and allows the parallel operation of the power transistors to be synchronized. In particular, the sequential execution of parallel-connected (drain and source) but separately controllable gate transistors is important for their switching balance.

[0012] In one particular embodiment, power transistors, connected in series or parallel, are connected to the supply voltage. Step a) includes turning on the second power transistor and then turning it off, such that the supply voltage is applied to the first power transistor. Furthermore, before repeating steps a) to d) for the second power transistor, the first power transistor is turned off, such that the supply voltage is applied to the second power transistor. Thus, a defined supply voltage can be applied to the first and second power transistors respectively. Based on this principle, individual power transistors can be measured sequentially under the same conditions, allowing for a reasonable comparison of transistor parameters.

[0013] Preferably, determining the switch-related transistor parameters includes identifying a first time point at which the power transistor is fully turned on, and further, determining the switch-related transistor parameters includes determining the gate charging current and the gate on-charge at the first time point. Here, the gate on-charge is a particularly important transistor parameter that allows for conclusions regarding the control profile to be used.

[0014] In one particular implementation, the determination of the switch-related transistor parameters includes determining a second time point at which the gate-source voltage reaches its maximum value during the turn-on process. Furthermore, the determination of the switch-related transistor parameters includes determining the corresponding gate charge based on the gate charging current and the determined second time point. This gate charge, up until the gate voltage is fully established away from the Miller-Plateau region, is also a sensitive parameter and allows conclusions to be drawn regarding the control profile to be used.

[0015] Preferably, the method for determining the switch-related transistor parameters includes sampling the gate voltage of the power transistor at a first time point, at which the power transistor is fully turned on. The method further includes determining a threshold voltage from the sampled gate voltage. The threshold voltage is another very important transistor parameter or a characteristic parameter used to determine the optimal control profile.

[0016] In a particular embodiment of the invention, the threshold voltage is determined during the first gate charging cycle, and wherein, during the second gate charging cycle (in which steps a) to d) are repeated, the switching-related transistor parameters of the first power transistor are determined in response to the gate charging current as follows: based on the threshold voltage determined in the first gate charging cycle, the gate-source charge and / or gate-drain charge are determined. Furthermore, the corresponding capacitance can also be determined from the known gate charging current, which is another particular transistor parameter for determining the control current. Here, two comparators with threshold voltages slightly below and slightly above the determined threshold voltage can be used to determine the start and end points for the Miller flattening region.

[0017] In one particular implementation, the determination of switch-related transistor parameters is performed at predetermined time intervals, further including a matching of the control profile after each determination. This allows for time-dependent matching of the control profile. For example, power transistors can change over time and can also change at varying speeds. Therefore, periodic determination enables flexible time-dependent matching, taking into account transistor parameter drift of individual transistor parameters, such as the temperature dependence of threshold voltage and the dependence of Miller flattening level on drain current.

[0018] Furthermore, a computer program product is provided for use, comprising instructions that, when executed by a computer, cause the computer to perform the method according to the embodiments described above. With such a program, parameter measurement and process control can be implemented on a microcontroller. In this case, the microcontroller can utilize hardware for control circuitry (such as controllable gate current sources, measurement units, etc.). It is also possible to perform the calculations necessary for matching the control profile on the same chip.

[0019] According to the present invention, a control circuit for controlling at least one power transistor to be switched is provided for use. Here, the control circuit includes a supply voltage applied to a first power transistor. Furthermore, the control circuit includes a controllable first current source configured to charge the first power transistor with a gate charging current. Furthermore, the control circuit includes a first measuring unit configured to determine transistor parameters related to the switching of the first power transistor in response to the gate charging current. Furthermore, the control circuit includes a control unit configured to match a control profile for switching the first power transistor according to the determined transistor parameters. Furthermore, the controllable first current source is configured to control the first power transistor according to the matched control profile. The advantages of the control circuit can be seen from the above-described embodiments of the method.

[0020] In one particular embodiment, the supply voltage of the control circuit is applied to a first power transistor and a second power transistor connected in parallel or series with the first power transistor. Furthermore, the control circuit includes a controllable second current source configured to charge the second power transistor with a gate charging current. In this embodiment, the control circuit also includes a second measurement unit configured to determine switching-related transistor parameters of the second power transistor in response to the gate charging current. Additionally, a control unit is included, configured to match a control profile for switching the first and second power transistors based on the determined transistor parameters. The controllable second current source is further configured to control the second power transistor according to the matched control profile.

[0021] Preferably, the measurement unit is configured to determine a first time point at which the power transistor is fully turned on, and wherein the control unit is configured to determine the gate-on charge based on the gate charging current and the determined first time point. The measurement unit may include a first comparator, a first input of which is connected to the drain terminal of the power transistor, and a first threshold voltage is applied to a second input of the first comparator. Furthermore, the measurement unit may be configured to generate an indicative first time signal for the first time point (at which the drain-source voltage drops below the first threshold voltage) and send the first time signal to the control unit, wherein the control unit is configured to determine the gate-on charge based on the gate charging current and the first time point.

[0022] In a preferred embodiment, the measurement unit is configured to determine a second time point at which the gate-source voltage reaches its maximum value, wherein the control unit is configured to determine the gate charge based on the gate charging current and the second time point. For this purpose, the measurement unit may include a second comparator, the first input of which is connected to the gate junction of the power transistor, and a second threshold voltage is applied to the second input of the second comparator. The measurement unit is further configured to generate a second time signal indicating a time point at which the gate-source voltage has risen above the second threshold voltage, wherein the second threshold voltage is higher than a threshold voltage, and to send the second time signal to the control unit, wherein the control unit is configured to determine the gate charge based on the gate charging current and the second time point.

[0023] Preferably, the measurement unit is configured to sample the gate voltage of the power transistor at a first time point, at which the power transistor is fully turned on, and wherein the control unit is configured to determine a threshold voltage from the sampled gate voltage. The measurement unit includes a sampling circuit connected to the gate junction of the power transistor and the control unit, and furthermore, the measurement unit is configured to sample the gate voltage of the power transistor at the first time point (when the power transistor is fully turned on) and send a status signal indicating the sampled voltage value to the control unit, wherein the control unit is configured to determine the threshold voltage from the sampled gate voltage.

[0024] Advantageous extensions of the invention are given in the dependent claims and described in the specification. Attached Figure Description

[0025] Embodiments of the invention will be explained in more detail with reference to the drawings and the following description. The drawings illustrate: Figure 1 A control circuit for controlling at least one power transistor is shown according to an embodiment of the present invention. Figure 2 The illustration shows a method for controlling at least one power transistor according to one embodiment of the present invention. Figure 3 A schematic voltage-time curve of a power transistor supplied with voltage in response to a gate charging current is shown to illustrate the invention. Figure 4 An exemplary control profile for a power transistor is shown as a gate current-time graph. Figure 5 The simulation results are shown for different power transistors using the method according to the invention. Figure 6 This illustration shows a control circuit for controlling at least one power transistor according to another embodiment of the present invention. Figure 7 The diagram illustrates a control circuit according to another embodiment of the present invention. Figure 8 A schematic voltage-time curve of a power transistor supplied with voltage in response to gate charging current during the first and second gate charging cycles is shown to illustrate the invention. Detailed Implementation

[0026] exist Figure 1 The diagram shows a control circuit 10 for controlling at least one power transistor T1, T2 according to an embodiment of the present invention. Figure 2 The diagram schematically illustrates corresponding methods for controlling at least one power transistor T1, T2 according to an embodiment of the present invention. Furthermore, in Figure 3 The figures show voltage-time curves of power transistors T1 and T2 in response to the gate charging current to illustrate the invention with respect to the measurements disclosed herein. The three figures will now be described together for better illustration.

[0027] Figure 1 A control circuit 10 according to one embodiment of the present invention is shown. In the current example, two power transistors T1 and T2 are provided, but the invention is not limited thereto. Here, the power transistors T1 and T2 are preferably IGBTs. Here, the control circuit 10 in this exemplary embodiment includes a first control sub-circuit connected to the first power transistor T1 and a second control sub-circuit connected to the second power transistor T2. The first control sub-circuit and the second control sub-circuit are constructed substantially equivalently. In another simple embodiment of the invention (which is not explicitly shown here), the control circuit 10 includes only the first control sub-circuit connected to the first power transistor T1 and does not include the second power transistor T2.

[0028] The control circuit 10 includes a supply voltage Vsup. When the second power transistor T2 is turned on, the supply voltage Vsup is applied to the load node N1 (not explicitly shown here) between the power transistors T1 and T2. This charges the load node N1 at the defined voltage Vsup. Then, the supply voltage Vsup is applied to the drain terminal of the first power transistor T1.

[0029] In another embodiment of the invention (not explicitly shown here, in which a second power transistor T2 is not provided), the supply voltage Vsup can be applied directly to the drain terminal of the first power transistor T1, and pre-on (Vorschalten) is not important. The source terminal is preferably grounded here and hereinafter. The application of the supply voltage Vsup to the first power transistor T1 or the provision of a voltage corresponding to the... Figure 2 Step a. Vsup can be, for example, 200V, but the invention is not limited thereto.

[0030] Furthermore, a controllable first current source I1 is provided. This controllable current source I1 is configured to charge the first power transistor T1 with a gate charging current Ig. Preferably, a constant gate charging current I1 (e.g., 10mA) is used here, but the invention is not limited thereto. Charging the first power transistor T1 with the gate charging current Ig corresponds to... Figure 2 Step b. In response to the charging process, a characteristic voltage change curve for the first power transistor T1 is generated in response to the gate charging current Ig, the characteristic voltage change curve being in Figure 3 As shown in the example.

[0031] Furthermore, the control circuit 10 includes a first measurement unit configured to determine, in response to the gate charging current Ig, transistor parameters related to the switching of the first power transistor T1. In further description and in conjunction with... Figure 3 The measurement unit implemented herein in the preferred embodiment will be described in more detail in connection with this description. Here, the switch-related transistor parameters may be, for example, the threshold voltage Vth, the gate charge Qg1, or the transconductance gm = di / dt, wherein the invention is not limited thereto. Here, the determination of the switch-related transistor parameters of the first power transistor T1 corresponds to... Figure 2 Step c in the process.

[0032] Furthermore, a control unit 21 is provided, which is configured to match a control profile for switching the first power transistor T1 according to the obtained transistor parameters. The matching of the control profile for switching the first power transistor T1 according to the obtained transistor parameters corresponds to... Figure 2 Step d in the process. Here, matching the control profile may include the initial creation of a control profile for switching the first power transistor T1 or a correction of a previous control profile. Here, the control profile is preferably a gate current-time curve (that is, a single control profile of the gate current intensity Ig as a function of time), and an exemplary embodiment of the invention is also seen. Figure 4 .

[0033] Furthermore, a controllable first current source I1 is configured to control the first power transistor T1 according to a matched control profile. For this purpose, for example, the control unit 21 can send a control signal 23 to the controllable current source I1, which in turn responsively generates a corresponding gate current for switching the first power transistor T1. Here, the first power transistor T1 is controlled according to the matched power transistor T1 to switch the first power transistor T1 accordingly. Figure 2 Step e in the text. Up to this point, the description so far has depicted an embodiment of the invention itself. Here, the matching of the control profile can be performed, for example, against a reference power transistor, so that the first power transistor T1 obtains the desired switching behavior through the matched control profile. This self-identification of individual transistor parameters can generate a matched, corrected control profile adapted to the individual, measured transistor parameters. Thus, the parallel, synchronous operation of the power transistors can be improved. Typical applications here and below include, for example, inverters or bridge circuits (such as half-bridge or full-bridge).

[0034] Furthermore, in this exemplary embodiment, the control circuit 10 includes applying a supply voltage Vsup in parallel to a first power transistor T1 and a second power transistor T2 connected in series with the first power transistor T1. In other embodiments, the power transistors may be connected in parallel. Here, a load node N1 may be provided between the first power transistor and the second power transistors T1 and T2, and a load (not shown here) may be connected to this load node N1.

[0035] In this embodiment, the control circuit 10 further includes a controllable second current source I2, configured to charge the second power transistor T2 with a gate charging current Ig. Additionally, a second measurement unit is provided, configured to determine the switching-related transistor parameters of the second power transistor T2 in response to the gate charging current Ig. Furthermore, the control circuit 10 includes control units 21 and 22, configured to match a control profile for switching the first and second power transistors T1 and T2 based on the determined transistor parameters of the first and second power transistors T1 and T2. For this purpose, for example, control units 21 and 22 can exchange the detected transistor parameter values ​​via an exchange signal 25. Alternatively, a common control unit can be used instead of two separate control units, which thus obtain information on the two determined transistor parameters. Therefore, the current embodiment achieves mutual balancing of the switching behavior of power transistors T1 and T2. This reduces switching losses during synchronous or parallel operation of the two power transistors T1 and T2. The parallel operation of power transistors T1 and T2 is thus synchronized. This can be done in particular without reference switch behavior, but directly relative to each other, since the matching of the control profiles is based on the parameters of the two transistors.

[0036] A controllable second current source I2 can be correspondingly configured to control the second power transistor T2 according to a matched control profile. The invention includes the possibility of matching the control profile of only one of the two power transistors T1 and T2. In other cases, both control profiles can be matched. In still other cases, when the transistor parameters are equal or nearly equal, matching may not be necessary because synchronized operation is already sufficiently achieved.

[0037] In this method, this corresponds to the repetition of steps a to c for the second power transistor T2, which is electrically connected in series with the first power transistor T1, prior to step e, wherein step d) includes matching the control profiles of the first power transistor T1 and the second power transistor T2 according to the transistor parameters obtained for the first power transistor and the second power transistor T1, T2. Furthermore, step e) can then be performed for the second power transistor, i.e., controlling the second power transistor T2 according to the control profile matched for this purpose. To perform the corresponding measurement with the same defined supply voltage Vsup, the second power transistor T2 is turned on and then turned off before step a), such that the supply voltage Vsup is applied to the first power transistor T1. Before repeating steps a) to d) for the second power transistor T2, the first power transistor T1 is turned off, such that the supply voltage Vsup is applied to the second power transistor T2, which is now to be measured. With the prior turning on of T1, the load node N1 has been pulled to ground.

[0038] The preferred embodiment of the measuring unit will now be described in more detail using the current control circuit 10 as an example.

[0039] The measurement unit can be configured to determine a first time point t1, at which power transistors T1 and T2 are fully turned on. Figure 3 In this case, when the drain-source voltage Vds drops sufficiently, it corresponds to complete switching on.

[0040] First, during charging with the gate charging current Ig, almost only the gate-drain capacitance Cgd charges until the gate-source voltage Vgs reaches the threshold voltage Vth. From the threshold voltage Vth onwards, the gate-source voltage Vgs remains maximally (i.e., almost) constant, a region known as the Miller flattening. Within this time period, the capacitor Cgd is recharged; see [link to relevant documentation]. Figure 3 .

[0041] To determine the first time point t1, the measurement unit preferably includes a first comparator K1. Here, as in... Figure 1 As shown, the first positive input terminal can be connected to the drain terminals of power transistors T1 and T2; for the first power transistor, this corresponds to load node N1. A first threshold voltage V1 is applied to the negative input terminal.

[0042] Furthermore, the first comparator K1 can be connected to the control units 21 and 22 on its output side. Additionally, the first comparator K1 can be configured to generate a first time signal st1 indicative of a first time point t1, at which time point t1, the drain-source voltage Vds drops below a first threshold voltage V1. (See also...) Figure 3 Accordingly, a first time signal st1 is sent to control units 21 and 22, so that the control units obtain time point t1.

[0043] Here, the first comparator K1 and voltage source V1 can be part of a DESAT circuit (also known as a desaturation circuit) to protect against short circuits in the switched-on power transistors. The first comparator and the voltage source are already pre-integrated as protection circuitry in various control circuits. Thus, advantageously, existing circuit architectures can be used. In the current embodiment, a current source I and a protection diode D1 are also provided, which protect the first comparator K1 from high current.

[0044] Furthermore, control units 21 and 22 are configured to calculate the gate charge Qg1 = Qgs + Qgd based on the gate charging current Ig and the first time point t1. This can also be intuitively explained by seeing... Figure 3 The gate charge Qg1 can be calculated by control units 21 and 22 using Qg1 = Ig * t1. Therefore, this parameter can be provided to match the control profile.

[0045] Furthermore, the measurement unit can be configured to determine a second time point t2, at which the gate-source voltage Vgs reaches its maximum value Vgsmax. For details, see [link to relevant documentation]. Figure 3 The following region is defined in the region where the voltage Vgs rises from the Miller flat region up to the maximum gate-source voltage Vgsmax.

[0046] For this purpose, the measurement unit may include a second comparator K2. The first input terminal of the second comparator K2 may be connected to the gate junction of power transistors T1 and T2. As shown in this embodiment, a second threshold voltage V2 may be applied to the second input terminal.

[0047] In addition, such as in Figure 1 As can be seen by example, the second comparator K2 is connected to the control units 21 and 22 on the output side. Here, the second comparator K2 is further configured to generate a second time signal st2 indicative of a second time point t2, at which time point t2 the gate-source voltage Vgs rises above a second threshold voltage V2. This is also seen in... Figure 3 The second threshold voltage V2 is above the threshold voltage Vth.

[0048] Furthermore, the second comparator K2 is configured to send a second time signal st2 to the control units 21 and 22. Additionally, the control units 21 and 22a are configured to calculate the corresponding gate charge Qg2 based on the gate charging current Ig and the second time point t2. This can be performed according to the equation Qg2 = Ig * t2.

[0049] Furthermore, the measurement unit may include a sampling circuit 30. Here, the sampling circuit 30 may be configured to sample the gate voltages of power transistors T1 and T2 at a first time point t1, at which power transistors T1 and T2 are fully turned on. For this purpose, the sampling circuit 30 may be connected to the gate terminals of power transistors T1 and T2 and to control units 21 and 22, i.e., inserted between the gate terminals and control units 21 and 22. Preferably, the sampling of the gate voltage may be performed using a sample-and-hold circuit 34. Furthermore, an A / D converter 36 may be included in the sampling circuit, which converts the sampled analog signal into a discrete signal. The sampling circuit 30 may then send a status signal 32 to control units 21 and 22, which is indicative of the sampled voltage value. Control units 21 and 22 may also be configured to determine a threshold voltage Vth from the sampled gate voltage. Therefore, advantageously, the transistor parameters may also be available to control units 21 and 22 for matching control profiles.

[0050] The measured transistor parameters can be stored in a multidimensional composite characteristic curve, including parameters such as temperature and gate charging current, and then the control circuit can access the obtained parameters.

[0051] The switching-related transistor parameters can be calculated at defined time intervals. Furthermore, this includes matching the control profile after each calculation. Thus, parameter drift of the transistor parameters can be determined, and therefore the matching of the control profile can be appropriately considered.

[0052] Preferably, during parameter determination, the load applied to load node N1 should not be subject to current flow; that is, the load must be able to switch to high resistance on the load side, as is possible, for example, in a full-bridge configuration. This requires, for example, that the described method be performed during startup before load activation or during the system's inertial operation phase after load shutdown.

[0053] exist Figure 4An exemplary control profile of power transistors 21 and 22 is shown. The control profile corresponds to a gate current-time graph with time-discrete current values. In this example, after the gate current Ig is turned on in a first time interval, the gate current decreases in a second time interval and then gradually increases again. Then, from the fourth time interval onwards, the maximum gate current is provided.

[0054] The current value can be adjusted accordingly and matched individually for each power transistor T1, T2 according to the previous description. Matching can be particularly suitable by means of discrete values. However, the invention is not limited thereto. Essentially, simulated (i.e., time-continuous) gate current-time curves are also included in the invention as control profiles.

[0055] exist Figure 5 The diagram shows simulation results of the electrical response behavior of three different power transistors T1, T2, and T3 to gate current, using the method according to the invention. Here, the time-varying curves of the gate-source voltage Vgs and drain-source voltage Vds are shown as the gate junctions of the respective power transistors T1, T2, and T3 are charged.

[0056] In the current example simulation, the gate charging current Ig is tuned to 10mA. A 100kΩ resistor is used as the drain-pull-up resistor for the corresponding power transistor, based on the 800V supply voltage Vsup.

[0057] As explained above, the first time point t1 is measured using the first comparator K1. As explained above, the first comparator K1 can be a comparator in a DESAT circuit. In the current example, the first threshold voltage V1 is specified as 8V. The drain-source voltages Vds1, Vds2, and Vds3 (see also...) decrease in response to the gate charging current. Figure 3 The intersection points of the first threshold value V1 and the first threshold value V1 are defined by time points t1-1, t1-2, and t1-3 determined by the first comparator K1, and these time points are obviously different.

[0058] Then, at these time points t1-1, t1-2, and t1-3, the threshold voltages Vth1, Vth2, and Vth3 of the corresponding power transistors (which in this figure can also be viewed as the flat region voltages of the gate-source voltages Vgs1, Vgs2, and Vgs3) are obtained by the sampling circuit 30, especially the sample-and-hold circuit 32 as described above, and converted by means of an AD converter. The threshold voltages Vth1, Vth2, and Vth3 also differ significantly depending on the power transistor.

[0059] Furthermore, it is also clear that the times t2-1, t2-2, and t2-3 indicating when the gate-source voltage leaves the Miller flat region or reaches its maximum value Vgsmax are significantly different, which can be determined by means of the second comparator K2, as explained above.

[0060] Clearly, power transistor T1 is a fast-switching transistor (here, a SiC transistor). Power transistor T2 is a nominal switching transistor. Clearly, power transistor T3 is a slow-switching transistor. The first power transistor T1 has the determined transistor parameters Qg1-1=Qgs+Qgd=10mA*4.56μs=45.6nAs and Vth1=5.53V, the second power transistor T2 has the determined transistor parameters Qg1-2=Qgs+Qgd=10mA*6.05µs=60.5nAs and Vth2=5.31V, and the third power transistor has the determined transistor parameters Qg1-3=Qgs+Qgd=10mA*7.80µs=78.0nAs and Vth3=6.06V. These transistor parameters are clearly important for different turn-on behaviors and can be directly used to determine the control profile of each power transistor T1, T2, T3.

[0061] exist Figure 6 The diagram illustrates another embodiment of the invention. In this embodiment, a method is constructed relative to... Figure 1 A more complex circuit topology, comprising six power transistors T1, T2, T3, T4, T5, and T6. An exemplary circuit topology corresponds to the B6 bridge circuit.

[0062] Here, the control circuit includes six power transistors T1, T2, T3, T4, T5, and T6. The first and second transistors T1 and T2 form a first pair and are connected in parallel with the supply voltage Vsup. This essentially corresponds to... Figure 1 The contents are shown in the diagram. Furthermore, however, the third and fourth power transistors T3 and T4 are also connected in parallel with the supply voltage Vsup and capacitor C, as are the fifth and sixth power transistors T5 and T6. Load nodes N1, N2, or N3 are exemplarily positioned between pairs of power transistors, with inductive loads L1, L2, and L3 electrically connected to said load nodes. On the output side, each load L1, L2, and L3 is interconnected via a common output node Nx.

[0063] First, all power transistors T1, T2, T3, T4, T5, and T6 are turned off, and correspondingly, the second power transistor T2 is also turned off. All load nodes N1, N2, and N3 are pre-charged by briefly turning on half-bridges T2, T4, and T6. Then, one or more power transistors T2, T4, and T6 of the half-bridge are turned off again. The method flow (steps a to d) for determining transistor parameters described above is applied to power transistors, such as T1. The measured power transistor T1 is then turned off. Steps a to d are repeated until all power transistors T1, T2, T3, T4, T5, and T6 of the B6 bridge have been measured. Here, the control circuit 10 is only symbolically shown as controllable current sources I1, I2, I3, I4, I5, and I6, which controllable current sources operate the corresponding power transistors to switch on and off based on the measured transistor parameters, as previously described. For its detailed route layout (Beschaltung), see [link to Beschaltung]. Figure 1 And the description of what it belongs to.

[0064] Essentially, this invention is not limited to a specific topology. Transistor parameter determination can also be applied to higher power level switching networks, such as in full-bridge topologies.

[0065] Figure 7 and Figure 8 The following diagram illustrates the invention in a schematic voltage-time curve of the control circuit 10 according to another embodiment of the invention, and the power transistor supplied with voltage in response to the gate charging current during the first and second gate charging cycles.

[0066] In this embodiment of the control circuit 10, the threshold voltage Vth is determined during the first gate charging cycle, as also seen in [reference needed]. Figure 8 The left side. This is as follows: Figure 1 The operation is performed as described in the control circuit 10.

[0067] In the second gate charge cycle (see...) Figure 8 In the right part), repeat steps a) to d). Here, the determination of transistor parameters related to the switching of the first power transistor T1 in response to the gate charging current Ig includes the determination of the gate-source charge Qgs and / or gate-drain charge Qgd based on the threshold voltage Vth determined in the first gate charging cycle. For this purpose, in addition to Figure 1In addition to the embodiment shown, the control circuit 10 includes a third comparator K3 and a fourth comparator K4, which are connected to the gate junction of the first power transistor T1. Here, the third comparator K3 has a threshold voltage slightly higher than the threshold voltage Vth determined in the first gate charging cycle (e.g., Vth + 0.5V), and the fourth comparator K4 has a threshold voltage slightly lower than the threshold voltage Vth determined in the first gate charging cycle (e.g., Vth - 0.5V). Therefore, the fourth comparator K4 generates a fourth time signal st4 on the output side that indicates the time point t3a when the Miller flat region is reached, see... Figure 8 The right-hand side. Therefore, the third comparator K3 generates a third time signal st3 indicative of the time point t3b leaving the Miller flat region, see... Figure 8 The right-hand side. These time signals st3, st4 are transmitted to control unit 21. The threshold voltage Vth, or a threshold value deviating from it, can be transmitted as an analog signal to comparators K3, K4, for example, via digital-to-analog converter 38. Now, from these time points t3a and t3b and therefore according to the threshold voltage Vth, the gate-source charge Qgs (Qgs≈Ig*t3a), gate-drain charge Qgd≈Ig(t3b-t3a), charge Qon≈Ig*(t2-t3b), and Cgs≈Qgs / Vth can be determined, all with the gate charging current Igs known. Here, time point t2 corresponds to the time point at which Vgs = Vgsmax - 0.5V (i.e., slightly below the maximum value). This can be achieved by means of... Figure 1 The second comparator K2 shown has a corresponding threshold voltage for detection. An advantage of this implementation is that additional charging parameters of the power transistor can be determined.

Claims

1. A method for controlling at least one power transistor to be switched, the method comprising the steps of: a) Apply the supply voltage (Vsup) to the first power transistor (T1); b) Charge the first power transistor (T1) with the gate charging current (Ig); c) Determine the switching-related transistor parameters of the first power transistor (T1) in response to the gate charging current (Ig); d) Match the control profile for switching the first power transistor (T1) according to the obtained transistor parameters of the first power transistor (T1); e) Control the first power transistor (T1) according to the matched control profile. The switch-related transistor parameters are characterized in that the threshold voltage (Vth) is included, wherein the determination of the switch-related transistor parameters includes sampling the gate voltage of the first power transistor (T1) at a first time point (t1), at which the drain-source voltage (Vds) drops below a first threshold voltage (V1), wherein the sampled gate voltage corresponds to the threshold voltage (Vth) of the first power transistor (T1).

2. The method according to claim 1, wherein, Before step e), steps a) to c) are repeated for a second power transistor (T2) electrically connected in parallel or in series with the first power transistor (T1), wherein step d) includes matching the control profiles of the first power transistor (T1) and the second power transistor (T2) according to the obtained transistor parameters of the first power transistor (T1) and the second power transistor (T2), and step e) includes also controlling the second power transistor (T2) according to the control profile matched for this purpose.

3. The method according to claim 2, wherein, The first power transistor (T1) and the second power transistor (T2) connected in parallel or in series are connected to the supply voltage (Vsup), wherein step a) further includes turning on the second power transistor (T2) and then turning off the second power transistor (T2) so that the supply voltage (Vsup) is applied to the first power transistor (T1), and before repeating steps a) to d) for the second power transistor (T2), the first power transistor (T1) is turned off so that the supply voltage (Vsup) is applied to the second power transistor (T2).

4. The method according to any one of claims 1 to 3, wherein, The determination of the switch-related transistor parameters includes determining a first time point (t1), at which the first power transistor (T1) is fully turned on, and the determination of the switch-related transistor parameters also includes determining the gate charge (Qg1) based on the gate charging current (Ig) and the first time point (t1).

5. The method according to claim 2 or 3, wherein, The determination of the switch-related transistor parameters includes determining a first time point (t1), at which the second power transistor (T2) is fully turned on, and the determination of the switch-related transistor parameters also includes determining the gate charge (Qg1) based on the gate charging current (Ig) and the first time point (t1).

6. The method according to any one of claims 1 to 3, wherein, The determination of the switch-related transistor parameters includes determining a second time point (t2), at which the gate-source voltage (Vgs) reaches its maximum value (Vgsmax) during the turn-on process. The determination of the switch-related transistor parameters also includes determining the corresponding gate charge (Qg2) based on the gate charging current (Ig) and the second time point (t2).

7. The method according to any one of claims 1 to 3, wherein, The threshold voltage (Vth) is determined in the first gate charging cycle, wherein, in the second gate charging cycle which repeats steps a) to d), the switching-related transistor parameters of the first power transistor (T1) are determined in response to the gate charging current (Ig) as follows: the gate-source charge (Qgs) and / or the gate-drain charge (Qgd) are determined based on the threshold voltage (Vth) determined in the first gate charging cycle.

8. The method according to claim 7, wherein, Determining the gate-drain charge (Qgd) based on the threshold voltage (Vth) obtained in the first gate charging cycle includes: defining a threshold of the gate voltage that is slightly lower than the obtained threshold voltage (Vth) and defining a threshold of the gate voltage that is slightly higher than the obtained threshold voltage (Vth); detecting a fourth time point (t3a) when the gate voltage reaches the threshold of the gate voltage that is slightly lower than the obtained threshold voltage (Vth) and a third time point (t3b) when the gate voltage reaches the threshold of the gate voltage that is slightly higher than the obtained threshold voltage (Vth); and determining the gate-drain charge (Qgd) based on the detected fourth time point (t3a) and the detected third time point (t3b) and the gate charging current.

9. The method according to claim 7, wherein, Determining the gate-source charge (Qgs) based on the threshold voltage (Vth) obtained in the first gate charging cycle includes: defining a threshold of the gate voltage that is slightly lower than the obtained threshold voltage (Vth); detecting a fourth time point (t3a) at which the gate voltage reaches the threshold of the gate voltage that is slightly lower than the obtained threshold voltage (Vth); and determining the gate-source charge (Qgs) based on the determined fourth time point (t3a) and the gate charging current.

10. The method according to any one of claims 1 to 3, wherein, The method involves obtaining transistor parameters related to the switch at defined time intervals, and further includes matching the control profile after each obtaining.

11. A computer program product comprising instructions that, when executed by a computer, cause the computer to perform the method according to any one of claims 1 to 10.

12. A control circuit (10) for controlling at least one power transistor to be switched. - Supply voltage (Vsup), which is applied to the first power transistor (T1); - A controllable first current source (I1), the controllable first current source (I1) being configured to charge the first power transistor (T1) with a gate charging current (Ig); - A first measurement unit, configured to determine the switching-related transistor parameters of the first power transistor (T1) in response to the gate charging current (Ig); - Control unit (21, 22), the control unit (21, 22) being configured to match an operating profile for switching the first power transistor (T1) according to the obtained transistor parameters; and - The controllable first current source (I1) is further configured to control the first power transistor (T1) according to a matched control profile. Its features are, The switch-related transistor parameters include a threshold voltage (Vth), wherein the first measurement unit includes a first sampling circuit (30), which is configured to sample the gate voltage of the first power transistor (T1) at a first time point (t1), at which the drain-source voltage (Vds) drops below a first threshold voltage (V1), wherein the sampled gate voltage corresponds to the threshold voltage (Vth) of the first power transistor (T1).

13. The control circuit (10) according to claim 12, wherein, The supply voltage (Vsup) is also applied to the first power transistor (T1) and the second power transistor (T2) connected in parallel or in series with the first power transistor (T1). The control circuit (10) further includes: - A controllable second current source (I2), the controllable second current source (I2) being configured to charge the second power transistor (T2) with a gate charging current (Ig); - A second measurement unit, configured to determine the switching-related transistor parameters of the second power transistor (T2) in response to the gate charging current (Ig); - Control unit (21, 22), the control unit (21, 22) is configured to match an operation profile for switching the first power transistor (T1) and the second power transistor (T2) according to the obtained transistor parameters of the first power transistor (T1) and the second power transistor (T2); - Wherein, the controllable second current source (I2) is configured to control the second power transistor (T2) according to a matched control profile.

14. The control circuit (10) according to any one of claims 12 to 13, wherein, The first measurement unit is configured to determine a first time point (t1), at which the first power transistor (T1) is fully turned on, wherein the control unit (21, 22) is configured to calculate the gate charge (Qg1) based on the gate charging current (Ig) and the determined first time point (t1).

15. The control circuit (10) according to claim 13, wherein, The second measurement unit is configured to determine a first time point (t1) at which the second power transistor (T2) is fully turned on, wherein the control unit (21, 22) is configured to calculate the gate charge (Qg1) based on the gate charging current (Ig) and the determined first time point (t1).

16. The control circuit (10) according to any one of claims 12 to 13, wherein, The first measurement unit is configured to determine a second time point (t2) at which the gate-source voltage (Vgs) reaches its maximum value (Vgsmax). The control unit (21, 22) is configured to calculate the gate charge (Qg2) based on the gate charging current (Ig) and the second time point (t2).

17. The control circuit (10) according to claim 13, wherein, The second measurement unit is configured to determine a second time point (t2) at which the gate-source voltage (Vgs) reaches its maximum value (Vgsmax). The control unit (21, 22) is configured to calculate the gate charge (Qg2) based on the gate charging current (Ig) and the second time point (t2).

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