Logic synthesis method, device, electronic device, medium and chip for integrated circuit

Abstract

The present disclosure provides a logic synthesis method, apparatus, electronic device, medium and chip for an integrated circuit, wherein the method comprises: determining a module connection relationship between sub-modules in the integrated circuit; determining target position constraint information for each sub-module based on the module connection relationship; the target position constraint information is used to control the module position of each sub-module in a preset panel area; and performing logic synthesis processing on standard library units in each sub-module of the integrated circuit based on the target position constraint information to obtain a logic synthesis result.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip design, and in particular to a logic synthesis method, device, electronic device, medium, and chip for an integrated circuit. Background Art

[0002] With the rise of big data and various artificial intelligence algorithms, the demand for chip computing power is increasing, while also maintaining high energy efficiency and achieving the ultimate PPA (Power / Performance / Area) indicator. In digital circuits, a minimum physical block processed by a chip's implementation process typically consists of multiple submodules, each of which typically contains a large number of standard library cells. In related logic synthesis technologies, improper placement of submodules can easily lead to improper layout of standard library cells within each submodule, resulting in poor timing constraints between standard library cells, increased chip power consumption and area, and, consequently, an inability to achieve a better PPA indicator. Summary of the Invention

[0003] The embodiments of the present disclosure at least provide a logic synthesis method, apparatus, electronic device, medium, and chip for an integrated circuit.

[0004] In a first aspect, an embodiment of the present disclosure provides a logic synthesis method for an integrated circuit, wherein the integrated circuit includes multiple sub-modules, including: determining a module connection relationship between the sub-modules in the integrated circuit; determining target position constraint information of each of the sub-modules based on the module connection relationship; the target position constraint information is used to control the module position of each sub-module in a preset panel area; and performing logic synthesis processing on standard library units in each of the sub-modules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result.

[0005] As can be seen from the above description, by determining positional constraints based on the module connection relationships between submodules, it is possible to control the module positions within the preset panel area, thereby improving the rationality of the submodule layout. When performing logic synthesis on the annotated library cells of each submodule based on this positional constraint information, it provides a better starting point for the placement of standard library cells, thereby obtaining a more comprehensive logic synthesis result and achieving a better PPA indicator.

[0006] In an optional embodiment, the target position constraint information of each sub-module is determined based on the module connection relationship, including: determining the relative orientation information of each sub-module in the preset panel area based on the module connection relationship; determining the preset module area of ​​each sub-module; and determining the target position constraint information of each sub-module based on the relative orientation information and the preset module area.

[0007] In an optional embodiment, the target position constraint information of each sub-module is determined based on the relative orientation information and the preset module area, including: determining the module position of each sub-module in the preset panel area based on the relative orientation information and the preset module area; and determining the module position as the target position constraint information of the corresponding sub-module.

[0008] In the above embodiment, the relative position information can be used to accurately determine the approximate position of each submodule, and the preset module area can be used to determine the occupied area of ​​the submodule within the preset panel area. By combining the preset module area and the relative position information, the target position constraint information of each submodule can be more accurately determined.

[0009] In an optional embodiment, the logic synthesis processing is performed on the standard library units in each of the sub-modules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result, including: determining the module position of each of the sub-modules in the preset panel area according to the target position constraint information, and laying out the standard library units in each of the sub-modules based on the module position to obtain a first layout result; adjusting the first layout result based on timing constraints to obtain a second layout result that satisfies the timing constraints; and determining the second layout result as the logic synthesis result.

[0010] In the above embodiment, after obtaining the first layout result, by adjusting the layout information of the standard library units in each submodule in the first layout result, the flexibility of the layout of the standard library units can be improved, thereby achieving a better PPA index.

[0011] In an optional embodiment, adjusting the first layout result based on the timing constraint to obtain a second layout result that satisfies the timing constraint includes: adjusting the layout positions of at least some standard library cells in the first layout result based on the timing constraint to obtain an adjusted result; if it is determined based on the adjustment result that the multiple sub-modules do not satisfy the timing constraint, determining a sub-module to be adjusted among the multiple sub-modules and determining new position constraint information for the sub-module to be adjusted; determining a new module position for the sub-module to be adjusted based on the new position constraint information, and placing the standard library cells in the sub-module to be adjusted based on the new module position to obtain a new first layout result; adjusting the layout positions of at least some standard library cells in the new first layout result based on the timing constraint to obtain a new adjusted result, and if the new adjusted result satisfies the timing constraint, determining the new adjusted result as the second layout result; otherwise, returning to the step of determining a sub-module to be adjusted among the multiple sub-modules and determining new position constraint information for the sub-module to be adjusted based on the new adjustment result.

[0012] In the above implementation, the logic synthesis time of each physical unit in the integrated circuit can be shortened, thereby improving the logic synthesis efficiency.

[0013] In an optional embodiment, determining the sub-module to be adjusted from the multiple sub-modules includes: determining a first type of sub-module that does not meet the timing constraint conditions from the multiple sub-modules, and determining a second type of sub-module associated with the first type of sub-module from the remaining sub-modules of the multiple sub-modules; wherein the module position of the second type of sub-module changes with the change of the module position of the first type of sub-module; and determining the sub-module to be adjusted based on the first type of sub-module and the second type of sub-module.

[0014] This processing method can reduce the workload in the logic synthesis process, thereby improving the efficiency of logic synthesis.

[0015] In an optional embodiment, determining the new position constraint information of the sub-module to be adjusted includes: determining multiple alternative module positions of the sub-module to be adjusted in the preset panel area based on the module connection relationship; determining a target alternative module position among the multiple alternative module positions, and determining the target alternative module position as the new position constraint information of the sub-module to be adjusted.

[0016] In the above embodiment, when the sub-module to be adjusted contains multiple alternative module positions, by updating the position constraint information of the adjustment sub-module based on the multiple alternative module positions, multiple layout methods can be provided for the physical unit, thereby maximizing the layout effect of the standard library unit.

[0017] In an optional embodiment, determining the new position constraint information of the sub-module to be adjusted includes: determining the actual delay time between the sub-modules to be adjusted based on the adjustment result; when it is determined based on the actual delay time that the sub-module to be adjusted meets the adjustment requirements, shortening the distance between the sub-modules to be adjusted, and determining the new position constraint information of the sub-module to be adjusted based on the module position of the sub-module to be adjusted after shortening the distance.

[0018] In the above embodiment, by adjusting the distance between the sub-modules to be adjusted by the actual delay time, the module position of each sub-module in the second layout result can be finely adjusted, thereby improving the flexibility of adjusting the module position of the sub-module and achieving a better PPA indicator.

[0019] In an optional embodiment, determining the module connection relationship between each sub-module in each integrated circuit includes: obtaining the RTL code file of the integrated circuit; extracting the connection file in the RTL code file, and determining the module connection relationship based on the extracted connection file, wherein the connection file contains the connection relationship between the module ports of each sub-module.

[0020] In the above implementation, by analyzing the RTL code file to obtain the module connection relationship, the module connection relationship between sub-modules can be quickly and accurately obtained, thereby improving the efficiency of logic synthesis while ensuring the accuracy of the target position constraint information.

[0021] In a second aspect, an embodiment of the present disclosure provides a logic synthesis device for an integrated circuit, wherein the integrated circuit includes multiple sub-modules, including: a first determination unit, used to determine the module connection relationship between the sub-modules in the integrated circuit; a second determination unit, used to determine the target position constraint information of each of the sub-modules based on the module connection relationship; the target position constraint information is used to indicate the module position of each sub-module in a preset panel area; and a logic synthesis unit, used to perform logic synthesis processing on the standard library units in each of the sub-modules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result.

[0022] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the above-mentioned first aspect or any possible implementation of the first aspect are performed.

[0023] In a fourth aspect, an embodiment of the present disclosure further provides a chip, which adopts the logic synthesis method of the integrated circuit as described in any one of the first aspects above to perform logic synthesis, and layouts and routes each sub-module of the integrated circuit based on the logic synthesis result.

[0024] In the fifty-fourth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned first aspect or any possible implementation of the first aspect are executed.

[0025] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without inventive effort.

[0027] Figure 1 A flow chart of a logic synthesis method for an integrated circuit provided by an embodiment of the present disclosure is shown;

[0028] Figure 2 A flowchart showing a specific method for determining module connection relationships between sub-modules in each integrated circuit in the logic synthesis method of the integrated circuit provided by the embodiment of the present disclosure is shown;

[0029] Figure 3 A flowchart showing a specific method for determining target position constraint information of each submodule based on module connection relationships in the logic synthesis method of an integrated circuit provided by an embodiment of the present disclosure is shown;

[0030] Figure 4 A connection diagram showing a module connection relationship between various sub-modules in a physical unit provided by an embodiment of the present disclosure;

[0031] Figure 5 A flowchart showing a specific method for performing logic synthesis processing on the standard library cells in each sub-module of the integrated circuit based on the target position constraint information to obtain a logic synthesis result in the logic synthesis method of the integrated circuit provided by the embodiment of the present disclosure is shown;

[0032] FIG6(a) shows a schematic diagram of a first layout result obtained after a first logic synthesis process under the constraints of position constraint information, provided by an embodiment of the present disclosure;

[0033] FIG6( b ) is a schematic diagram showing a second layout result obtained after performing a second logic synthesis process based on the first layout result while discarding position constraint information, provided by an embodiment of the present disclosure;

[0034] FIG7( a ) shows a schematic diagram of a connection relationship between two registers provided by an embodiment of the present disclosure;

[0035] FIG7( b ) shows a schematic diagram of a connection relationship between two registers after extending the connection distance between the two registers provided by an embodiment of the present disclosure;

[0036] Figure 8 A flowchart of another integrated circuit logic synthesis method provided by an embodiment of the present disclosure is shown;

[0037] Figure 9 A schematic diagram of a logic synthesis device for an integrated circuit provided by an embodiment of the present disclosure is shown;

[0038] Figure 10 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0041] The term "and / or" herein simply describes an association relationship, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, and the existence of B alone. In addition, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0042] Research has found that with the rise of big data and various artificial intelligence algorithms, the requirements for chip computing power are becoming increasingly higher, while also taking into account high energy efficiency to achieve the ultimate PPA (Power / Performance / Area) indicator.

[0043] To achieve this goal, the demand for customized chip implementation processes is increasing. The traditional chip implementation process includes processes such as RTL (Register Transfer Level) synthesis, netlist, layout, clock tree synthesis, and routing. Most of these processes are automated by EDA tools. However, in digital circuits, the smallest physical block processed by the chip implementation process typically contains 2-4 million standard library cells. During layout, EDA (Electronic Design Automation) tools are required to determine the location of each standard library cell, which is a very challenging task. Due to the large number of components in a chip and the limited processing power of EDA tools, EDA tools can pre-divide the chip into multiple modules during the chip implementation process. Each module is the smallest physical unit.

[0044] Each minimum physical unit contains 2-4 million standard library units. A large number of standard library units will affect the placement of each standard library unit in the minimum physical unit. Based on this, the EDA tool can divide the above minimum physical unit into different sub-module clusters, and then determine the approximate position of each sub-module cluster based on the fixed-position port or hard macro, and then place the standard library units in each sub-module cluster. Among them, the EDA tool can divide the minimum physical unit into different sub-modules according to the functions implemented by the minimum physical unit, or the EDA tool can also divide the minimum physical unit into multiple sub-modules according to a preset partitioning grid.

[0045] However, the inventors discovered that in some cases, EDA tools cannot effectively determine the placement of each submodule cluster. Improper planning of the submodules can lead to poor timing constraints after the layout of all standard library cells. This poor timing leads to increased power consumption and area, preventing the chip from achieving optimal PPA.

[0046] Based on the above research, the present disclosure provides a logic synthesis method, apparatus, electronic device, medium, and chip for an integrated circuit. In an embodiment of the present disclosure, the module connection relationships between the various submodules in the integrated circuit are first determined. Position constraint information for controlling the module position of each submodule within a predetermined panel area is then determined based on the module connection relationships. Subsequently, logic synthesis processing is performed on the standard library cells within the submodules of the integrated circuit based on the target position constraint information, thereby obtaining a logic synthesis result.

[0047] As can be seen from the above description, by determining positional constraints based on the module connection relationships between submodules, it is possible to control the module positions within the preset panel area, thereby improving the rationality of the submodule layout. When performing logic synthesis on the annotated library cells of each submodule based on this positional constraint information, it provides a better starting point for the placement of standard library cells, thereby obtaining a more comprehensive logic synthesis result and achieving a better PPA indicator.

[0048] To facilitate understanding of this embodiment, a logic synthesis method for an integrated circuit disclosed in the embodiment of the present disclosure is first introduced in detail. The execution subject of the logic synthesis method for an integrated circuit provided in the embodiment of the present disclosure is generally an electronic device with certain computing capabilities.

[0049] See also Figure 1 FIG. 1 is a flow chart of a logic synthesis method for an integrated circuit provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S105, wherein:

[0050] S101: Determine a module connection relationship between sub-modules in the integrated circuit.

[0051] In the embodiment of the present disclosure, the integrated circuit may be pre-divided into a plurality of physical units, wherein the physical unit may be understood as a minimum physical unit (physical block) processed by the integrated circuit implementation process, and each physical unit includes a plurality of submodules.

[0052] Here, the submodules described in step S101 may be module connection relationships between the submodules in each physical unit in the integrated circuit. The module connection relationship is used to represent the connection relationship between the module ports of the submodules in each physical unit, where the module ports include module input ports and module output ports.

[0053] Based on this, in the embodiment of the present disclosure, the module connection relationship may be determined based on the connection relationship between the module ports of each sub-module in each physical unit in the integrated circuit.

[0054] S103: Determine target position constraint information of each submodule based on the module connection relationship; the target position constraint information is used to control the module position of each submodule in a preset panel area.

[0055] Here, the relative orientation information between the sub-modules in each physical unit can be determined based on the module connection relationship, and then the position of each sub-module on the preset panel area can be estimated based on the relative orientation information, so as to determine the target position constraint information of each sub-module according to the estimated position.

[0056] The target position constraint information of each sub-module may be a position coordinate, for example, a plurality of vertex coordinates, wherein the plurality of vertex coordinates may be vertex coordinates capable of determining a position area in the preset panel area, for example, the plurality of vertex coordinates may be 4 vertex coordinates, so as to determine a regular or irregular position area through the 4 vertex coordinates, and then determine the position area as the module position of the sub-module in the preset panel area.

[0057] It should be understood that the module positions of the submodules in the preset panel area may be adjacent but not overlapped, and therefore the target position constraint information of each submodule is different.

[0058] Here, the preset panel area can be understood as a layout area that matches the physical unit in the complete layout area corresponding to the integrated circuit.

[0059] From the above description, it can be seen that in the embodiment of the present disclosure, the integrated circuit is divided into multiple physical units, and for each physical unit, a corresponding layout area is pre-divided for the physical unit in the complete layout area, and the corresponding layout area is the preset panel area in step S103.

[0060] S105: Performing logic synthesis processing on the standard library unit in each of the sub-modules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result.

[0061] In an embodiment of the present disclosure, the standard library cells in each submodule in each physical unit can be laid out based on the target position constraint information, that is, the position of the standard library cells in each submodule in the preset panel area can be determined to obtain a logic synthesis result.

[0062] In specific implementations, the target position constraint information can be used to estimate the position of each submodule within a predetermined panel area. For example, the position can be the position corresponding to the target position constraint information, along with the range within which the position can vary. Once the position is determined, logic synthesis can be performed on the standard library cells in each submodule based on the position to obtain a logic synthesis result.

[0063] Here, the target position constraint information is used to constrain the approximate layout position of each submodule and / or the standard library unit in the submodule. That is, the final layout position of each submodule and / or the standard library unit of the submodule in the preset panel area can be located within the position constrained by the target position constraint information, and can also be partially located within the position constrained by the target position constraint information. Through this setting method, the module position of each submodule and the layout position of the standard library unit in each submodule can be flexibly adjusted to achieve a better PPA indicator.

[0064] The steps described in steps S101 to S105 will be described in detail below in conjunction with specific implementations.

[0065] In an optional embodiment, if Figure 2 As shown, the above step S101 determines the module connection relationship between each sub-module in each integrated circuit, which specifically includes the following steps:

[0066] Step S1011, obtaining the RTL code file of the integrated circuit;

[0067] Step S1012 , extracting a connection file from the RTL code file, and determining the module connection relationship based on the extracted connection file, wherein the connection file includes the connection relationship between module ports of each sub-module.

[0068] In an embodiment of the present disclosure, first, an integrated circuit is divided into multiple physical blocks, and then an RTL code file for each physical block is determined, wherein the RTL code file contains the behavioral logic of the physical unit, such as the module connection relationship between each sub-module in each physical unit.

[0069] In the embodiment of the present disclosure, the RTL code file includes not only the RTL code but also a connection file; wherein the connection file includes the connection relationship between the module ports of each sub-module of the physical unit.

[0070] Based on this, a connection file can be extracted from the RTL code file, and the connection relationship in the connection file can be read, and the read connection relationship can be determined as the above module connection relationship.

[0071] Since the module connection relationship is the connection relationship between the module ports of each sub-module in the physical unit, based on this, the processing flow of data in the physical unit can be determined based on the module connection relationship, which is also the direction of data flow, and then the target position constraint information of each sub-module can be determined based on the data flow direction.

[0072] For example, the relative position information between the submodules can be determined according to the direction of the data flow. For example, the relative position information can be: submodule A is located in the right area of ​​submodule B.

[0073] In the above implementation, by analyzing the RTL code file to obtain the module connection relationship, the module connection relationship between sub-modules can be quickly and accurately obtained, thereby improving the efficiency of logic synthesis while ensuring the accuracy of the target position constraint information.

[0074] In an optional embodiment, if Figure 3 As shown, the above step S103 determines the target position constraint information of each submodule based on the module connection relationship, and specifically includes the following steps:

[0075] Step S1031, determining relative position information of each of the submodules in the preset panel area based on the module connection relationship;

[0076] Step S1032, determining a preset module area of ​​each of the submodules;

[0077] Step S1033: Determine target position constraint information of each submodule based on the relative orientation information and the preset module area.

[0078] In an embodiment of the present disclosure, a first-level sub-module can be determined in each sub-module of each physical unit; wherein, the first-level sub-module can be understood as a sub-module whose input interface is connected to the input interface of other physical units; or, the first-level sub-module is the starting processing module of data in the physical unit.

[0079] Taking the first-level submodule as the starting module, the second-level submodule connected to the output port of the first-level submodule is determined based on the module connection relationship. The third-level submodule connected to the output port of the second-level submodule is determined based on the module connection relationship. Similarly, the relative position information of each submodule in the predetermined panel area can be determined based on the hierarchical relationship between the submodules.

[0080] For example, the sub-module of the first level may be located to the left of the sub-module of the second level, and the sub-module of the second level may be located to the left of the sub-module of the third level.

[0081] Here, the preset module area of ​​each submodule can be understood as the area used by each submodule in the preset panel area, wherein the preset module area of ​​each submodule can be determined based on the standard library units included in each submodule.

[0082] In a specific implementation, the number and / or model of standard library units contained in each submodule can be determined, and then the area of ​​all standard library units contained in the submodule can be estimated based on this number and / or model. Then, the preset module area of ​​the submodule can be determined based on this area. For example, the area of ​​all standard library units can be divided by a coefficient k (for example, the value of k can be 0.6). Ultimately, the final value is determined as the preset module area of ​​the submodule on the preset panel area, as well as the area within the physical space.

[0083] In the disclosed embodiment, the area of ​​all standard library cells contained in a submodule can be estimated using an EDA tool. Alternatively, the area of ​​all standard library cells contained in a submodule can be determined by looking up a table. For example, sub-data that matches the number and / or model of standard library cells in the submodule can be found in a data table, and the area of ​​all standard library cells contained in the submodule can be determined based on the sub-data. Here, the sub-data can include a mapping relationship between the number and / or model of standard library cells and the corresponding area.

[0084] After the relative orientation information between the submodules in the corresponding physical unit and the preset module area are determined in the manner described above, the target position constraint information of each submodule in the physical unit can be determined.

[0085] During specific implementation, the target position constraint information may be determined according to the hierarchical relationship between the submodules in the physical unit and based on the relative orientation information and the preset module area.

[0086] Here, the relative orientation information of each submodule on the preset panel area may include multiple different orientation positions. For example, the submodule of the third level may be set to the left of the submodule of the second level, or to the right of the submodule of the second level. At this time, a corresponding orientation priority may be set for each orientation position, and the target position constraint information may be determined based on the orientation priority and the preset module position. The orientation priority is associated with the PPA index of the physical unit. For example, the better the PPA index of the physical unit, the higher the orientation priority of the corresponding orientation position.

[0087] In an optional embodiment, the step S1033 determines the target position constraint information of each submodule based on the relative orientation information and the preset module area, and specifically includes the following steps:

[0088] Step S11: determining a module position of each submodule in the preset panel area based on the relative orientation information and the preset module area;

[0089] Step S12: Determine the module position as target position constraint information of the corresponding submodule.

[0090] In a specific implementation, the target position constraint information of the submodule can be determined according to the module hierarchical relationship between the submodules in the physical unit, and in turn according to the relative orientation information of the submodules at the corresponding level and the preset module area. The module hierarchical relationship between the submodules is determined based on the module connection relationship between the submodules.

[0091] For example, if Figure 4 The figure shows a schematic diagram of the module connection relationship between each submodule in a physical unit. Figure 4 As can be seen from the figure, the physical unit contains 4 submodules, namely submodule0, submodule1, submodule2, and submodule3. Figure 4 As can be seen from the figure, submodule1 and submodule3 are first-level submodules. Since submodule0 is connected to submodule1 and submodule3 respectively, submodule0 is a second-level submodule. Since submodule2 is connected to submodule0, submodule1, and submodule3 respectively, submodule2 is determined to be a third-level submodule.

[0092] Based on this, we can start with the first-level sub-modules and determine the target position constraint information for the first-level sub-modules based on the preset module area of ​​the first-level sub-modules. Next, we can determine the relative orientation information between the second-level sub-modules and the first-level sub-modules, and then determine the target position constraint information for the second-level sub-modules based on this relative orientation information and the preset module area of ​​the second-level sub-modules. Similarly, we can obtain the target position constraint information for sub-modules at other levels.

[0093] Continuing with the above example, we can start with submodule 1 and submodule 3 and determine the corresponding module positions for submodule 1 and submodule 3 in the preset panel area based on the preset module area of ​​submodule 1 and the preset module area of ​​submodule 3. Then, we can determine the module position of submodule 0 based on the relative position information between submodule 0 and submodule 1 and submodule 3 and the preset module area of ​​submodule 0. For example, Figure 4 As shown, submodule 0 can be set to the left of submodule 1 and submodule 3, or to the right of submodule 1 and submodule 3. In this case, submodule 0 corresponds to multiple positions (i.e., 2). Based on this, the module position of submodule 0 can be determined according to the position priority of the position and the preset module area of ​​submodule 0.

[0094] Here, the orientation priority is associated with the PPA index of the physical unit. For example, the better the PPA index of the physical unit, the higher the orientation priority of the corresponding orientation position.

[0095] In a specific implementation, the PPA index of the physical unit can be determined when each submodule is set at each azimuth position. If the PPA index is better, it means that the azimuth position with the better PPA index has a higher azimuth priority.

[0096] Assume that the right side of submodule 1 and submodule 3 has a higher orientation priority than the left side of submodule 1 and submodule 3. That is, when submodule 0 is placed to the right of submodule 1 and submodule 3, the PPA index of the physical unit is better than the PPA index when submodule 0 is placed to the left of submodule 1 and submodule 3. In this case, the module position of submodule 0 can be determined on the right side of submodule 1 and submodule 3 according to the preset module area of ​​submodule 0.

[0097] For submodule 2, since submodule 2 is connected to submodule 0, submodule 1, and submodule 3 respectively, the relative position information of submodule 2 can be determined to be to the right of submodule 0, submodule 1, and submodule 3. At this time, the module position of submodule 2 can be determined on the right side of submodule 0, submodule 1, and submodule 3 according to the preset module area of ​​submodule 2.

[0098] In an embodiment of the present disclosure, after determining the module position of each sub-module in the preset panel area in the manner described above, relevant technical personnel can also adjust the module position of each sub-module, for example, the distance between each sub-module, or the shape of the module position of each sub-module, etc. The present disclosure does not specifically limit the specific adjustment process.

[0099] Here, the module position of each submodule in the preset panel area determined based on the relative orientation information and the preset module area can be expressed as a plurality of vertex coordinates, wherein the plurality of vertex coordinates can determine a region of regular or irregular shape.

[0100] In the above embodiment, the relative position information can be used to accurately determine the approximate position of each submodule, and the preset module area can be used to determine the occupied area of ​​the submodule within the preset panel area. By combining the preset module area and the relative position information, the target position constraint information of each submodule can be more accurately determined.

[0101] In an optional embodiment, if Figure 5 As shown, the above step S105 performs logic synthesis processing on the standard library unit in each sub-module of the integrated circuit based on the target position constraint information to obtain a logic synthesis result, which specifically includes the following steps:

[0102] Step S1051: determining the module position of each of the submodules in the preset panel area according to the target position constraint information, and laying out the standard library units in each of the submodules based on the module position to obtain a first layout result.

[0103] In specific implementation, the RTL code file of each physical unit in the integrated circuit can be obtained, and the RTL code file of the physical unit can be converted into the netlist of the physical unit, wherein the netlist of the physical unit contains the module layout information of each sub-module of the physical unit.

[0104] Afterwards, under the constraints of the target position constraint information, the first logic synthesis process can be performed on the standard library units in each sub-module of the physical unit based on the netlist, thereby obtaining a first layout result.

[0105] Here, the first layout result is used to indicate layout information of the standard library units in each sub-module in the module position indicated by the target position constraint information.

[0106] In the disclosed embodiment, when the first logical synthesis process is performed on the annotated library cells of each submodule based on the target position constraint information, a better starting point can be provided for the placement of the standard library cells. In order to enable the physical cells after synthesis to achieve better PPA indicators, the layout information of the standard library cells in each submodule in the first layout result needs to be adjusted to increase the flexibility of the layout of the standard library cells. The specific adjustment method can be described as the following steps.

[0107] Step S1052: adjusting the first layout result based on the timing constraint condition to obtain a second layout result that satisfies the timing constraint condition.

[0108] In an embodiment of the present disclosure, after performing the first logic synthesis process on the standard library units in each submodule of the physical unit according to the steps described in S1051 above, it is necessary to perform a second logic synthesis process on the standard library units in each submodule of the physical unit based on the timing constraints and the first layout result. If the synthesis result of the second logic synthesis process meets the timing constraints, it is determined that a second layout result that meets the timing constraints is obtained. If the synthesis result of the second logic synthesis process does not meet the timing constraints, it is necessary to redetermine the position constraint information of the submodule, and return to repeat steps S1051 and S1052 based on the redetermined position constraint information until a second layout result that meets the timing constraints is obtained.

[0109] Here, based on the layout information corresponding to the existing first layout result, the layout positions of at least some standard library cells can be adjusted around the layout position corresponding to the first layout result based on preset timing constraints, thereby implementing the second logic synthesis process.

[0110] During specific implementation, a timing constraint file (Synopsys design constraints, SDC) can be created, and then the timing constraint file and the first layout result can be input into the EDA tool. The EDA tool can then use the optimal timing as a target and adjust the layout positions of at least some standard library cells in the first layout result based on the timing constraints contained in the timing constraint file, thereby implementing the above-mentioned second logic synthesis processing process to obtain a second layout result that meets the timing constraints.

[0111] The standard library unit after the second logic synthesis processing does not have to be limited to the module position corresponding to the target position constraint information, that is, the standard library unit after the second logic synthesis processing can be located in an area outside the module position corresponding to the target position constraint information.

[0112] Here, the layout positions of at least part of the standard library cells in the first layout result may be adjusted based on a preset density requirement, wherein the preset density requirement is used to characterize the density of the standard library cells of each submodule in a preset panel area.

[0113] For example, as shown in Figures 6(a) and 6(b), Figure 6(a) shows a schematic diagram of the result of the first layout result, and Figure 6(b) shows a schematic diagram of the result of the second layout result. As can be seen from Figure 6(a), the position of each sub-module in the preset panel area is a relatively regular position area, and the standard library unit of each sub-module is located in the relatively regular position area. After the second logic synthesis process, the position of each sub-module in the preset panel area changes to an irregular position area, that is, after the second logic synthesis process, the layout position of the standard library unit in each sub-module has changed. And as shown in Figure 6(b), the standard library units of each sub-module are distributed in a relatively concentrated irregular position area, that is, the density of the standard library units of the sub-module meets the preset density requirement.

[0114] This processing method can prevent some standard library units of a submodule from being adjusted to a position far away from the remaining standard library units of the submodule, which is not conducive to achieving the PPA indicator.

[0115] Step S1053: Determine the second layout result as the logic synthesis result.

[0116] After performing the first and second logic synthesis processes on the standard library cells in each submodule, it is necessary to analyze whether the actual delay time between the submodules in the physical unit meets the timing constraints. If it is determined that the timing constraints are met, a second layout result that meets the timing constraints is determined, and the second layout result is determined as the logic synthesis result. If it is determined that the timing constraints are not met, the position constraint information of at least some of the submodules can be adjusted, and the standard library cells in each submodule are re-processed for logic synthesis according to S1051 and S1052 above until a second layout result that meets the timing constraints is obtained.

[0117] In an optional embodiment, the step S1052 of adjusting the first layout result based on the timing constraint to obtain a second layout result that satisfies the timing constraint specifically includes the following steps:

[0118] Step S10531: adjusting the layout positions of at least part of the standard library cells in the first layout result based on the timing constraint condition to obtain an adjustment result;

[0119] Step S10532: if it is determined based on the adjustment result that the multiple submodules do not meet the timing constraint condition, determining a submodule to be adjusted among the multiple submodules, and determining new position constraint information of the submodule to be adjusted;

[0120] Step S10533: determining a new module position of the submodule to be adjusted based on the new position constraint information, and laying out the standard library units in the submodule to be adjusted based on the new module position to obtain a new first layout result;

[0121] Step S10534: adjusting the layout positions of at least part of the standard library cells in the new first layout result based on the timing constraint conditions to obtain a new adjusted result, and if the new adjusted result satisfies the timing constraint conditions, determining the new adjusted result as the second layout result; otherwise, based on the new adjusted result, returning to the step of determining a sub-module to be adjusted from the multiple sub-modules and determining new position constraint information for the sub-module to be adjusted.

[0122] In the disclosed embodiments, the submodules to be adjusted can be understood as submodules that do not meet the timing constraints, as well as submodules associated with the submodules that do not meet the timing constraints. Here, "associated" can be understood as meaning that the actual delay time corresponding to the associated submodules is easily affected by changes in the module position of the submodule that does not meet the timing constraints. Alternatively, the submodules to be adjusted can be understood as all submodules of the physical unit.

[0123] Here, the position constraint information of the submodule to be adjusted may be updated based on other relative position information between the submodules and / or the actual delay time between the submodules, thereby obtaining new position constraint information.

[0124] For example, the position constraint information of the sub-module to be adjusted can be updated based on other relative orientation information between the sub-modules and the preset module area of ​​each sub-module, and / or the position constraint information of the sub-module to be adjusted can be updated based on the gap between the actual delay time and the timing constraint conditions between the sub-modules.

[0125] After updating the position constraint information of the submodule to be adjusted, the new module position of the submodule to be adjusted can be determined in the preset panel area according to the new position constraint information, and the standard library units in the submodule to be adjusted are laid out based on the new module position (i.e., the first logic synthesis process) to obtain a new first layout result; thereafter, the layout position of at least part of the standard library units in the new first layout result is adjusted based on the timing constraint conditions (i.e., the second logic synthesis process) to obtain a new adjustment result. If the new adjustment result meets the timing constraint conditions, it is determined that the second layout result is obtained. If the new adjustment result does not meet the timing constraint conditions, then return to the above-mentioned step S10532, and execute steps S10532 to S10534 again until an adjustment result that meets the timing constraint conditions is obtained. The execution process will not be described in detail here.

[0126] The process of determining the new position constraint information of the submodule to be adjusted will be described below in different situations.

[0127] Method 1:

[0128] In this first approach, the above steps update the position constraint information of the submodule to be adjusted, specifically including the following steps:

[0129] (1) determining multiple candidate module positions of the submodule to be adjusted in the preset panel area based on the module connection relationship;

[0130] (2) Determine a target candidate module position among the multiple candidate module positions, and determine the target candidate module position as new position constraint information of the submodule to be adjusted.

[0131] If the relative orientation information between the submodules to be adjusted includes multiple orientation positions, it can be determined that the submodules to be adjusted include multiple candidate module positions. Each candidate module position corresponds to an orientation position. Based on this, multiple orientation positions of the submodules to be adjusted can be determined in the preset panel area based on the module connection relationship, and then multiple candidate module positions can be determined based on the multiple orientation positions.

[0132] Next, the target candidate module position can be determined from the multiple candidate module positions according to the position priority of each position. For example, the candidate module position with the highest position priority among the multiple candidate module positions can be determined as the target candidate module position.

[0133] It should be understood that the target candidate module position is not the module position corresponding to the sub-module to be adjusted in the second layout result.

[0134] After the target candidate module position is determined, the target candidate module position can be determined as the updated position constraint information of the sub-module to be adjusted to obtain new position constraint information.

[0135] In the above embodiment, when the sub-module to be adjusted contains multiple alternative module positions, by updating the position constraint information of the adjustment sub-module based on the multiple alternative module positions, multiple layout methods can be provided for the physical unit, thereby maximizing the layout effect of the standard library unit.

[0136] Method 2:

[0137] In the second approach, the above steps of determining the new position constraint information of the submodule to be adjusted include:

[0138] (1) determining the actual delay time between the sub-modules to be adjusted based on the adjustment result;

[0139] (2) When it is determined based on the actual delay time that the sub-module to be adjusted meets the adjustment requirements, the distance between the sub-modules to be adjusted is shortened, and new position constraint information of the sub-module to be adjusted is determined based on the module position of the sub-module to be adjusted after the distance is shortened.

[0140] In the disclosed embodiment, as shown in Figure 7(a), two registers are connected via combinational logic. As shown in Figure 7(b), the distance between the two registers increases, which degrades the timing between them. This increase in distance requires additional buffering and longer traces, increasing the area and power consumption of the integrated circuit.

[0141] Based on this, the actual delay time between the submodules to be adjusted can be determined based on the adjustment results, and the difference between the actual delay time and the preset clock period can be analyzed. If it is determined that the difference is less than the preset difference, it is determined that the submodules to be adjusted meet the adjustment requirements. At this time, the distance between the submodules to be adjusted can be shortened, and the position constraint information of the submodules to be adjusted can be updated based on the module position of the submodules to be adjusted after the distance is shortened to obtain new position constraint information.

[0142] Here, a target mapping table may be obtained, wherein the target mapping table is used to map the correspondence between distances and gaps. For example, the target mapping table may include multiple mapping relationships, each of which may include a gap interval and a distance interval. The mapping relationship is used to indicate that when the gap is within the gap interval, the distance between the sub-modules to be adjusted can be adjusted within the distance interval.

[0143] After obtaining the target mapping table, a target mapping relationship matching the gap may be determined from multiple mapping relationships included in the target mapping table, thereby shortening the distance between the submodules to be adjusted based on the distance interval included in the target mapping relationship.

[0144] In the above embodiment, by adjusting the distance between the sub-modules to be adjusted by the actual delay time, the module position of each sub-module in the second layout result can be finely adjusted, thereby improving the flexibility of adjusting the module position of the sub-module and achieving a better PPA indicator.

[0145] In an optional embodiment, the step of determining the submodule to be adjusted from the multiple submodules in step S10531 further includes the following steps:

[0146] (1) Determine a first-category submodule that does not satisfy the timing constraint condition among the multiple submodules, and determine a second-category submodule associated with the first-category submodule among the remaining submodules of the multiple submodules; wherein the module position of the second-category submodule changes as the module position of the first-category submodule changes.

[0147] For example, if Figure 4 As shown in the figure, if the timing constraints between submodule 1 and submodule 0 are not met, submodule 1 and submodule 0 are determined to be first-class submodules. In this case, the module positions of submodule 1 and submodule 0 need to be adjusted. If the module position of submodule 2 changes as the module position of submodule 0 changes, submodule 2 is determined to be second-class submodule.

[0148] For example, submodule 0 needs to be adjusted to the left of submodule 1. At this time, the distance between submodule 0 and submodule 2 becomes farther. From the contents described in Figure 7(a) and Figure 7(b) above, it can be seen that in order to meet the requirements of the area, power consumption and timing of the integrated circuit, the distance between submodule 0 and submodule 2 needs to be adjusted, and the module position of submodule 2 must be adjusted. In this case, submodule 2 is a second-type submodule.

[0149] (2) Determine the submodule to be adjusted based on the first type of submodule and the second type of submodule.

[0150] In the embodiment of the present disclosure, the first type of submodule and the second type of submodule can be determined as the submodule to be adjusted. By this processing method, the workload in the logic synthesis process can be reduced, thereby improving the efficiency of logic synthesis.

[0151] The following will Figure 8 An overall introduction to the logic synthesis method of the integrated circuit described above is given. Figure 8 As shown, the logic synthesis method of the integrated circuit includes the following steps:

[0152] S801: Obtain the RTL code file of the integrated circuit;

[0153] S802: Determine module connection relationships between sub-modules in physical units in the integrated circuit based on the RTL code file.

[0154] In a specific implementation, a connection file can be extracted from the RTL code file, and the module connection relationship can be determined based on the extracted connection file, wherein the connection file contains the connection relationship between the module ports of each sub-module. The specific determination process is as described above in steps S1011 and S1012 and will not be described in detail here.

[0155] S803: Determine target position constraint information of each submodule based on the module connection relationship; wherein the target position constraint information is used to control the module position of each submodule in a preset panel area.

[0156] In a specific implementation, the relative orientation information of each submodule within the predetermined panel area can be determined based on the module connection relationship, and the predetermined module area of ​​each submodule can be determined. Furthermore, based on the relative orientation information and the predetermined module area, the module position of each submodule within the predetermined panel area can be determined. The module position is determined as the target position constraint information for the corresponding submodule. The specific determination process is as described above in steps S1031 to S1033 and will not be described in detail here.

[0157] S804: Performing a first logic synthesis process on the standard library cells in each sub-module based on the target position constraint information to obtain a first layout result.

[0158] In a specific implementation, the module position of each submodule can be determined in the preset panel area according to the target position constraint information, and the standard library units in each submodule are laid out based on the module position to obtain a first layout result. The specific determination process is as described in step S1051 above and will not be described in detail here.

[0159] S805: Perform a second logic synthesis process on the standard library cells in each sub-module based on the timing constraint conditions and the first layout result to obtain an adjustment result.

[0160] In specific implementation, the layout positions of at least some standard library cells in the first layout result can be adjusted based on the timing constraints to obtain the second layout result. The specific determination process is as described in step S1052 above and will not be described in detail here.

[0161] S806: When the adjustment result satisfies the timing constraint, determine a second layout result that satisfies the timing constraint, and determine the second layout result as a logic synthesis result.

[0162] S807: When the adjustment result does not satisfy the timing constraint condition, a submodule to be adjusted is determined from the multiple submodules, and position constraint information of the submodule to be adjusted is updated to obtain new position constraint information.

[0163] In specific implementation, a first type of sub-module that does not meet the timing constraint conditions can be determined among the multiple sub-modules, and a second type of sub-module associated with the first type of sub-module can be determined among the remaining sub-modules of the multiple sub-modules; wherein the module position of the second type of sub-module changes with the change of the module position of the first type of sub-module; and the sub-module to be adjusted is determined based on the first type of sub-module and the second type of sub-module.

[0164] In the embodiment of the present disclosure, the position constraint information of the submodule to be adjusted may be updated by the methods described in the above-mentioned method 1 and method 2, which will not be described in detail here.

[0165] S808: Determine the new position constraint information as the target position constraint information of the submodule to be adjusted, and return to step S804 until a second layout result that meets the timing constraint condition is obtained, and determine the second layout result that meets the timing constraint condition as the logic synthesis result.

[0166] As can be seen from the above description, by determining positional constraints based on the module connection relationships between submodules, it is possible to control the module positions within the preset panel area, thereby improving the rationality of the submodule layout. When performing logic synthesis on the annotated library cells of each submodule based on this positional constraint information, it provides a better starting point for the placement of standard library cells, thereby obtaining a more comprehensive logic synthesis result and achieving a better PPA indicator.

[0167] Those skilled in the art will understand that in the above method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0168] Based on the same inventive concept, the embodiments of the present disclosure also provide a logic synthesis device for an integrated circuit corresponding to the logic synthesis method for an integrated circuit. Since the principle of solving the problem by the device in the embodiments of the present disclosure is similar to the logic synthesis method for the integrated circuit in the embodiments of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0169] Reference Figure 9 FIG. 1 is a schematic diagram of a logic synthesis device for an integrated circuit provided by an embodiment of the present disclosure, wherein the device includes: a first determination unit 10, a second determination unit 20, and a logic synthesis unit 30; wherein,

[0170] A first determining unit 10 is configured to determine a module connection relationship between submodules in the integrated circuit;

[0171] A second determining unit 20 is configured to determine target position constraint information of each submodule based on the module connection relationship; the target position constraint information is used to indicate the module position of each submodule in a preset panel area;

[0172] The logic synthesis unit 30 is configured to perform logic synthesis processing on the standard library cells in each of the sub-modules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result.

[0173] As can be seen from the above description, by determining positional constraints based on the module connection relationships between submodules, it is possible to control the module positions within the preset panel area, thereby improving the rationality of the submodule layout. When performing logic synthesis on the annotated library cells of each submodule based on this positional constraint information, it provides a better starting point for the placement of standard library cells, thereby obtaining a more comprehensive logic synthesis result and achieving a better PPA indicator.

[0174] In one possible implementation, the second determination unit is further used to: determine the relative orientation information of each of the sub-modules in the preset panel area based on the module connection relationship; determine the preset module area of ​​each of the sub-modules; and determine the target position constraint information of each of the sub-modules based on the relative orientation information and the preset module area.

[0175] In one possible implementation, the second determination unit is further used to: determine the module position of each of the submodules in the preset panel area based on the relative orientation information and the preset module area; and determine the module position as the target position constraint information of the corresponding submodule.

[0176] In one possible implementation, the logic synthesis unit is further used to: determine the module position of each of the sub-modules in the preset panel area according to the target position constraint information, and layout the standard library units in each of the sub-modules based on the module position to obtain a first layout result; adjust the first layout result based on the timing constraint condition to obtain a second layout result that satisfies the timing constraint condition; and determine the second layout result as the logic synthesis result.

[0177] In one possible implementation, the logic synthesis unit is further configured to: adjust the layout positions of at least some standard library cells in the first layout result based on the timing constraints to obtain an adjusted result; if it is determined based on the adjustment result that the multiple sub-modules do not satisfy the timing constraints, determine a sub-module to be adjusted among the multiple sub-modules and determine new position constraint information for the sub-module to be adjusted; determine a new module position for the sub-module to be adjusted based on the new position constraint information, and layout the standard library cells in the sub-module to be adjusted based on the new module position to obtain a new first layout result; adjust the layout positions of at least some standard library cells in the new first layout result based on the timing constraints to obtain a new adjusted result, and if the new adjusted result satisfies the timing constraints, determine the new adjusted result as the second layout result; otherwise, based on the new adjustment result, return to the step of determining a sub-module to be adjusted among the multiple sub-modules and determining new position constraint information for the sub-module to be adjusted.

[0178] In one possible implementation, the logic synthesis unit is further used to: determine a first type of sub-module that does not meet the timing constraint conditions among the multiple sub-modules, and determine a second type of sub-module associated with the first type of sub-module among the remaining sub-modules of the multiple sub-modules; wherein the module position of the second type of sub-module changes with the change of the module position of the first type of sub-module; and determine the sub-module to be adjusted based on the first type of sub-module and the second type of sub-module.

[0179] In one possible implementation, the logic synthesis unit is further used to: determine multiple alternative module positions of the sub-module to be adjusted in the preset panel area based on the module connection relationship; determine a target alternative module position among the multiple alternative module positions, and determine the target alternative module position as the new position constraint information of the sub-module to be adjusted.

[0180] In one possible implementation, the logic synthesis unit is further used to: determine the actual delay time between the sub-modules to be adjusted based on the adjustment result; when it is determined based on the actual delay time that the sub-modules to be adjusted meet the adjustment requirements, shorten the distance between the sub-modules to be adjusted, and determine the new position constraint information of the sub-modules to be adjusted based on the module position of the sub-modules to be adjusted after the distance is shortened.

[0181] In one possible implementation, the first determination unit is further used to: obtain the RTL code file of the integrated circuit; extract the connection file in the RTL code file, and determine the module connection relationship based on the extracted connection file, wherein the connection file contains the connection relationship between the module ports of each sub-module.

[0182] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference can be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0183] Corresponding to Figure 1 The embodiment of the present disclosure further provides an electronic device 1000, such as Figure 10 FIG. 1 is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of the present disclosure, including:

[0184] Processor 101, memory 102, and bus 103; memory 102 is used to store execution instructions, including internal memory 1021 and external memory 1022; the internal memory 1021 is also called internal memory, which is used to temporarily store operation data in the processor 101 and data exchanged with external memory 1022 such as a hard disk. The processor 101 exchanges data with the external memory 1022 through the internal memory 1021. When the electronic device 1000 is running, the processor 101 and the memory 102 communicate through the bus 103, so that the processor 101 executes the following instructions:

[0185] Determining a module connection relationship between submodules in the integrated circuit;

[0186] Determine target position constraint information of each submodule based on the module connection relationship; the target position constraint information is used to control the module position of each submodule in a preset panel area;

[0187] Based on the target position constraint information, logic synthesis processing is performed on the standard library unit in each sub-module of the integrated circuit to obtain a logic synthesis result.

[0188] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program executes the steps of the integrated circuit logic synthesis method described in the above method embodiment. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0189] An embodiment of the present disclosure also provides a computer program product, which carries program code. The instructions included in the program code can be used to execute the steps of the logic synthesis method of the integrated circuit described in the above method embodiment. For details, please refer to the above method embodiment and will not be repeated here.

[0190] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0191] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0192] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be integrated circuits, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0193] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0194] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0195] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The scope of protection of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present disclosure, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope of protection of the claims.

Claims

1. A logic synthesis method for an integrated circuit, characterized in that: The integrated circuit includes multiple sub-modules, including: Determining a module connection relationship between submodules in the integrated circuit; Determine target position constraint information of each submodule based on the module connection relationship; the target position constraint information is used to control the module position of each submodule in a preset panel area; Performing logic synthesis processing on the standard library unit in each submodule of the integrated circuit based on the target position constraint information to obtain a logic synthesis result; The performing logic synthesis processing on the standard library unit in each submodule of the integrated circuit based on the target position constraint information to obtain a logic synthesis result includes: determining a module position of each of the submodules in the preset panel area according to the target position constraint information, and laying out the standard library units in each of the submodules based on the module position to obtain a first layout result; Adjusting the first layout result based on a timing constraint condition to obtain a second layout result that satisfies the timing constraint condition, and determining the second layout result as the logic synthesis result; The adjusting the first layout result based on the timing constraint condition to obtain a second layout result that satisfies the timing constraint condition includes: Adjusting the layout positions of at least part of the standard library cells in the first layout result based on the timing constraint condition to obtain an adjustment result; In a case where it is determined based on the adjustment result that the multiple submodules do not meet the timing constraint condition, determining a submodule to be adjusted among the multiple submodules, and determining new position constraint information of the submodule to be adjusted; Determining a new module position of the submodule to be adjusted based on the new position constraint information, and laying out the standard library units in the submodule to be adjusted based on the new module position to obtain a new first layout result; Adjusting the layout positions of at least some standard library cells in the new first layout result based on the timing constraint to obtain a new adjusted result, and determining the new adjusted result as the second layout result if the new adjusted result satisfies the timing constraint; Otherwise, based on the new adjustment result, return to the step of determining a submodule to be adjusted among the multiple submodules, and determining new position constraint information of the submodule to be adjusted.

2. The method according to claim 1, characterized in that The determining of target position constraint information of each submodule based on the module connection relationship includes: Determining relative position information of each of the submodules in the preset panel area based on the module connection relationship; Determining a preset module area of ​​each of the submodules; Based on the relative orientation information and the preset module area, target position constraint information of each submodule is determined.

3. The method according to claim 2, characterized in that The determining of target position constraint information of each submodule based on the relative orientation information and the preset module area includes: Determining a module position of each of the submodules in the preset panel area based on the relative orientation information and the preset module area; The module position is determined as target position constraint information of the corresponding submodule.

4. The method according to claim 1, wherein The determining of a submodule to be adjusted from among the multiple submodules includes: Determining a first type of submodule that does not satisfy the timing constraint condition from among the multiple submodules, and determining a second type of submodule associated with the first type of submodule from among the remaining submodules of the multiple submodules; wherein a module position of the second type of submodule changes as the module position of the first type of submodule changes; The submodule to be adjusted is determined based on the first-category submodule and the second-category submodule.

5. The method according to claim 3 or 4, characterized in that The determining of the new position constraint information of the submodule to be adjusted includes: Determining multiple candidate module positions of the submodule to be adjusted in the preset panel area based on the module connection relationship; A target candidate module position is determined among the multiple candidate module positions, and the target candidate module position is determined as new position constraint information of the submodule to be adjusted.

6. The method according to any one of claims 1 to 4, characterized in that The determining of the new position constraint information of the submodule to be adjusted includes: Determine the actual delay time between the submodules to be adjusted based on the adjustment result; When it is determined based on the actual delay time that the submodules to be adjusted meet the adjustment requirements, the distance between the submodules to be adjusted is shortened, and new position constraint information of the submodules to be adjusted is determined based on the module positions of the submodules to be adjusted after the distance is shortened.

7. The method according to any one of claims 1 to 4, characterized in that Determining the module connection relationship between the sub-modules in each of the integrated circuits includes: Obtaining an RTL code file of the integrated circuit; A connection file is extracted from the RTL code file, and the module connection relationship is determined based on the extracted connection file, wherein the connection file includes the connection relationship between the module ports of each sub-module.

8. A logic synthesis device for an integrated circuit, characterized in that: The integrated circuit includes multiple sub-modules, including: a first determining unit, configured to determine a module connection relationship between sub-modules in the integrated circuit; A second determining unit is configured to determine target position constraint information of each submodule based on the module connection relationship; the target position constraint information is used to indicate a module position of each submodule in a preset panel area; a logic synthesis unit, configured to perform logic synthesis processing on the standard library unit in each of the submodules of the integrated circuit based on the target position constraint information to obtain a logic synthesis result; The logic synthesis unit is further configured to: determine a module position of each of the submodules in the preset panel area according to the target position constraint information, and layout the standard library cells in each of the submodules based on the module position to obtain a first layout result; adjust the first layout result based on a timing constraint condition to obtain a second layout result that satisfies the timing constraint condition; and determine the second layout result as the logic synthesis result; The logic synthesis unit is further specifically configured to: adjust the layout positions of at least some of the standard library cells in the first layout result based on the timing constraints to obtain an adjusted result; if it is determined based on the adjustment result that the multiple sub-modules do not satisfy the timing constraints, determine a sub-module to be adjusted among the multiple sub-modules, and determine new position constraint information for the sub-module to be adjusted; determine a new module position of the sub-module to be adjusted based on the new position constraint information, and layout the standard library cells in the sub-module to be adjusted based on the new module position to obtain a new first layout result; adjust the layout positions of at least some of the standard library cells in the new first layout result based on the timing constraints to obtain a new adjusted result, and if the new adjusted result satisfies the timing constraints, determine the new adjusted result as the second layout result; otherwise, based on the new adjustment result, return to the step of determining the sub-module to be adjusted among the multiple sub-modules and determining the new position constraint information for the sub-module to be adjusted.

9. An electronic device, characterized in that: include: A processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the logic synthesis method of the integrated circuit as described in any one of claims 1 to 7 are performed.

10. A chip, characterized in that: The chip is subjected to logic synthesis using the integrated circuit logic synthesis method according to any one of claims 1 to 7, and layout and routing are performed on each sub-module of the integrated circuit based on the logic synthesis result.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the logic synthesis method for an integrated circuit as claimed in any one of claims 1 to 7 are executed.

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