A pin state control method and system of a chip, a chip, and a host computer

Abstract

The embodiment of the application discloses a pin state control method and system of a chip, a chip and an upper computer, relates to the technical field of chips, and can effectively improve the design efficiency and integration of the chip. The method comprises the following steps: generating an enable control signal of an input-output control component corresponding to a target pin of the chip based on preset values moved into a boundary scan unit corresponding to the target pin through a JTAG interface; and controlling the input-output control component to be in an input enable state or an output enable state according to the enable control signal, so that, in the input enable state, a pin signal flows into the chip through the target pin, or in the output enable state, a pin signal flows out of the chip through the target pin. The application is suitable for being applied to the chip.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, system, chip, and host computer for controlling the pin states of a chip. Background Technology

[0002] As chip complexity continues to increase, especially for very large-scale chips (VLSI), numerous functional modules are integrated within the chip. The same pin is often reused by different modules, and a pin may be in either an input-enabled or output-enabled state within each module. To effectively control the switching between these states, complex control circuitry is often required within the chip. For chip testing, complex test control circuitry is also needed to control the pins to either output or input-enabled states as needed during performance verification tests of various functional modules. Of course, many other scenarios require controlling the chip's pin states using complex internal control circuitry. While these control circuits can control pin states, the complex control logic not only reduces chip design efficiency but also occupies a significant area within the chip, decreasing its integration density. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method, system, chip, host computer, and control system for controlling the pin state of a chip, which can effectively improve chip design efficiency and integration.

[0004] In a first aspect, embodiments of the present invention provide a pin state control method for a chip, the method comprising:

[0005] Based on the preset value shifted into the boundary scan unit corresponding to the target pin of the chip via the JTAG interface, an enable control signal for the input / output control unit corresponding to the target pin is generated.

[0006] The input / output control component is controlled to be in an input-enabled state or an output-enabled state according to the enable control signal, so that in the input-enabled state, the pin signal flows into the chip through the target pin, or in the output-enabled state, the pin signal flows out of the chip through the target pin.

[0007] Optionally, the chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain, and at least one end of the boundary scan chain communicates with the outside world through a JTAG interface;

[0008] The generation of the enable control signal for the input / output control unit corresponding to the target pin, based on the preset value shifted in via the JTAG interface in the boundary scan unit corresponding to the target pin of the chip, includes:

[0009] Based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, an enable control signal for the input / output control unit corresponding to the target pin is generated. Based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface, a redundant signal is generated.

[0010] Optionally, the step of generating an enable control signal for an input / output control unit corresponding to the target pin based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, and generating a redundant signal based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface, includes:

[0011] Driven by the first type of signal output by the Test Access Port Controller (TAPC), the preset value and the arbitrary value are shifted into the first boundary scan unit and the second boundary scan unit corresponding to the target pin via the JTAG interface;

[0012] Driven by the second type of signal output by the Test Access Port Controller (TAPC), the preset value and the arbitrary value are output from the first boundary scan unit and the second boundary scan unit corresponding to the target pin to their respective parallel output ports to generate the enable control signal and the redundant signal of the input / output control component.

[0013] Optionally, after controlling the input / output control unit to be in an input-enabled state or an output-enabled state according to the enable control signal, the method further includes:

[0014] The test signal sent by the test device is received through the target pin which is in the input enabled state;

[0015] The test signal is processed, and the processed signal is output from the target pin that is in the output enable state.

[0016] Secondly, embodiments of the present invention also provide another method for controlling the pin states of a chip, the method comprising:

[0017] Generate preset values ​​based on the expected input / output states of the target pins of the chip;

[0018] The preset value is moved into the boundary scan unit corresponding to the target pin through the JTAG interface, so as to control the target pin to be in the input enabled state or the output enabled state through the boundary scan unit.

[0019] Optionally, the chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain;

[0020] The step of generating preset values ​​based on the expected input / output states of the target pins of the chip includes:

[0021] Based on the structure of the boundary scan chain, the positions of the first boundary scan units corresponding to each target pin, the positions of the second boundary scan units corresponding to each target pin, and the positions of the first and second boundary scan units corresponding to each non-target pin are determined.

[0022] The preset value is configured at the position of each first boundary scan unit corresponding to each target pin, and an arbitrary value is configured at the position of each second boundary scan unit corresponding to each target pin. An arbitrary value is configured at the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin. The preset value and the arbitrary value are arranged in the order of the positions of each boundary scan unit in the boundary scan chain to form a value string.

[0023] The step of shifting the preset value into the boundary scan unit corresponding to the target pin via the JTAG interface includes:

[0024] The numerical string is moved into the corresponding boundary scan units in the boundary scan chain via the JTAG interface.

[0025] Optionally, before generating the preset value based on the expected input / output state of the target pin of the chip, the method further includes:

[0026] Obtain the target pin in the chip that corresponds to a specific test item.

[0027] Optionally, after shifting the preset value into the boundary scan unit corresponding to the target pin via the JTAG interface, so as to control the target pin to be in an input enabled state or an output enabled state through the boundary scan unit, the method further includes: sending a command to the test device to execute the specific test item, and receiving the corresponding test results.

[0028] Optionally, sending the command to the testing device to execute the specific test item and receiving the corresponding test results includes:

[0029] Send a command to the testing device to execute the specific test item, so as to control the testing device to input the test signal of the specific test item to the target pin that is in the input enable state;

[0030] The test device is controlled to acquire the test output signal from the target pin that is in the output enable state;

[0031] Receive the test output signal and generate test results based on the test output signal.

[0032] Thirdly, embodiments of the present invention provide a chip, the chip comprising:

[0033] A boundary scan unit is used to generate an enable control signal for the input / output control component of the target pin based on a preset value shifted in via the JTAG interface; wherein the target pin corresponds to the boundary scan unit.

[0034] An input / output control unit is connected at one end to the boundary scanning unit and at the other end to the target pin. It is used to control the target pin to be in an input enabled state or an output enabled state according to the enable control signal generated by the boundary scanning unit.

[0035] The target pin is connected to the input / output control unit and is used to input a pin signal into the chip in the input enable state, or to output a pin signal from the chip in the output enable state.

[0036] Optionally, the chip has at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain, and at least one end of the boundary scan chain communicates with the outside world through a JTAG interface; the first boundary scan unit is connected to the corresponding input / output control unit through its own parallel output port;

[0037] The first boundary scan unit corresponding to the target pin is used to generate an enable control signal for the input / output control unit corresponding to the target pin based on the preset value shifted in via the JTAG interface.

[0038] The second boundary scan unit corresponding to the target pin is used to generate a redundant signal based on any value shifted in via the JTAG interface.

[0039] Optionally, the first boundary scan unit and the second boundary scan unit corresponding to the target pin are specifically used to: receive the value and the arbitrary value shifted in via the JTAG interface in response to the first type of signal output by the Test Access Port Controller (TAPC); and output the preset value and the arbitrary value to their respective parallel output ports in response to the second type of signal output by the Test Access Port Controller (TAPC), so as to generate the enable control signal and the redundant signal of the input / output control component.

[0040] Optionally, the chip further includes: functional logic components;

[0041] The input / output control unit is also used to receive test signals sent by the test device through the target pin in the input enabled state;

[0042] The functional logic component is used to process the test signal;

[0043] The input / output control unit is also used to output the signal processed by the functional logic unit from the target pin that is in the output enable state.

[0044] Fourthly, embodiments of the present invention provide a host computer, the host computer comprising:

[0045] The generation unit is used to generate preset values ​​based on the expected input / output states of the target pins of the chip.

[0046] The shift unit is used to shift the preset value into the boundary scan unit corresponding to the target pin through the JTAG interface, so as to control the target pin to be in the input enabled state or the output enabled state through the boundary scan unit.

[0047] Optionally, the chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain;

[0048] The generation unit is specifically used for:

[0049] Based on the structure of the boundary scan chain, the positions of the first boundary scan units corresponding to each target pin, the positions of the second boundary scan units corresponding to each target pin, and the positions of the first and second boundary scan units corresponding to each non-target pin are determined.

[0050] The preset value is configured at the position of each first boundary scan unit corresponding to each target pin, and an arbitrary value is configured at the position of each second boundary scan unit corresponding to each target pin. An arbitrary value is configured at the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin. The preset value and the arbitrary value are arranged in the order of the positions of each boundary scan unit in the boundary scan chain to form a value string.

[0051] The shifting unit is specifically used for:

[0052] The numerical string is moved into the corresponding boundary scan units in the boundary scan chain via the JTAG interface.

[0053] Optionally, the host computer further includes: an acquisition unit, used to acquire the target pin in the chip corresponding to a specific test item before generating a preset value based on the expected input / output state of the target pin in the chip.

[0054] Optionally, the host computer further includes:

[0055] The sending and receiving unit is used to send commands to the testing device to execute the specific test item and to receive the corresponding test results.

[0056] Optionally, the transmitting and receiving unit is specifically used for:

[0057] Send a command to the testing device to execute the specific test item, so as to control the testing device to input the test signal of the specific test item to the target pin that is in the input enable state;

[0058] The test device is controlled to acquire the test output signal from the target pin that is in the output enable state;

[0059] The test output signal is received, and a test result is generated based on the test output signal.

[0060] Fifthly, embodiments of the present invention provide a pin state control system for a chip, the system including any of the aforementioned chips and any of the aforementioned host computers, wherein the host computer configures the enable state of a target pin of the chip.

[0061] The pin state control method, system, chip, and host computer provided in the embodiments of the present invention can generate an enable control signal for an input / output control component corresponding to a target pin based on a preset value shifted into the boundary scan unit corresponding to the target pin via the JTAG interface. The enable control signal controls the input / output control component to be in an input-enabled state or an output-enabled state, so that in the input-enabled state, the pin signal flows into the chip through the target pin, or in the output-enabled state, the pin signal flows out of the chip through the target pin. In this way, the existing JTAG interface and boundary scan unit in the chip can be used to configure preset values ​​as corresponding control parameters for the target pin, and the target pin can be controlled to be in an input-enabled state or an output-enabled state through these control parameters, without the need to design complex test control circuits in the chip to control the input / output state of the target pin, effectively improving chip design efficiency and integration. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 A flowchart of a chip pin state control method provided for an embodiment of the present invention;

[0064] Figure 2 A schematic diagram illustrating an application scenario of the chip pin state control method provided in an embodiment of the present invention;

[0065] Figure 3 A schematic diagram of the structure of a boundary scanning unit provided for an embodiment of the present invention;

[0066] Figure 4 Another flowchart of a chip pin state control method provided for an embodiment of the present invention;

[0067] Figure 5 A schematic diagram of a chip structure provided for an embodiment of the present invention;

[0068] Figure 6 This is a schematic diagram of a host computer provided for an embodiment of the present invention. Detailed Implementation

[0069] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0070] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0071] To more clearly explain the principles of the embodiments of the present invention, the relevant background knowledge involved in the embodiments of the present invention will first be introduced.

[0072] A chip is a miniature structure that uses a specific process to fabricate one or more small pieces of semiconductor wafer or dielectric substrate together with interconnected wiring for a circuit. These components, such as transistors, resistors, capacitors, and inductors, are then packaged in a housing to form a miniature structure with the required circuit function.

[0073] Boundary scan technology is a test architecture design method applied to digital integrated circuit devices. The term "boundary" refers to the test circuit being positioned around the functional logic circuitry of the integrated circuit device, near the boundaries of the device's input and output pins. The term "scan" refers to the fact that the test circuit connecting the device's input and output pins is actually a serial shift register called a boundary scan cell (BSC). Various codes consisting of "1"s and "0"s can be input into the boundary scan chain of BSC cells to perform a "scanning" test on the circuit, and the output result is used to determine its correctness.

[0074] JTAG (Joint Test Action Group) is an international standard testing protocol primarily used for internal chip testing. Its basic principle is to define a TAP (Test Access Port) within the chip, and then use dedicated JTAG testing tools to test internal nodes. The standard JTAG interface uses a four-wire configuration: TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data In), and TDO (Test Data Out), representing mode selection, clock, data input, and data output, respectively. The IEEE 1149.1 standard was initially proposed by the JTAG organization and was ultimately approved and standardized by the IEEE; therefore, the IEEE 1149.1 standard is commonly referred to as the JTAG debugging standard.

[0075] The TCK signal provides an independent, fundamental clock signal for the TAP's operation; all TAP operations are driven by this clock signal. The TMS signal controls the transitions of the TAP state machine, allowing the TAP to switch between different states. TDI is the data input interface; all data to be input to a specific BSC is serially input bit by bit through the TDI interface (driven by TCK). TDO is the data output interface; all data to be output from a specific BSC is serially output bit by bit through the TDO interface (driven by TCK). Additionally, there is an optional port TRST (Test Reset), which is the test system reset signal, used for forced reset.

[0076] The general process for accessing the data register (DR) through the TAP interface is as follows: 1. Select a data register to be accessed through the instruction register; 2. Connect the selected data register between TDI and TDO; 3. Driven by TCK, input the required data into the selected data register through TDI; at the same time, read the data in the selected data register through TDO.

[0077] In a first aspect, embodiments of the present invention provide a pin state control method for a chip, which can effectively improve chip design efficiency and integration.

[0078] like Figure 1 As shown, the pin state control method of the chip may include:

[0079] S11, Based on the preset value shifted into the boundary scan unit corresponding to the target pin of the chip via the JTAG interface, an enable control signal for the input / output control unit corresponding to the target pin is generated.

[0080] The pins of a chip refer to the connections that lead out from the internal circuitry of the chip to the external circuitry. All the pins together constitute the interface of the chip. Figure 2 In this context, PADs are silicon chip pins, packaged inside the chip. Each pin of the chip is connected to a corresponding PAD via a wire, for example, in... Figure 2 In the diagram, PAD1 is connected to pin 1, PAD2 is connected to pin 2, and PADn is connected to pin n.

[0081] Each chip typically has multiple pins. The target pin is the pin where the user needs to control the input / output status. Each target pin is internally connected to one or more BSCs, depending on the specific hardware design. For example... Figure 2As shown, the input / output control unit is a controlled input / output control unit that is electrically connected to the corresponding target pin. Under the control signal generated by the corresponding BSC, the input / output control unit can be in an input enabled state or an output enabled state, thereby facilitating the target pin to input or output signals through the input / output control unit.

[0082] In this step, the TDI in the JTAG interface can be used to send a message to the BSC corresponding to the target pin (e.g., ...). Figure 2 A preset value is shifted into the boundary scan unit (as shown in the example). This preset value can be a single bit of binary data, such as 0 or 1. Based on the preset value, an enable control signal for the input / output control unit corresponding to the target pin can be generated. For example, if the target pin is pin 1, a low-level PAD1_oe (PAD1 output enable) signal can be generated when the preset value is 0, and a high-level PAD1_oe signal can be generated when the preset value is 1. Similarly, the target pin can also be other pins, and the corresponding enable control signals for the input / output control units can be generated in the same way as in the example above.

[0083] S12, according to the enable control signal, control the input / output control component to be in an input enable state or an output enable state, so that in the input enable state, the pin signal flows into the chip through the target pin, or in the output enable state, the pin signal flows out of the chip through the target pin.

[0084] In this step, such as Figure 2 As shown, the PAD1_oe signal is connected to the input / output control unit corresponding to pin 1, which can be composed of a tri-state output gate and a tri-state input gate. If the target pin is pin 1, the enable state of the tri-state output gate can be controlled using the PAD1_oe signal generated in step S11. Specifically, when PAD1_oe is a low-level output enable control signal, the tri-state output gate can achieve normal logic state output (logic 0, logic 1), that is, it is in the output enable state. When PAD1_oe is a high-level non-output enable control signal, the output of the tri-state output gate is in a high-impedance state, that is, it is equivalent to being disconnected from the connected circuit, and cannot output a valid level signal, and is in the non-output enable state, that is, the input enable state.

[0085] It should be noted that whether the signal output from PAD1_oe is active high or active low depends on the hardware design of the tri-state output gate. By modifying the hardware structure of the tri-state output gate, it is possible to make the high level output from PAD1_oe a valid signal and the low level output from PAD1_oe an invalid signal. This implementation method is similar to... Figure 2The hardware design shown does not differ substantially in principle and is also within the protection scope of this invention.

[0086] The chip pin state control method provided by the embodiments of the present invention can generate an enable control signal for an input / output control component corresponding to a target pin based on a preset value shifted into the boundary scan unit via the JTAG interface in the boundary scan unit corresponding to the target pin of the chip. The input / output control component is controlled to be in an input enabled state or an output enabled state according to the enable control signal, so that in the input enabled state, the pin signal flows into the chip through the target pin, or in the output enabled state, the pin signal flows out of the chip through the target pin. In this way, the existing JTAG interface and boundary scan unit in the chip can be used to configure a preset value as a corresponding control parameter for the target pin, and the target pin can be controlled to be in an input enabled state or an output enabled state by this control parameter, without the need to design complex test control circuits in the chip to control the input / output state of the target pin, effectively improving chip design efficiency and integration.

[0087] Specifically, in embodiments of the present invention, when it is necessary to control the input / output state of a target pin in a chip, the BSC corresponding to the target pin can receive a corresponding preset value from an external source (e.g., a host computer) via a JTAG interface. Whether this preset value is 0 or 1 is determined by the external source based on the expected input / output state of the target pin. Furthermore, the chip can generate a corresponding enable control signal based on the preset value in the BSC. In step S12, the input / output control component (e.g., [missing information]) of the target pin is controlled according to the aforementioned enable control signal. Figure 2 The input / output port section (shown in the figure) controls the input / output state. The pin state control method provided in this embodiment can replace the function of a dedicated test control circuit in the chip, thereby controlling the input / output state of the target pin.

[0088] Optionally, in one embodiment of the present invention, the chip may be provided with two or more chip pins, and the target pin is one or more of the chip pins; each chip pin may correspond to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin may be connected in series through their respective serial ports to form a boundary scan chain, and one or both ends of the boundary scan chain may communicate with the outside world through a JTAG interface; based on this, in step S11, generating an enable control signal for an input / output control component corresponding to the target pin based on a preset value shifted into the boundary scan unit corresponding to the target pin via the JTAG interface may include: generating an enable control signal for an input / output control component corresponding to the target pin based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, and generating a redundant signal based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface.

[0089] In embodiments of the present invention, such as Figure 2 As shown, each pin in the chip corresponds to two boundary scan units (BSCs), BC_2 and BC_7. For example, pin 1 corresponds to the first boundary scan unit PAD1_BC_2 and the second boundary scan unit PAD1_BC_7. The BSCs are connected sequentially, forming a boundary scan chain. The preset values ​​in the first boundary scan unit BC_2 of each pin can generate control signals such as the output enable signal PAD1_oe for PAD1, the output enable signal PAD2_oe for PAD2, and the output enable signal PAD3_oe for PAD3. This allows for the control of the enable state of the tri-state output gates corresponding to each pin, placing them in either the output enable state or the input enable state. The values ​​in the second boundary scan unit (BC_7) corresponding to each pin are not used to control the enable state of the tri-state output gates. Therefore, whether the value in BC_7 is 0 or 1 does not affect the input / output state of the corresponding pin. Thus, the signals generated based on the values ​​in BC_7 are redundant. For example, if the preset value in PAD1_BC_2 corresponding to pin 1 is 0, PAD1_oe can be a low-level output enable control signal. If the preset value in PAD1_BC_2 corresponding to pin 1 is 1, PAD1_oe can be a high-level non-output enable control signal. Whether the preset value in PAD1_BC_7 is 0 or 1 will not affect the PAD1_oe signal. Therefore, 0 or 1 can be arbitrarily filled into the second boundary scan unit (i.e., BC_7) corresponding to the target pin to generate redundant signals.

[0090] In practical applications, the BC_7 corresponding to each target pin is connected to the aforementioned input / output control unit. Under the control signal generated by BC_2, the input / output control unit can be in either an input enabled state or an output enabled state. In the input enabled state, the target pin can transmit external input signals to the PI_in (input of the parallel input port) terminal of BC_7 through the input / output control unit, and output signals from the PO_in (output of the parallel input port) terminal of BC_7 (e.g., ...). Figure 2 The data_in_PAD1 signal (shown in the function control and data / test data section) is further transmitted to the internal function / test input section of the chip for processing. Similarly, in the output enable state, the chip's function / test output section can output signals (such as...) Figure 2 The data_out_PAD1 signal shown in the function control and data / test data section is transmitted to the PI_out (input of the parallel output port) port of BC_7, and output from the PO_out (output of the parallel output port) port of BC_7, and further transmitted to the input / output control unit, and finally outputting the output signal from the target pin. It should be noted that boundary scan units have various different structures. In the 2001 version, the IEEE 1149.1 standard introduced 10 different boundary scan unit types (BC_1 to BC_10). In the embodiments of this invention, as shown... Figure 2 As shown, the first scanning unit can be BC_2 and the second boundary scanning unit can be BC_7. However, the embodiments of the present invention do not make any special limitations on this. Boundary scanning units that can achieve the same function as BC_2 and BC_7 in the IEEE 1149.1 standard, or boundary scanning units that can achieve the same function as BC_2 and BC_7 in future related standards, can all be applied to the embodiments of the present invention and are all within the protection scope of the embodiments of the present invention.

[0091] In specific implementations, the shifting operation of a preset value and the generation operation of an enable control signal can be controlled by the drive signal generated by the Test Access Port Controller (TAPC). For example, in one embodiment of the present invention, the generation of an enable control signal for an input / output control unit corresponding to the target pin based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, and the generation of a redundant signal based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface, may include: shifting the preset value and the arbitrary value into the first boundary scan unit and the second boundary scan unit corresponding to the target pin via the JTAG interface under the drive of a first type of signal output by the Test Access Port Controller; and outputting the value from the first boundary scan unit and the second boundary scan unit corresponding to the target pin to their respective parallel output ports under the drive of a second type of signal output by the Test Access Port Controller (TAPC), thereby generating the enable control signal for the input / output control unit and the redundant signal.

[0092] BSC is the core of boundary scan technology. It forms the basic unit of the boundary scan chain, and each BSC consists of registers and multiplexers. Figure 3 A schematic diagram of the internal structure of a boundary scan unit is shown. In this embodiment of the invention, the level of the mode signal determines whether the chip is in JTAG mode or operating mode. Whether all BSCs operate in operating mode or JTAG mode is controlled by the mode signal; it is impossible to operate in both modes simultaneously. The mode signal is controlled by the scan command.

[0093] Combination Figure 2 as well as Figure 3 As shown, when the input at the mode terminal is 0, the chip is in working mode. The data from the parallel input terminal parallel_input is transmitted directly to the parallel output terminal parallel_output through the multiplexer MUX2, without going through the registers Q1 and Q2 in the BSC and the multiplexer MUX1.

[0094] The following explanation uses the example of shifting a preset value to the first boundary scan unit corresponding to the target pin. When the input at the mode terminal is 1, the chip is in JTAG mode. Since the serial input (serial_input) terminal of the first boundary scan unit PAD1_BC_2 corresponding to pin 1 is connected to TDI, when the selector (shiftdr) signal of the multiplexer MUX1 is 1, the preset value is transmitted to the input terminal of register Q1 via the multiplexer MUX1. On the effective edge of the clock input (clockdr) signal of register Q1 (which can be a rising edge or a falling edge, depending on the specific hardware design), the preset value is transmitted from the input terminal of register Q1 to the serial output (serial_output) terminal of PAD1_BC_2 (e.g., ...). Figure 2 As shown). The serial_output terminal of PAD1_BC_2 is connected to the serial_input terminal of PAD1_BC_7, thereby shifting the preset value from PAD1_BC_2 into PAD1_BC_7 (in... Figure 2 In this context, serial_input is abbreviated as SI, and serial_output is abbreviated as SO. Similarly, when the shiftdr signal in PAD1_BC_7 is 1, the preset value is transmitted through the multiplexer MUX1. On the effective edge of clockdr, the preset value is transmitted through the register to the SO terminal of PAD1_BC_7.

[0095] The SO terminal of PAD1_BC_7 is connected to the SI terminal of PAD2_BC_2 on pin 2. Driven by the shiftdr and clockdr signals generated by TAPC, the preset value can be further shifted from the BSC of pin 1 to the BSC of pin 2. The above process is the shifting process of the preset value in the boundary scan chain. Therefore, driven by the shiftdr and clockdr signals generated by TAPC, the preset value can be continuously shifted in the scan chain until it reaches the BSC corresponding to the last pin. Since the BSC of the last pin is connected to the TDO of the JTAG interface, the preset value can also be moved to the TDO signal line. In this embodiment of the invention, it is only necessary to move the preset value to the first boundary scan unit corresponding to the target pin.

[0096] It should be noted that the aforementioned shiftdr and clockdr signals are generated by the TMS and TCK signals in the TAPC. The purpose of the shift process is that the TMS and TCK signals serve as input signals to the TAPC, and the first type of signals generated (including the shiftdr and clockdr signals) act as driving signals, causing the preset value to be shifted from TDI to the scan chain. A certain number of serial shifts are then performed in the scan chain to move the preset value to the first boundary scan unit corresponding to the target pin.

[0097] After the above shifting process is completed, the first boundary scan unit corresponding to each target pin stores the value corresponding to the expected input and output state. For example, if the target pins are pin 1, pin 3 and pin 5, and the expected input and output states are input enable state, input enable state and output enable state respectively, then after the shifting process is completed, the values ​​in register Q1 in the first boundary scan unit (i.e. BC_2) corresponding to the three target pins are 1, 1 and 0 respectively.

[0098] Similarly, since the value in the second boundary scan unit corresponding to the target pin can be arbitrary, when moving any value into the second boundary scan unit corresponding to the target pin, the same method as described above can be used to move the arbitrary value into the second boundary scan unit corresponding to the target pin.

[0099] After the shifting process is completed, the next step is to perform an update process. For the first boundary scan unit corresponding to the target pin, the preset value in Q1 of the first boundary scan unit needs to be shifted into register Q2, and then output to the PO terminal through Q2, thereby generating the corresponding PADn_oe enable control signal. Based on the previous example, this means that the PO terminal corresponding to pin 1 outputs a low-level output enable control signal, the PO terminal corresponding to pin 3 outputs a low-level output enable control signal, and the PO terminal corresponding to pin 5 outputs a high-level non-output enable control signal. Similarly, for the second boundary scan unit corresponding to the target pin, the process of generating redundant signals is similar to the above process and will not be described in detail here.

[0100] The global signal lines mode, shiftdr, updatedr (updatedataregister), and clockdr are connected to all BSCs, and their states are identical at the same time. Therefore, during the shift process, the preset values ​​in all BSCs are simultaneously shifted serially under the drive of the shiftdr and clockdr signals.

[0101] During the update process, all preset values ​​stored in the first boundary scan units are simultaneously driven by the valid edge of the updater signal, and are therefore simultaneously output at their respective PO terminals, thereby generating enable control signals at the PO terminals corresponding to all target pins. Therefore, during the update process, when mode = 1 and at the valid edge of the updater signal, the preset values ​​in the BSC corresponding to all target pins are output to their respective PO terminals via their respective registers Q2 and multiplexers MUX2, thereby generating valid enable control signals at each target pin and controlling the corresponding input / output control components to the expected input / output state. Similarly, any values ​​stored in all second boundary scan units also generate corresponding redundant signals under the drive of the second type of drive signal; the process is similar to the above and will not be repeated here.

[0102] Specifically, taking pin 1 as the target pin as an example, after shifting the preset value 1 to PAD1_BC_2 corresponding to the first pin, when mode = 1 and on the valid edge of the updatedr signal, the preset value 1 in Q1 is output to the PO terminal of PAD1_BC_2 through register Q2 and multiplexer MUX2, thereby generating a high-level non-output enable control signal, controlling the input / output control unit of pin 1 in the input enabled state. Similarly, the PO terminals corresponding to pins 3 and 5 also use the same method to generate input / output status control signals.

[0103] Therefore, driven by the second type of signals generated by TAPC (including the updater signal and the mode signal), the preset value input from the JTAG interface can be simultaneously shifted from each BC_2 in the scan chain to the corresponding PO terminal, thereby generating input / output status control signals for each target pin. Simultaneously, the second type of signals generated by TAPC also utilize arbitrary values ​​input to each BC_7 in the scan chain via the JTAG interface, along with multiple redundant signals.

[0104] In specific implementation, the specific input / output states of the target pins can be set according to the specific application scenario of the chip. For example, in one embodiment of the present invention, if the chip needs to be tested, the input / output states of each target pin of the specific test item can be set according to the actual needs of the specific test item, thereby creating test conditions for the specific test item. Optionally, in one embodiment of the present invention, after controlling the input / output control component to be in an input-enabled state or an output-enabled state according to the enable control signal, the pin state control method provided by the embodiment of the present invention may further include: receiving a test signal sent by the test device through the target pin in the input-enabled state; processing the test signal; and outputting the processed signal from the target pin in the output-enabled state.

[0105] In this embodiment of the invention, for example, the target pins of test item 1 are pin 1, pin 3, and pin 5, and their expected enable states are input enable state, input enable state, and output enable state, respectively. After setting the three to their expected input and output states through the aforementioned steps, the test conditions for executing test item 1 have been created. Next, test item 1 can be further executed to verify the functionality of the corresponding functional modules in the chip. Specifically, the chip receives the corresponding test signals through control pins 1 and 3, processes the test signals, generates an output signal, and outputs the output signal through pin 5. After receiving the output signal, the test device can compare it with the expected output signal to determine whether the functional module corresponding to test item 1 is functioning correctly.

[0106] Secondly, embodiments of the present invention provide another method for controlling the pin states of a chip, which can effectively improve chip design efficiency and integration.

[0107] like Figure 4 As shown, another chip pin state control method provided by an embodiment of the present invention may include:

[0108] S21, Generate a preset value based on the expected input / output state of the target pin of the chip;

[0109] If the target pins are pin 1, pin 3 and pin 5 respectively, and the expected input and output states of the three are input enable state, input enable state and output enable state respectively, then the preset values ​​of the three can be determined to be 1, 1 and 0 respectively.

[0110] S22, the preset value is moved into the boundary scan unit corresponding to the target pin through the JTAG interface, so as to control the target pin to be in the input enable state or the output enable state through the boundary scan unit.

[0111] Specifically, preset values ​​1, 1, and 0 can be shifted into the BSCs corresponding to pins 1, 3, and 5 respectively via the JTAG interface, so that the chip can control the input and output states of each target pin through the preset values ​​shifted into each BSC. The detailed implementation process has been described in detail in the previous embodiments and will not be repeated here.

[0112] The chip pin state control method provided by the embodiments of the present invention can generate a preset value based on the expected input / output state of the target pin of the chip, and then move the preset value into the boundary scan unit corresponding to the target pin through a JTAG interface, so as to control the target pin to be in an input enabled state or an output enabled state through the boundary scan unit. In this way, the corresponding preset value can be moved into the boundary scan unit corresponding to the target pin of the chip using the JTAG interface, and the target pin can be controlled in the expected input / output state through the preset value in the boundary scan unit, without designing complex test control circuits in the chip to control the input / output state of the target pin, effectively improving chip design efficiency and integration.

[0113] Optionally, in one embodiment of the present invention, the chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain;

[0114] In order to control each target pin in the chip to be in the expected input or output state, it is necessary to accurately shift preset values ​​into the corresponding target pins. Therefore, generating preset values ​​based on the expected input / output states of the target pins of the chip can specifically include:

[0115] Based on the structure of the boundary scan chain, the positions of the first boundary scan units corresponding to each target pin, the positions of the second boundary scan units corresponding to each target pin, and the positions of the first and second boundary scan units corresponding to each non-target pin are determined.

[0116] The preset value is configured at the position of each first boundary scan unit corresponding to each target pin, and an arbitrary value is configured at the position of each second boundary scan unit corresponding to each target pin. An arbitrary value is configured at the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin. The preset value and the arbitrary value are arranged in the order of the positions of each boundary scan unit in the boundary scan chain to form a value string.

[0117] Accordingly, the step of shifting the preset value into the boundary scan unit corresponding to the target pin via the JTAG interface may specifically include:

[0118] The numerical string is moved into the corresponding boundary scan units in the boundary scan chain via the JTAG interface.

[0119] Based on the aforementioned example, if the target pins are pin 1, pin 3, and pin 5, the preset value corresponding to pin 1 is 1, the preset value corresponding to pin 3 is 1, and the preset value corresponding to pin 5 is 0. There are 10 BSCs corresponding to pins 1 to 5, with each pin corresponding to two BSCs: the first boundary scan unit BC_2 and the second boundary scan unit BC_7. Among these 10 BSCs, three BSCs can generate valid enable control signals, namely BC_2 corresponding to the three target pins mentioned above, namely PAD1_BC_2, PAD3_BC_2, and PAD5_BC_2.

[0120] Each pin in the chip corresponds to two BSCs, BC_2 and BC_7, and the BSCs are connected sequentially end-to-end to form a boundary scan chain, as shown in the specific structure. Figure 2 As shown. The positions of the three BC_2s in the 10 BSCs are the 10th (BC_2 corresponding to pin 1), the 6th (BC_2 corresponding to pin 3), and the 2nd (BC_2 corresponding to pin 5) from the left. The remaining positions are the BC_7s corresponding to the three target pins, which are the 9th, 5th, and 1st positions respectively. The non-target pins include pins 2 and 4, whose corresponding BC_2s and BC_7s are the 3rd, 4th, 7th, and 8th positions respectively.

[0121] Configure the 10th bit from the left of the numerical string as 1, the 6th bit as 1, and the 2nd bit as 0. The other 7 bits are not used to control the input / output state of the target pins; therefore, they can be configured with any value of 0 or 1 without affecting the input / output state of the target pins. For example, configuring all 7 bits as 0 yields the numerical string 0000010001. Then, by generating the corresponding TMS and TCK signals and inputting them into the TAPC, the TAPC can generate the aforementioned first type of signals (including shiftdr and clockdr signals) based on the input TMS and TCK signals. Driven by these first type of signals, the numerical string can be shifted into the boundary scan chain within the chip. This ensures that the values ​​of BC_2 for the three target pins are 1, 1, and 0 respectively, thus shifting each preset value to the corresponding BSC.

[0122] It should be noted that the above-mentioned numerical strings, TMS signals, and TCK signals can be in the format of STIL (Standard Test Interface Language) files. The preset values ​​can be transmitted to the corresponding BSC by connecting a host computer to a JTAG emulator, or the preset values ​​can be transmitted to the corresponding BSC by a test machine. This embodiment of the invention does not limit this.

[0123] Finally, it should be noted that the embodiments of the present invention can also be applied to complex scenarios involving multiple connected identical or different chips. In this case, the scan chains in each chip are connected end to end to form a longer scan chain. The same method as for a single chip can be used to move the preset value to the corresponding BSC through a serial shift operation, thereby generating the corresponding enable control signal in the target pin of each chip.

[0124] In practice, the specific input / output states of the target pins in the chip can be set according to the specific application scenario of the chip. For example, in one embodiment of the present invention, if the chip needs to be tested, the input / output states of the pins corresponding to specific test items can be controlled. To facilitate the control of pin input / output states according to the actual needs of test items, in one embodiment of the present invention, before generating preset values ​​based on the expected input / output states of the target pins of the chip, the method further includes: obtaining the target pins in the chip corresponding to the specific test items.

[0125] Specifically, for a particular test item, the input and output pins used in that test item can be obtained first, which are the target pins. For example, for test item 1, the input pins are pin 1 and pin 3, and the output pin is pin 5. Therefore, the target pins for test item 1 can be determined as pin 1, pin 3, and pin 5. Then, preset values ​​can be generated based on the expected input and output states of each target pin in test item 1.

[0126] Based on the actual needs of a specific test project, the input and output states of each target pin are set to create test conditions for the aforementioned specific test project. In one embodiment of the present invention, after the preset value is moved into the boundary scan unit corresponding to the target pin through the JTAG interface, so as to control the target pin to be in an input enabled state or an output enabled state through the boundary scan unit, the method may further include: sending a command to the test device to execute the specific test project, and receiving the corresponding test results.

[0127] Specifically, based on the aforementioned example, after setting the input and output states of each target pin—that is, setting pins 1 and 3 to input enable and pin 5 to output enable—the conditions for performing a specific test are essentially met. A command to execute the specific test can then be sent to the testing device, enabling the testing device to output test signals to the chip. When the chip outputs test results, the test results are received, thereby allowing verification of the functional implementation of the corresponding modules within the chip based on the test results.

[0128] Optionally, in one embodiment of the present invention, sending a command to the testing device to execute the specific test item and receiving the corresponding test result may include: sending a command to the testing device to execute the specific test item to control the testing device to input a test signal of the specific test item to a target pin in an input enabled state; controlling the testing device to obtain a test output signal from a target pin in an output enabled state; receiving the test output signal and generating a test result based on the test output signal.

[0129] Specifically, based on the aforementioned example, pins 1 and 3 are in the input enable state, and pin 5 is in the output enable state. Since the test device is connected to the chip, after receiving the command from the host computer to execute test item 1, it can control the test device to input test signals to the chip under test through pins 1 and 3. After receiving and processing the test signals, the chip will generate a corresponding output signal on pin 5. Therefore, the host computer can control the test device to obtain the test output signal from pin 5, and thus receive the test output signal from the test device, and generate test results based on the test output signal. By comparing the test results with the expected output signal, and whether the two are consistent, it can be determined whether the function of the module under test in the chip is normal.

[0130] It should be noted that the execution subject of the above method can be a host computer, which can be a computer connected to the chip via a JTAG emulator or a test machine. This embodiment of the invention does not limit this.

[0131] Thirdly, embodiments of the present invention provide a chip 6 that can effectively improve chip design efficiency and integration.

[0132] like Figure 5 As shown, chip 6 includes:

[0133] Boundary scan unit 61 is used to generate an enable control signal for the input / output control component of the target pin based on a preset value shifted in via the JTAG interface; wherein the target pin corresponds to the boundary scan unit.

[0134] The input / output control unit 62 is connected at one end to the boundary scanning unit and at the other end to the target pin. It is used to control the target pin to be in an input enabled state or an output enabled state according to the enable control signal generated by the boundary scanning unit.

[0135] The target pin 63 is connected to the input / output control unit and is used to input a pin signal into the chip in the input enable state, or to output a pin signal from the chip in the output enable state.

[0136] The chip provided in the embodiments of the present invention can generate an enable control signal for the input / output control component of a target pin based on a preset value shifted in via the JTAG interface. Then, based on the enable control signal generated by the boundary scan unit, it controls the target pin to be in an input-enabled state or an output-enabled state. This allows the pin signal to be input to the chip in the input-enabled state or output from the chip in the output-enabled state. In this way, the existing JTAG interface and boundary scan unit in the chip can be used to configure preset values ​​as corresponding control parameters for the target pin. These control parameters control the target pin to be in an input-enabled state or an output-enabled state without designing complex test control circuitry within the chip to control the input / output state of the target pin, effectively improving chip design efficiency and integration.

[0137] Chip 6 has at least two chip pins, and target pin 63 is at least one of the pins of chip 6; each pin of chip 6 corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each pin of chip 6 are connected in series through their respective serial ports to form a boundary scan chain, and at least one end of the boundary scan chain communicates with the outside world through a JTAG interface; the first boundary scan unit is connected to the corresponding input / output control unit 62 through its own parallel output port;

[0138] The first boundary scan unit corresponding to the target pin 63 is used to generate an enable control signal for the input / output control unit corresponding to the target pin 63 based on the value shifted in via the JTAG interface.

[0139] The second boundary scan unit corresponding to target pin 63 is used to generate redundant signals based on the values ​​shifted in via the JTAG interface.

[0140] Optionally, the first boundary scan unit and the second boundary scan unit corresponding to the target pin 63 are specifically used to: receive the value shifted in via the JTAG interface in response to the first type of signal output by the test access port controller TAPC; and output the value to their respective parallel output ports in response to the second type of signal output by the test access port controller TAPC, so as to generate the enable control signal of the input / output control unit 62 and the redundant signal.

[0141] Optionally, chip 6 may also include: functional logic components;

[0142] The input / output control unit 62 is used to receive test signals sent by the test device through the target pin which is in the input enabled state;

[0143] Functional logic components are used to process the test signals;

[0144] The input / output control unit 62 is also used to output the processed signal from the target pin that is in the output enable state.

[0145] Fourthly, embodiments of the present invention provide a host computer 7, which can effectively improve chip design efficiency and integration.

[0146] like Figure 6 As shown, the host computer 7 includes:

[0147] The generation unit 71 is used to generate preset values ​​based on the expected input / output state of the target pin of the chip;

[0148] The shift unit 72 is used to shift the preset value into the boundary scan unit 61 corresponding to the target pin 63 through the JTAG interface, so as to control the target pin 63 to be in the input enabled state or the output enabled state through the boundary scan unit 61.

[0149] The host computer provided in the embodiments of the present invention can generate a preset value based on the expected input / output state of the target pin of the integrated circuit chip, and then move the preset value into the boundary scan unit corresponding to the target pin through the JTAG interface, so as to control the target pin to be in an input enabled state or an output enabled state through the boundary scan unit. In this way, the corresponding preset value can be moved into the boundary scan unit corresponding to the target pin of the integrated circuit chip using the JTAG interface, and the target pin can be controlled in the expected input / output state through the preset value in the boundary scan unit, without designing complex test control circuits in the chip to control the input / output state of the target pin, effectively improving chip design efficiency and integration.

[0150] Optionally, the chip is provided with at least two chip pins, and the target pin 63 is at least one of the pins of the chip 6; each pin of the chip 6 corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain;

[0151] The generating unit 71 is specifically used for:

[0152] Based on the structure of the boundary scan chain, the positions of the first boundary scan units corresponding to each target pin, the positions of the second boundary scan units corresponding to each target pin, and the positions of the first and second boundary scan units corresponding to each non-target pin are determined.

[0153] The preset value is configured at the position of each first boundary scan unit corresponding to each target pin, and an arbitrary value is configured at the position of each second boundary scan unit corresponding to each target pin. An arbitrary value is configured at the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin. The preset value and the arbitrary value are arranged in the order of the positions of each boundary scan unit in the boundary scan chain to form a value string.

[0154] The shift unit 72 is specifically used for:

[0155] The numerical string is moved into the corresponding boundary scan units in the boundary scan chain via the JTAG interface.

[0156] Optionally, the host computer 7 also includes: an acquisition unit, used to acquire the target pin in the chip corresponding to a specific test item before generating a preset value based on the expected input / output state of the target pin of the integrated circuit chip.

[0157] Optionally, the host computer 7 further includes a sending and receiving unit, used to send a command to the testing device to execute the specific test item, and to receive the corresponding test results.

[0158] Optionally, the transmitting and receiving unit is specifically used for:

[0159] Send a command to the testing device to execute the specific test item, so as to control the testing device to input the test signal of the specific test item to the target pin that is in the input enable state;

[0160] The test device is controlled to acquire the test output signal from the target pin that is in the output enable state;

[0161] Receive the test output signal and generate test results based on the test output signal.

[0162] Fifthly, embodiments of the present invention provide a pin state control system for a chip, which can effectively improve chip design efficiency and integration.

[0163] The system includes any of the aforementioned chips and any of the aforementioned host computers, wherein the host computer configures the input / output states of the target pins of the chip.

[0164] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0165] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0166] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0167] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0168] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0169] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of controlling the state of pins of a chip, characterized by, include: Based on the preset value shifted into the boundary scan unit corresponding to the target pin of the chip via the JTAG interface, an enable control signal for the input / output control unit corresponding to the target pin is generated; wherein, the target pin is the pin to be controlled for input / output status. The input / output control component is controlled to be in an input enabled state or an output enabled state according to the enable control signal, so that in the input enabled state, the pin signal flows into the chip through the target pin, or in the output enabled state, the pin signal flows out of the chip through the target pin; The chip has at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through their respective serial ports to form a boundary scan chain, and at least one end of the boundary scan chain communicates with the outside world through a JTAG interface; The generation of the enable control signal for the input / output control unit corresponding to the target pin, based on the preset value shifted in via the JTAG interface in the boundary scan unit corresponding to the target pin of the chip, includes: Based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, an enable control signal for the input / output control unit corresponding to the target pin is generated. Based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface, a redundant signal is generated.

2. The method according to claim 1, characterized in that, The method involves generating an enable control signal for an input / output control unit corresponding to the target pin based on the preset value shifted into the first boundary scan unit corresponding to the target pin via the JTAG interface, and generating a redundant signal based on any value shifted into the second boundary scan unit corresponding to the target pin via the JTAG interface, including: Driven by the first type of signal output by the Test Access Port Controller (TAPC), the preset value and the arbitrary value are shifted into the first boundary scan unit and the second boundary scan unit corresponding to the target pin via the JTAG interface; Driven by the second type of signal output by the Test Access Port Controller (TAPC), the preset value and the arbitrary value are output from the first boundary scan unit and the second boundary scan unit corresponding to the target pin to their respective parallel output ports to generate the enable control signal and the redundant signal of the input / output control component.

3. The method of claim 1, wherein, After controlling the input / output control unit to be in an input-enabled state or an output-enabled state according to the enable control signal, the method further includes: The test signal sent by the test device is received through the target pin which is in the input enabled state; The test signal is processed, and the processed signal is output from the target pin that is in the output enable state.

4. A method of controlling the state of pins of a chip, characterized by, include: Generate a preset value according to an expected input / output state of a target pin of a chip; wherein the target pin is a pin to be controlled in an input / output state; Move the preset value to a boundary scan unit corresponding to the target pin through a JTAG interface, so as to control the target pin to be in an input enable state or an output enable state through the boundary scan unit; The chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through respective serial ports to form a boundary scan chain; The preset value is generated according to the expected input / output state of the target pin of the chip, including: According to the structure of the boundary scan chain, determine the position of each first boundary scan unit corresponding to each target pin, the position of each second boundary scan unit corresponding to each target pin, and the position of the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin; In the position of each first boundary scan unit corresponding to each target pin, the preset value is configured, and in the position of each second boundary scan unit corresponding to each target pin, an arbitrary value is configured, and in the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin, an arbitrary value is configured; the preset value and the arbitrary value are arranged in order according to the position arrangement order of each boundary scan unit in the boundary scan chain to form a value string; The preset value is moved to the boundary scan unit corresponding to the target pin through the JTAG interface, including: The value string is moved to the corresponding boundary scan unit in the boundary scan chain through the JTAG interface.

5. The method of claim 4, wherein, Before the preset value is generated according to the expected input / output state of the target pin of the chip, the method further includes: Obtain the target pin corresponding to a specific test item in the chip.

6. The method of claim 5, wherein, After the preset value is moved to the boundary scan unit corresponding to the target pin through the JTAG interface to control the target pin to be in an input enable state or an output enable state through the boundary scan unit, the method further includes: sending a command to execute the specific test item to a test device, and receiving a corresponding test result.

7. The method of claim 6, wherein, The command to execute the specific test item is sent to the test device to control the test device to input a test signal in the specific test item to the target pin in the input enable state; Control the test device to obtain a test output signal from the target pin in the output enable state; Receive the test output signal and generate a test result according to the test output signal. Include:

8. A chip, characterized by ​ A boundary scan unit is configured to generate an enable control signal of an input-output control component of a target pin according to preset values input through a JTAG interface, wherein the target pin corresponds to the boundary scan unit, and the target pin is a pin to be controlled in an input-output state; The input-output control component is connected to the boundary scan unit at one end and connected to the target pin at the other end, and is configured to control the target pin in an input enable state or an output enable state according to the enable control signal generated by the boundary scan unit; The target pin is connected to the input-output control component, and is configured to input a pin signal into the chip in the input enable state or output the pin signal from the chip in the output enable state; The chip is provided with at least two chip pins, and the target pin is at least one of the chip pins; each chip pin corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each chip pin are connected in series through respective serial ports to form a boundary scan chain, at least one end of the boundary scan chain is connected to the outside through a JTAG interface, and the first boundary scan unit is connected to the corresponding input-output control component through a parallel output port thereof; The first boundary scan unit corresponding to the target pin is configured to generate an enable control signal of an input-output control component corresponding to the target pin according to preset values input through a JTAG interface; The second boundary scan unit corresponding to the target pin is configured to generate a redundant signal according to any value input through a JTAG interface.

9. The chip of claim 8, wherein The first boundary scan unit and the second boundary scan unit corresponding to the target pin are specifically configured to: in response to a first type of signal output by a test access port controller (TAPC), receive the values and the any values input through the JTAG interface, and in response to a second type of signal output by the test access port controller (TAPC), output the preset values and the any values to respective corresponding parallel output ports to generate the enable control signal of the input-output control component and the redundant signal.

10. The chip of claim 8, wherein, Further comprising: A functional logic component; The input-output control component is further configured to receive a test signal sent by a test device through the target pin in the input enable state; The functional logic component is configured to process the test signal; The input-output control component is further configured to output the signal processed by the functional logic component from the target pin in the output enable state.

11. A host computer, characterized by Comprising: A generation unit is configured to generate preset values according to an expected input-output state of a target pin of a chip, wherein the target pin is a pin to be controlled in an input-output state; A shift unit is configured to input the preset values into a boundary scan unit corresponding to the target pin through a JTAG interface, so as to control the target pin in an input enable state or an output enable state through the boundary scan unit; The chip is provided with at least two chip pins, the target pin is at least one of the chip pins; each of the chip pins corresponds to a first boundary scan unit and a second boundary scan unit, and the first boundary scan unit and the second boundary scan unit of each of the chip pins are connected in series through respective serial ports in turn to form a boundary scan chain; The generating unit is specifically configured to: According to the structure of the boundary scan chain, determine the position of each first boundary scan unit corresponding to each target pin, the position of each second boundary scan unit corresponding to each target pin, and the position of the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin; In the position of each first boundary scan unit corresponding to each target pin, the preset value is configured, in the position of each second boundary scan unit corresponding to each target pin, any value is configured, and in the first boundary scan unit and the second boundary scan unit corresponding to each non-target pin, any value is configured, the preset value and the arbitrary value are arranged in order according to the position arrangement order of each boundary scan unit in the boundary scan chain, forming a value string; The shifting unit is specifically configured to: Shift the value string into the corresponding boundary scan unit in the boundary scan chain through the JTAG interface.

12. The host computer of claim 11, wherein, Further comprising: An acquisition unit is configured to, before generating the preset value according to the expected input and output state of the target pin of the chip, acquire the target pin corresponding to a specific test item in the chip.

13. The host computer of claim 12, wherein, Further comprising: A sending and receiving unit is configured to send a command to execute the specific test item to a test device, and receive a corresponding test result.

14. The host computer of claim 13, wherein, The sending and receiving unit is specifically configured to: Send a command to execute the specific test item to the test device, so as to control the test device to input a test signal in the specific test item to the target pin in the input enable state; Control the test device to acquire a test output signal from the target pin in the output enable state; Receive the test output signal, and generate a test result according to the test output signal.

15. A pin state control system for a chip, characterized in that, The chip according to any one of claims 8 to 10 and the host computer according to any one of claims 11 to 14, wherein the input and output state of the target pin of the chip is configured through the host computer.

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