A system verification simulation method, system, device, and medium

Abstract

The application discloses a system verification simulation method, comprising the following steps: configuring random constraints for each simulation verification environment; starting a simulation verification process in each simulation verification environment according to the configured random constraints and recording coverage into a corresponding coverage result file; periodically scanning each coverage result file; updating the random constraints of the corresponding simulation verification environment in response to the coverage in the coverage result file not reaching a preset value; ending the simulation verification process in the corresponding simulation verification environment in response to the coverage in the coverage result file reaching the preset value. The application also discloses a system, a computer device and a readable storage medium. The scheme provided by the application can perform simulation on multiple simulation environments in parallel, and can automatically switch the random constraints of each verification environment according to the self-defined rules, thereby improving the automation degree and the efficiency of parallel simulation verification.

Description

Technical Field

[0001] This invention relates to the field of chip simulation, and more specifically to a system verification simulation method, system, device, and storage medium. Background Technology

[0002] As process technology and application fields continue to develop, the complexity of chips is constantly increasing, and correspondingly, the requirements for simulation verification are also constantly rising. Not only are the functional points requiring simulation verification becoming increasingly complex, but the verification cycle requirements are also becoming increasingly stringent.

[0003] The existing chip design flow is divided into two stages: front-end design (logic design) and back-end design (physical design). Front-end design primarily implements the chip's logic functions using hardware description languages ​​(such as Verilog), and the correctness of the code description is mainly verified through simulation of this code (or the netlist generated from it). In a standard simulation verification process, the functional points of the logic involved in the front-end design need to be verified by constructing corresponding simulation scenarios to confirm the correctness of the front-end design logic functions.

[0004] For simulation verification of highly complex systems, randomized verification is a crucial step, allowing for the coverage of more complex and even unexpected scenarios with minimal human intervention. Randomized stimuli can generate a large amount of stimulus data with just a few lines of code, expanding the test space for verification by providing random stimulus signals to the design. However, when the design is large and highly complex, the randomized verification space becomes nearly infinite. Therefore, it's necessary to impose constraints on the randomization process to ensure that it generates randomized stimuli according to these constraints, meaning that the generated randomized stimuli fall more within the effective region or boundaries to achieve functional coverage requirements more quickly. Thus, the choice of randomized constraints also determines the efficiency of randomized verification. Overly broad constraints result in most randomly generated scenarios being meaningless, while overly strict constraints limit the types of scenarios that can be randomly generated.

[0005] In existing simulation verification, targeted verification is generally coverage-driven, which constructs specific stimuli for targeted verification by analyzing the coverage of functional points (or critical lines of code). However, as the scale of chips under verification continues to increase, more random verification is being introduced into coverage-driven verification to improve efficiency and shorten the verification cycle. By analyzing coverage, different random constraints are added to construct more verification scenarios. Then, for functional points that cannot be covered by random verification, specific targeted verification is constructed.

[0006] In the current mainstream verification process, the selection of random constraints still relies more on engineers to monitor and analyze the process of each random simulation verification, and manually adjust the random constraints according to the progress of the random verification. Although this approach ensures that there is no waste of extra time and simulation resources, its efficiency and accuracy depend entirely on the engineers, and the challenges become increasingly greater as the complexity and scale of the system increase.

[0007] To shorten the verification cycle with limited human resources, it is necessary to increase the parallelism of random verification, that is, to use more resources to start multiple simulation verification environments simultaneously. To increase the diversity of random verification scenarios, different verification environments will adopt different random constraints. Then, the decision to end the simulation is made manually or by writing automated scripts, and the verification results are collected, summarized and analyzed.

[0008] Existing parallel simulation methods have two main drawbacks: first, insufficient automation, as engineers still need to manually modify and restart simulations to select and switch random constraints; and second, a lag in the aggregation of verification results, because the actual overall coverage of each simulation verification process can only be summarized and statistically analyzed after verification is completed, and the completion time of verification for each verification environment usually varies significantly. Therefore, if the selection of random constraints for the next round of random verification needs to be determined based on the current execution status of parallel random verifications, it is necessary to wait until all verifications are completed, which reduces efficiency. Summary of the Invention

[0009] In view of this, in order to overcome at least one aspect of the above problems, embodiments of the present invention propose a system verification simulation method, comprising the following steps:

[0010] Configure random constraints for each simulation verification environment;

[0011] The simulation verification process in each simulation verification environment is started according to the configured random constraints, and the coverage is recorded to the corresponding coverage result file.

[0012] Periodically scan each coverage result file;

[0013] In response to the coverage result file showing that the coverage has not reached the preset value, the random constraints of the corresponding simulation verification environment are updated.

[0014] When the coverage in the coverage results file reaches the preset value, the simulation verification process in the corresponding simulation verification environment ends.

[0015] In some embodiments, it also includes:

[0016] In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

[0017] In some embodiments, in response to the coverage in the coverage result file not reaching a preset value, updating the random constraints of the corresponding simulation verification environment further includes:

[0018] In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm.

[0019] Record the updated random constraints to the random constraint file.

[0020] In some embodiments, it also includes:

[0021] Upon receiving a unified termination command, all simulation verification processes are terminated.

[0022] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a system verification simulation system, comprising:

[0023] The configuration module allows you to configure random constraints for each simulation verification environment.

[0024] The startup module is configured to start the simulation verification process in each simulation verification environment according to the configured random constraints and record the coverage to the corresponding coverage result file;

[0025] The scanning module is configured to periodically scan each coverage result file;

[0026] The update module is configured to update the random constraints of the corresponding simulation verification environment in response to the coverage result file not reaching the preset value.

[0027] The module is configured to terminate the simulation verification process in the corresponding simulation verification environment in response to the coverage result file reaching a preset value.

[0028] In some embodiments, an exception handling module is also included, configured as follows:

[0029] In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

[0030] In some embodiments, the update module is further configured to:

[0031] In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm.

[0032] Record the updated random constraints to the random constraint file.

[0033] In some embodiments, a termination module is also included, configured to:

[0034] Upon receiving a unified termination command, all simulation verification processes are terminated.

[0035] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer device, comprising:

[0036] At least one processor; and

[0037] A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of any of the system verification simulation methods described above.

[0038] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of any of the system verification simulation methods described above.

[0039] The present invention has one of the following beneficial technical effects: the proposed solution can perform simulations in multiple simulation environments in parallel, and can automatically switch random constraints in each verification environment according to custom rules, thereby improving the efficiency of parallel simulation verification while improving the degree of automation, thereby shortening the verification cycle and chip development cycle. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating the system verification simulation method provided in an embodiment of the present invention;

[0042] Figure 2 A flowchart of a system verification simulation method provided for embodiments of the present invention;

[0043] Figure 3 A schematic diagram of the system structure for system verification simulation provided in the embodiments of the present invention;

[0044] Figure 4 A schematic diagram of the structure of a computer device provided for an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0047] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0048] According to one aspect of the present invention, embodiments of the present invention provide a system verification simulation method, such as... Figure 1 As shown, it may include the following steps:

[0049] S1, configure random constraints for each simulation verification environment;

[0050] S2, start the simulation verification process in each simulation verification environment according to the configured random constraints and record the coverage to the corresponding coverage result file;

[0051] S3 periodically scans each coverage result file;

[0052] S4, in response to the coverage result file not reaching the preset value, update the random constraints of the corresponding simulation verification environment;

[0053] S5, in response to the coverage in the coverage result file reaching the preset value, ends the simulation verification process in the corresponding simulation verification environment.

[0054] The proposed solution can perform simulations in multiple simulation environments in parallel and can automatically switch random constraints between various verification environments according to custom rules. This improves the efficiency of parallel simulation verification while increasing the degree of automation, thereby shortening the verification cycle and chip development cycle.

[0055] In some embodiments, S1, random constraints are configured for each simulation verification environment, specifically, such as... Figure 2 As shown, the configuration script can be called uniformly and each simulation verification environment can be started according to different random constraints in the initial configuration. Each simulation verification environment has a random constraint file. The file places the values ​​of various random constraints in a specified format and order. When the simulation verification environment needs to obtain random constraints, it reads the contents of the file to obtain random constraints and generates random stimuli according to the random constraints for subsequent simulation verification.

[0056] In some embodiments, S2, the simulation verification process in each simulation verification environment is started according to the configured random constraints, and the coverage is recorded to the corresponding coverage result file. Specifically, for example... Figure 2 As shown, each simulation verification environment has a corresponding coverage result file, and this file is updated whenever a new coverage target is achieved during simulation verification.

[0057] In some embodiments, it also includes:

[0058] In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

[0059] Specifically, such as Figure 2 As shown, in order to achieve automation of control and management, it is necessary to realize unified recording of the simulation verification process status. Each simulation verification environment will have a corresponding status record file. When the simulation is terminated for various reasons (including simulation errors, system abnormalities, etc.), the information needs to be written to this file; conversely, the simulation time and other information need to be written to the file periodically. The length of the period can be determined according to the actual situation, but generally it should not exceed the preset scan period length in S3.

[0060] In some embodiments, in response to the coverage in the coverage result file not reaching a preset value, updating the random constraints of the corresponding simulation verification environment further includes:

[0061] In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm.

[0062] Record the updated random constraints to the random constraint file.

[0063] Specifically, such as Figure 2 As shown, the random constraint update module can be used to determine whether and how to update random constraints. If the coverage rate does not increase for a certain period of time, it can be determined that the corresponding random constraint needs to be updated. This period is dynamically adjusted based on the coverage rate growth of all simulation verification processes (because the growth rate of coverage rate will definitely slow down as coverage rate increases). As for how to update random constraints, various different algorithms can be used. The simplest one is to iterate and assign a new random constraint value that has not been used in any simulation verification process for each update.

[0064] In some embodiments, it also includes:

[0065] Upon receiving a unified termination command, all simulation verification processes are terminated.

[0066] Specifically, compared to the traditional manual initiation and management of multiple parallel simulation verification processes, this invention aims to implement a simple control and management program to control and manage each parallel simulation verification process and maintain its running state throughout the entire simulation process. Specific functions include: uniformly calling configuration scripts and starting each simulation verification environment according to different initial random constraints; periodically scanning the coverage result files corresponding to each simulation process and sending the coverage results and corresponding random constraint values ​​to the random constraint update module, modifying the corresponding random constraint files according to the feedback results; writing newly generated random constraints into the random constraint files of the corresponding simulation verification environment as needed; periodically scanning each status log file, and displaying or sending prompts to verification personnel when an abnormal termination of a simulation process is detected (other simulation processes continue); and, when necessary, uniformly terminating all simulation verification processes, performing a scan of the coverage and status files of all simulation verification processes before termination and outputting the summarized information.

[0067] This invention proposes a highly automated parallel simulation method for multiple random verification environments for the random simulation verification of large-scale chips. It standardizes the random constraint inputs and simulation result outputs of each simulation verification process, and dynamically updates the random constraints of each simulation verification process by automatically collecting coverage results. This improves the efficiency of parallel simulation for multiple random verification while increasing the degree of automation.

[0068] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a system 400 for system verification simulation, such as... Figure 3 As shown, it includes:

[0069] Configuration module 401 is configured to set random constraints for each simulation verification environment;

[0070] The startup module 402 is configured to start the simulation verification process in each simulation verification environment according to the configured random constraints and record the coverage to the corresponding coverage result file;

[0071] Scanning module 403 is configured to periodically scan each coverage result file;

[0072] Update module 404, configured to update the random constraints of the corresponding simulation verification environment in response to the coverage result file not reaching the preset value;

[0073] End module 405 is configured to terminate the simulation verification process in the corresponding simulation verification environment in response to the coverage in the coverage result file reaching a preset value.

[0074] In some embodiments, an exception handling module is also included, configured as follows:

[0075] In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

[0076] In some embodiments, the update module 404 is further configured to:

[0077] In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm.

[0078] Record the updated random constraints to the random constraint file.

[0079] In some embodiments, a termination module is also included, configured to:

[0080] Upon receiving a unified termination command, all simulation verification processes are terminated.

[0081] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 4 As shown, embodiments of the present invention also provide a computer device 501, comprising:

[0082] At least one processor 520; and

[0083] The memory 510 stores a computer program 511 that can run on the processor. When the processor 520 executes the program, it performs the steps of any of the system verification simulation methods described above.

[0084] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 5 As shown, embodiments of the present invention also provide a computer-readable storage medium 601, which stores computer program instructions 610. When the computer program instructions 610 are executed by a processor, they perform the steps of any of the system verification simulation methods described above.

[0085] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods.

[0086] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.

[0087] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0088] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0089] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0090] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0091] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0092] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A system verification simulation method, characterized in that, Includes the following steps: Configure a random constraint file for each simulation verification environment, and configure random constraints in the random constraint file; The simulation verification process in each simulation verification environment is started according to the configured random constraints, and the coverage is recorded to the corresponding coverage result file. Periodically scan each coverage result file; In response to the coverage result file showing that the coverage has not reached the preset value, the random constraints of the corresponding simulation verification environment are updated. When the coverage in the coverage result file reaches the preset value, the simulation verification process in the corresponding simulation verification environment ends. In response to the coverage result file showing that the coverage has not reached a preset value, the random constraints of the corresponding simulation verification environment are updated, further including: In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm. Record the updated random constraints to the corresponding random constraint file.

2. The method as described in claim 1, characterized in that, Also includes: In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

3. The method as described in claim 1, characterized in that, Also includes: Upon receiving a unified termination command, all simulation verification processes are terminated.

4. A system for system verification simulation, characterized in that, include: The configuration module is configured to configure a random constraint file for each simulation verification environment, and to configure random constraints in the random constraint file. The startup module is configured to start the simulation verification process in each simulation verification environment according to the configured random constraints and record the coverage to the corresponding coverage result file; The scanning module is configured to periodically scan each coverage result file; The update module is configured to update the random constraints of the corresponding simulation verification environment in response to the coverage result file not reaching the preset value. The module is configured to terminate the simulation verification process in the corresponding simulation verification environment in response to the coverage result file reaching a preset value. The update module is also configured as follows: In response to the detection that the coverage in the coverage result file has not reached the preset value and has not been updated for a preset time period, the random constraints of the corresponding simulation verification environment are updated using a preset algorithm. Record the updated random constraints to the random constraint file.

5. The system as described in claim 4, characterized in that, It also includes an exception handling module, configured as follows: In response to the detection of an anomaly during the simulation verification process, the corresponding anomaly information is recorded in the status log file.

6. The system as described in claim 4, characterized in that, It also includes a termination module, configured as follows: Upon receiving a unified termination command, all simulation verification processes are terminated.

7. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of the method as described in any one of claims 1-3.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-3.

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