A chip-based failure analysis platform and chip selection method

Abstract

The present invention relates to a chip-based failure analysis platform and a chip selection method, the platform comprising: a platform access module, used to determine whether an enterprise that wants to enter the platform meets the access conditions, and to grant different levels of platform use rights to the enterprise based on its contribution to the platform; an information collection module, used to obtain chip failure analysis information through platform information collection or enterprise information release; a platform management module, used to review the failed chip information, punish enterprises that publish false information, and give incentives to enterprises through assessment; a statistical analysis module, used to perform statistical analysis on the collected information using mathematical models to extract key information. The present invention effectively integrates various scattered failure analysis cases, realizes standardized and unified management of information, eliminates "information islands", breaks down information barriers, and forms a shareable knowledge platform; the platform plays an important supporting role in chip selection and rapid analysis of chip failures.

Description

Technical Field

[0001] The present invention belongs to the field of chip database management and application technology, and in particular relates to a chip-based failure analysis platform and a chip selection method. Background Art

[0002] Generally speaking, during the development, production, storage and use of chips, they are inevitably affected by the design, process technology, high temperature, static electricity, humidity and other comprehensive environmental stresses, and failure problems will inevitably occur. The causes of failure are complex and changeable, and the analysis is difficult, requiring a lot of manpower, material and financial resources.

[0003] As people's requirements for product quality and reliability continue to increase, failure analysis becomes more and more important.

[0004] For automobile manufacturers, as the core component of the network security and functional safety of intelligent connected vehicles, the safety and reliability of on-board chips run through the entire life cycle of the vehicle. Once the on-board chips fail, it will cause disruption of the vehicle's functions, such as sudden acceleration of the vehicle or failure of the brake lights, which will pose a serious threat to the lives of the passengers in the car.

[0005] Chip failure analysis determines the failure mode and failure mechanism, proposes corrective measures to prevent the recurrence of such failure mode and failure mechanism, reduces and prevents the recurrence of failure phenomena of similar chips, ensures product quality, and improves product competitiveness. At the same time, it can also provide feedback information for enterprise technology development and technological transformation, enhance the core competitiveness of enterprise products, and thus obtain greater economic benefits.

[0006] There are many types of chips, involving a wide range of knowledge and a large amount of information. The complexity and irreversibility of the failure analysis process (complying with the principles of non-destructive, semi-destructive, and destructive analysis), and the exclusivity of the causes of failure require high knowledge reserves and professional capabilities of failure analysis technicians. The construction of chip failure analysis lies in the recording of valuable experience, the geometry of results cases, and the statistical analysis after geometry. The chip failure analysis platform is also a carrier for the continuation of corporate experience. It can provide failure analysis technicians with timely consultation and knowledge, and provide quick extraction of solutions invisibly at work. How to make full use of the chip failure analysis platform to prevent problems before they happen, effectively control the risk factor of chip selection, reduce the risk of use, and improve the reliability of the whole machine has become the focus of more and more companies.

[0007] At present, the chip failure analysis case library platform is fragmented and scattered, mainly based on groups or individuals, unable to achieve resource sharing between individuals, between individuals and teams, and between groups, and lacks resource sustainability and continuity. With the rapid growth of resource information, how to achieve standardized and unified management of information, eliminate "information islands", break down information barriers, and avoid duplication of construction has become an urgent problem to be solved. Summary of the invention

[0008] The purpose of the present invention is to provide a chip-based failure platform and a chip selection method to solve the following technical problems: At present, the chip failure analysis platform is characterized by fragmentation and sporadic nature, and is mainly based on groups or individuals. It is impossible to achieve resource sharing between individuals, between individuals and teams, and between groups. It lacks resource sustainability and continuity. As resource information continues to grow rapidly, how to achieve standardized and unified management of information, eliminate "information islands", break down information barriers, and avoid duplicate construction has become a problem that urgently needs to be solved.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is: a chip failure analysis platform, comprising:

[0010] The platform access module is used to determine whether the enterprises that want to enter the platform meet the access conditions, and grant different levels of platform access rights to enterprises that have entered the platform based on their contribution. Among them, enterprises that have entered the platform can provide chip failure analysis cases to the platform to form a case library;

[0011] Information collection module, used to obtain chip failure analysis information through platform information collection or enterprise information release;

[0012] The platform management module is used to review the information of invalid chips, punish enterprises that publish false information, and evaluate enterprises to give incentives;

[0013] The statistical analysis module is used to use mathematical models to perform statistical analysis on the collected information to extract key information.

[0014] Preferably,

[0015] The access module includes access mode and enterprise permissions. There are two ways for enterprises to join the platform: for leading enterprises or TOP100 enterprises, the enterprises are actively invited by the platform to obtain platform access qualifications; for start-ups or weak enterprises, they can actively apply for access rights from the platform, and they can obtain platform access qualifications after the platform approves them.

[0016] Preferably,

[0017] In the information collection module, the chip failure analysis information includes chip information, failure mode, failure mechanism and failure improvement;

[0018] The chip information includes chip type, chip model, manufacturer, and production batch, wherein the manufacturer includes wafer fabs, packaging and testing plants, and design companies; the chip types include computing, control, storage, communication, power, sensors, and discrete components;

[0019] The failure mode refers to the manifestation of failure, including open circuit, short circuit, parameter drift and functional performance failure;

[0020] The failure mechanism refers to the external or internal factors that lead to failure, and the failure mechanism includes improper use, environmental factors, static electricity, design defects, manufacturing defects, and peripheral circuit mismatch, wherein the manufacturing defects include packaging defects and wafer defects;

[0021] The failure improvement can be divided into complete improvement, partial improvement without affecting the use of main functions, partial improvement with the possibility of affecting functions, and no improvement according to the effect.

[0022] Preferably,

[0023] In the platform management module, the platform evaluates enterprises on a quarterly basis, with the evaluation dimensions being the effectiveness and value level of the published information; the incentive measures include priority access to in-depth information.

[0024] Preferably,

[0025] In the statistical analysis module, the platform associates the collected information, i.e., chip information, failure mechanism, and failure improvement, and extracts key information, including chip failure risk coefficient and failure risk level of a specific process chip in a specific environment;

[0026] The chip failure risk coefficient is comprehensively derived from the failure mode coefficient, the failure mechanism coefficient and the failure improvement coefficient.

[0027] Preferably,

[0028] The failure mode coefficient is divided into four index levels according to the impact of the failure phenomenon on the product function, including the first index, the second index, the third index, and the fourth index; the first index indicates an impact on personal safety; the second index indicates a complete loss of function; the third index indicates a partial loss of function; and the fourth index indicates no obvious impact on the function.

[0029] Preferably,

[0030] The failure mechanism coefficient is divided into four index levels according to the cause of failure, including the fifth index, the sixth index, the seventh index, and the eighth index; the fifth index represents design defects; the sixth index represents manufacturing defects; the seventh index represents application environment factors; and the eighth index represents improper use factors.

[0031] Preferably,

[0032] The failure improvement coefficient is divided into four index levels according to the improvement situation, including the ninth index, the tenth index, the eleventh index, and the twelfth index; the ninth index indicates that it has been completely improved; the tenth index indicates that it has been partially improved and does not affect the use of the main functions; the eleventh index indicates that the partial improvement may still affect the function; the twelfth index indicates no improvement.

[0033] Preferably,

[0034] The chip failure risk coefficient is δ;

[0035] The failure mode coefficient is α;

[0036] The failure mechanism coefficient is β;

[0037] The failure improvement coefficient is γ;

[0038] δ = α × β × γ ;

[0039] The present invention also provides a chip selection method based on the above-mentioned chip-based failure analysis platform, comprising the steps of:

[0040] A01, the chip selection platform collects the selected chip information and auxiliary information;

[0041] A02, matching the selected chip information and auxiliary information of the selected chip with the failure analysis platform;

[0042] A03, if there is a match result, determine the risk level of the selected chip;

[0043] A04, if the determination result is high risk, whether the expert group assessment is available;

[0044] A05: If the risk is low, perform a source-tracing backup.

[0045] Preferably,

[0046] In A01, the selected chip information includes chip type, chip model, manufacturer, and production batch, wherein the chip types include computing, control, storage, communication, power, sensor, and discrete components;

[0047] The auxiliary information includes chip shipment volume, chip urgency, and replaceability.

[0048] Preferably,

[0049] In A03, a shipment index is obtained according to the chip shipment volume, and the shipment index has four levels, which respectively represent super large shipment volume, large shipment volume, small shipment volume, and new product;

[0050] According to the urgency of the chip, a demand index is obtained, and the demand index reflects three situations, namely, reserved adoption, normal adoption, and emergency adoption;

[0051] According to the replaceability, a replaceability index is obtained, and the replaceability index is divided into three categories, namely, mandatory type, optional type, and multiple-choice type;

[0052] The chip failure risk factor is δ;

[0053] The shipment index is з;

[0054] The demand index is м;

[0055] The replaceable index is σ;

[0056] The risk factor of selection is Φ;

[0057] The risk factor of the selected chip is obtained through the following calculation formula, and then the risk level is determined:

[0058] The selection risk coefficient Φ=δ×з×м×σ.

[0059] By adopting the above technical scheme, the beneficial technical effects that can be achieved by the present invention are as follows: the present invention effectively integrates various scattered failure analysis cases, realizes standardized and unified management of information, eliminates "information islands", breaks down information barriers, and forms a shareable knowledge platform; the platform plays an important supporting role in chip selection and rapid analysis of chip failures. By combining the chip selection platform with the present invention, the risk level of the selected chip can be quickly determined. The selected chips that match the platform of the present invention are synthesized by the shipment index з, the demand index м, the replaceable index σ, and the failure risk coefficient δ to obtain the selection risk coefficient Φ=δ×з×м×σ to determine the risk level of the selected chip. Risk assessment is performed according to the internal evaluation indicators of the enterprise. The selected chips determined to be high-risk are further evaluated by the internal expert group of the enterprise for use; the selected chips determined to be low-risk are traced and backed up. For the selected chips without matching results, it is necessary to pay attention to the usage data during use and feedback to the data platform in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 Build a flow chart for a chip-based failure analysis platform;

[0061] Figure 2 This is a schematic diagram of the chip failure analysis platform;

[0062] Figure 3 The chip selection flow chart for the chip-based failure analysis platform. DETAILED DESCRIPTION

[0063] The present invention will be further described below in conjunction with the accompanying drawings.

[0064] like Figure 1 and Figure 2 As shown, the present invention provides a chip-based failure analysis platform, including a platform access module, an information collection module, a platform management module, and a statistical analysis module.

[0065] The platform access module is used to determine whether the enterprises that want to enter the platform meet the access conditions. Based on the contribution of the enterprises that have entered the platform, different levels of platform use rights are given to them. Among them, the enterprises that have entered the platform can provide chip failure analysis cases to the platform to form a case library. The platform access module S101 includes access mode and enterprise permissions. There are two ways for enterprises to join the platform. For leading enterprises or TOP100 enterprises, the platform actively invites them to obtain platform access qualifications; for start-ups or relatively weak enterprises, they can actively apply and obtain platform access qualifications after being recognized by the platform. All injected enterprises can provide chip failure analysis cases to the platform, thus forming a classic, rich and valuable case library platform. The platform can set different levels of platform use permissions based on the contribution of the enterprise, so as to help enterprises realize activities such as chip selection or rapid analysis of failed chips.

[0066] The information collection module is used to obtain chip failure analysis information through platform information collection or enterprise information release. The information collection module S102 obtains chip failure analysis information through platform information collection or enterprise information release, including chip information, failure mode, failure mechanism, and failure improvement.

[0067] The platform management module is used to review the invalid chip information, punish the enterprises that publish false information, and evaluate the enterprises to give incentives. The platform management module S103, the platform reviews the invalid chip information, and specifies certain punishment measures for the enterprises that publish false information.

[0068] The statistical analysis module is used to use mathematical models to perform statistical analysis on the collected information to extract key information. In the statistical analysis module S104, the platform associates chip information, failure mechanism, failure improvement and other data, and uses statistical models to extract key information, such as chip failure risk coefficient, failure risk level of a specific process chip in a specific environment, etc., to provide data support and decision-making basis for chip design, manufacturing, selection, and use. The failure risk coefficient is derived from the failure mode coefficient, failure mechanism coefficient, and failure improvement coefficient.

[0069] Specifically, the platform access module includes access mode and enterprise permissions. There are two ways for enterprises to join the platform: for leading enterprises or TOP100 enterprises, the platform actively invites them to obtain platform access qualifications; for start-ups or weak enterprises, they can actively apply for access rights from the platform, and they can obtain platform access qualifications after the platform recognizes them. The platform access module S101 includes access mode and enterprise permissions. There are two ways for enterprises to join the platform: for leading enterprises or TOP100 enterprises, the platform actively invites them to obtain platform access qualifications; for start-ups or relatively weak enterprises, they can actively apply, and they can obtain platform access qualifications after obtaining platform recognition. All admitted enterprises can provide chip failure analysis cases to the platform, thus forming a classic, rich and valuable case library platform. The platform can set different levels of platform usage permissions according to the contribution of the enterprise, so as to help enterprises realize chip selection or rapid analysis of failed chips.

[0070] In the information collection module, chip failure analysis information includes chip information, failure mode, failure mechanism and failure improvement; chip information includes chip type, chip model, manufacturer, production batch, among which manufacturers include wafer fabs, packaging and testing plants and design companies; chip types include computing, control, storage, communication, power supply, sensors and discrete components; failure mode refers to the manifestation of failure, including open circuit, short circuit, parameter drift and functional performance failure;

[0071] Failure mechanism refers to external or internal factors that lead to failure. Failure mechanisms include improper use, environmental factors, static electricity, design defects, manufacturing defects, and peripheral circuit mismatch. Manufacturing defects include packaging defects and wafer defects. Failure improvement can be divided into complete improvement, partial improvement without affecting the main function, partial improvement that may still affect the function, and no improvement according to the effect.

[0072] In the platform management module, the platform evaluates enterprises on a quarterly basis, and the evaluation dimensions are based on the effectiveness and value level of the information released; the incentive measures include priority access to in-depth information. In the platform management module S103, the platform reviews the information of invalid chips and specifies certain disciplinary measures for enterprises that publish false information. The platform evaluates participating enterprises on a quarterly basis, and the evaluation dimensions can be based on the effectiveness and value level of the information released, and formulates certain incentive measures, such as priority access to in-depth information.

[0073] In the statistical analysis module, the platform correlates the collected information, i.e., chip information, failure mechanism, and failure improvement, and extracts key information, including the chip failure risk coefficient and the failure risk level of a specific process chip in a specific environment.

[0074] The chip failure risk coefficient is derived from the failure mode coefficient, failure mechanism coefficient, and failure improvement coefficient.

[0075] The failure mode coefficient is divided into four index levels according to the degree of influence of the failure phenomenon on the product function, including the first index, the second index, the third index, and the fourth index; the first index indicates that personal safety is affected; the second index indicates that the function is completely lost; the third index indicates that the function is partially lost; and the fourth index indicates that the function has no obvious impact. The failure mode coefficient α can be divided into four index levels according to the degree of influence of the failure phenomenon on the product function: 1 for affecting personal safety, 0.7 for complete loss of function, 0.4 for partial loss of function, and 0.1 for no obvious impact on function.

[0076] The failure mechanism coefficient β is divided into four index levels according to the cause of failure, including the fifth index, the sixth index, the seventh index, and the eighth index; the fifth index represents design defects; the sixth index represents manufacturing defects; the seventh index represents application environment factors; and the eighth index represents improper use factors. The failure mechanism coefficient β can be divided into four index levels according to the cause of failure: 1 represents design defects, 0.7 represents manufacturing defects, 0.4 represents application environment factors, and 0.1 represents improper use factors.

[0077] The failure improvement coefficient is divided into four index levels according to the improvement situation, including the ninth index, the tenth index, the eleventh index, and the twelfth index; the ninth index indicates that it has been completely improved; the tenth index indicates that it has been partially improved without affecting the use of the main functions; the eleventh index indicates that the partial improvement may still affect the function; the twelfth index indicates that it has not been improved. The failure improvement coefficient γ can be divided into four index levels according to the improvement situation: 1 represents complete improvement, 0.7 represents partial improvement without affecting the use of the main functions, 0.4 represents partial improvement still may affect the function, and 0.1 represents no improvement.

[0078] The chip failure risk coefficient is δ; the failure mode coefficient is α; the failure mechanism coefficient is β; the failure improvement coefficient is γ; δ=α×β×γ; the failure risk coefficient δ=α×β×γ is obtained by combining the failure mode coefficient, failure mechanism coefficient, and failure improvement coefficient. According to the failure mode and failure phenomenon, through analysis and verification, the failure is simulated to reproduce the failure phenomenon, the real cause of failure is found, the failure mechanism is excavated, and reasonable improvement measures are formulated. All collected information is effectively linked to form a failure analysis platform.

[0079] like Figure 2 As shown, the platform mainly includes chip information S201, failure mode S202, failure mechanism S203, and improvement measures S204.

[0080] The chip information S201 includes chip type (computing, control, storage, communication, power supply, sensor, discrete components, etc.), chip model, manufacturer, production batch, application scenario and others.

[0081] Failure mode S202 is further refined into S205, namely open circuit, short circuit, parameter drift, functional failure and others, and the impact of failure mode S202 on function is further refined into S206, namely affecting personal safety, causing loss of function, affecting partial function, and basically no impact.

[0082] Failure mechanism S203 refers to external or internal factors that lead to failure, including improper use, environmental factors (temperature, humidity, etc.), electrostatic discharge, design defects, manufacturing defects (packaging defects, wafer defects), peripheral circuit mismatch, etc.

[0083] Improvement measures S204 are divided into four categories according to the improvement effect: completely improved, partially improved and not affecting the use of main functions, partially improved and not affecting the use of main functions, partially improved but still likely to affect functions, and unable to be improved.

[0084] The present invention also provides a chip selection method based on the above-mentioned chip-based failure analysis platform. Once a chip fails, it will affect the time to market and brand value of new products and reduce the competitiveness of enterprises. On the other hand, it requires a lot of manpower, financial resources, material resources and time. The construction of the chip failure case library is to record valuable experience, the total price of the results cases, and form a statistical analysis after the collection. It provides an invisible way to quickly extract solutions at work, and is also a carrier for the continuation of corporate business experience. How to make full use of the chip failure analysis case library to prevent problems before they happen, effectively control the risk factor of the selected chip, reduce the risk of use, and improve the reliability of the whole machine has become the focus of more and more companies.

[0085] like Figure 3As shown, the present invention also provides a chip selection method based on the above-mentioned chip failure analysis platform, comprising the steps of:

[0086] A01, the chip selection platform collects the selected chip information and auxiliary information. When selecting the chip, the chip selection platform collects the selected chip information and auxiliary information. The selected chip information includes chip type, chip model, manufacturer, and production batch. The auxiliary information mainly includes chip shipments, chip urgency, and replaceability. A02, match the selected chip information and auxiliary information of the selected chip with the failure analysis platform; A03, if the match has a result, determine the risk level of the selected chip; A04, if the result is determined to be high risk, the expert group will evaluate whether it is available; A05, if the result is determined to be low risk, perform traceability backup.

[0087] In A01, the selected chip information includes chip type, chip model, manufacturer, and production batch. The chip types include computing, control, storage, communication, power, sensors, and discrete components. Auxiliary information includes chip shipments, chip urgency, and replaceability.

[0088] In A03, the shipment index is obtained based on the chip shipment volume. The shipment index has four levels, which represent super large shipment volume, large shipment volume, small shipment volume, and new products. According to the chip shipment volume A, the shipment index з can be divided into four levels: 1 represents super large shipment volume (A≥100kk), 0.7 represents large shipment volume (100 KK ≥ A ≥ 100 K), 0.4 represents small shipment volume (100K ≥ A ≥ 1k), and 0.1 represents new products (A<1K).

[0089] According to the urgency of the chip, the demand index is obtained, which reflects three situations, namely reserved adoption, normal adoption and emergency adoption. According to the urgency, the demand index м includes: 0.2 reserved adoption, 0.5 normal adoption, and 0.8 emergency adoption.

[0090] According to the replaceability, the replaceability index is obtained, which is divided into three categories: mandatory, optional, and multiple choices. According to the replaceability B of the selected chip, the replaceability index σ is divided into four categories, including 1 for mandatory (B=1), 0.5 for optional (3≥ B ≥ 2), and 0.1 for multiple choices (B ≥ 4).

[0091] The chip failure risk coefficient is δ; the shipment index is з; the demand index is м; the replaceability index is σ; the selection risk coefficient is Φ; the selection risk coefficient of the selected chip is obtained by the following calculation formula, and then the risk level is determined:

[0092] The selection risk coefficient Φ=δ×з×м×σ . The selected chips that match the chip failure analysis platform are composed of the shipment index з, the demand index м, the replaceable index σ, and the failure risk coefficient δ to obtain the selection risk coefficient Φ=δ×з×м×σ. Risk assessment is carried out according to the internal evaluation indicators of the enterprise. The selected chips judged to be high-risk are further evaluated by the internal expert group of the enterprise for use. The selected chips judged to be low-risk are traced and backed up. For the selected chips without matching results, it is necessary to pay attention to the usage data during use and feedback to the data platform in a timely manner.

[0093] The present invention effectively integrates various scattered failure analysis cases, realizes the standardization and unified management of information, eliminates "information islands", breaks down information barriers, and forms a shareable knowledge platform, which plays an important supporting role in chip selection and rapid analysis of chip failures.

Claims

1. A chip-based failure analysis platform, characterized in that: include: The platform access module is used to determine whether the enterprises that want to enter the platform meet the access conditions, and grant different levels of platform access rights to the enterprises that have entered the platform based on their contribution. Among them, the enterprises that have entered the platform can provide chip failure analysis cases to the platform to form a case library; Information collection module, used to obtain chip failure analysis information through platform information collection or enterprise information release; The platform management module is used to review the information of invalid chips, punish enterprises that publish false information, and evaluate enterprises to give incentives; Statistical analysis module, used to use mathematical models to perform statistical analysis on collected information to extract key information; In the information collection module, the chip failure analysis information includes chip information, failure mode, failure mechanism and failure improvement; The chip information includes chip type, chip model, manufacturer, and production batch, wherein the manufacturer includes wafer fabs, packaging and testing plants, and design companies; the chip types include computing, control, storage, communication, power, sensors, and discrete components; The failure mode refers to the manifestation of failure, including open circuit, short circuit, parameter drift and functional performance failure; The failure mechanism refers to the external or internal factors that lead to failure, and the failure mechanism includes improper use, environmental factors, static electricity, design defects, manufacturing defects, and peripheral circuit mismatch, wherein the manufacturing defects include packaging defects and wafer defects; The failure improvement can be divided into complete improvement, partial improvement without affecting the main function, partial improvement with the possibility of affecting the function, and no improvement according to the effect; In the statistical analysis module, the platform associates the collected information, i.e., chip information, failure mechanism, and failure improvement, and extracts key information, including chip failure risk coefficient and failure risk level of a specific process chip in a specific environment; The chip failure risk coefficient δ is obtained by combining the failure mode coefficient α, the failure mechanism coefficient β, and the failure improvement coefficient γ, δ=α×β×γ.

2. The platform according to claim 1, characterized in that The platform access module includes access mode and enterprise permissions. There are two ways for enterprises to join the platform: for strong enterprises, the enterprises are actively invited by the platform to obtain platform access qualifications; for start-ups or weak enterprises, they can actively apply for access rights from the platform, and they can obtain platform access qualifications after the platform approves them.

3. The platform according to claim 1, characterized in that: In the platform management module, the platform evaluates enterprises on a quarterly basis, with the evaluation dimensions being the effectiveness and value level of the published information; the incentive measures include priority access to in-depth information.

4. The platform according to claim 1, characterized in that: The failure mode coefficient is divided into four index levels according to the impact of the failure phenomenon on the product function, including the first index, the second index, the third index, and the fourth index; the first index indicates an impact on personal safety; the second index indicates a complete loss of function; the third index indicates a partial loss of function; and the fourth index indicates no obvious impact on the function.

5. The platform according to claim 1, characterized in that: The failure mechanism coefficient is divided into four index levels according to the cause of failure, including the fifth index, the sixth index, the seventh index, and the eighth index; the fifth index represents design defects; the sixth index represents manufacturing defects; the seventh index represents application environment factors; and the eighth index represents improper use factors.

6. The platform according to claim 1, characterized in that: The failure improvement coefficient is divided into four index levels according to the improvement situation, including the ninth index, the tenth index, the eleventh index, and the twelfth index; the ninth index indicates that it has been completely improved; the tenth index indicates that it has been partially improved and does not affect the use of the main functions; the eleventh index indicates that the partial improvement may still affect the function; the twelfth index indicates no improvement.

7. A chip selection method based on the chip-based failure analysis platform according to any one of claims 1 to 6, characterized in that: The steps involved are: A01, the chip selection platform collects selected chip information and auxiliary information; the selected chip information includes chip type, chip model, manufacturer, and production batch, wherein the chip types include computing, control, storage, communication, power, sensor, and discrete components; The auxiliary information includes chip shipments, chip urgency, and replaceability; A02, matching the selected chip information and auxiliary information of the selected chip with the failure analysis platform; A03, if there is a match result, determine the risk level of the selected chip; A04, if the determination result is high risk, whether the expert group assessment is available; A05: If the risk is low, perform a source-tracing backup.

8. The method according to claim 7, characterized in that In A03, a shipment index is obtained according to the chip shipment volume, and the shipment index has four levels, which respectively represent super large shipment volume, large shipment volume, small shipment volume, and new product; According to the urgency of the chip, a demand index is obtained, and the demand index reflects three situations, namely, reserved adoption, normal adoption, and emergency adoption; According to the replaceability, a replaceability index is obtained, and the replaceability index is divided into three categories, namely, mandatory type, optional type, and multiple-choice type; The chip failure risk factor is δ; The shipment index is з; The demand index is м; The replaceable index is σ; The risk factor of selection is Φ; The risk factor of the selected chip is obtained through the following calculation formula, and then the risk level is determined: The selection risk coefficient Φ=δ×з×м×σ.

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