Method of manufacturing a semiconductor device

Abstract

Embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a dummy gate electrode layer on a gate dielectric layer; forming a patterned mask layer above the dummy gate electrode layer; using the patterned mask layer as a mask, patterning the dummy gate electrode layer into a plurality of patterned dummy gate electrodes, the patterned dummy gate electrodes being spaced apart from each other such that each patterned dummy gate electrode has a top-wide and bottom-narrow profile in a cross-sectional view, wherein the patterning includes etching the dummy gate electrode layer with increasingly stronger lateral etching characteristics; forming gate spacers on the sidewalls of the patterned dummy gate electrodes; and replacing the patterned dummy gate electrodes with a metal-containing gate electrode.

Description

[0001] Divisional application

[0002] This application is a divisional application of patent application No. 201710680527.7, filed on August 10, 2017, entitled "Reducing Metal Gate Suspension by Forming a Pseudo Gate Electrode with a Wide Top and Narrow Bottom". Technical Field

[0003] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to a method for manufacturing semiconductor devices. Background Technology

[0004] The semiconductor integrated circuit (IC) industry has experienced rapid development. Technological advancements in IC materials and design have yielded generation after generation of ICs, each with smaller and more complex circuitry than the previous generation. However, these advancements have increased the complexity of handling and manufacturing ICs, requiring similar developments in IC handling and manufacturing to achieve these advancements. Throughout the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased.

[0005] To facilitate the scaling down of semiconductor devices, metal gate electrodes can be used instead of traditional polysilicon electrodes. The formation of a metal gate electrode can include a gate replacement process where a dummy gate electrode is removed to form an opening in its place, and the opening is subsequently filled with a metal material to form the metal gate electrode. However, conventional gate replacement processes may leave suspended portions in the opening, which can hinder the metal material from filling the opening. Therefore, voids may form in the metal gate, degrading the performance of the semiconductor device.

[0006] Therefore, while existing gate replacement processes are generally sufficient for their intended purposes, they are not entirely satisfactory in every respect. Summary of the Invention

[0007] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a polysilicon layer over a substrate; etching the polysilicon layer to form a dummy gate electrode, the dummy gate electrode including a top portion having a first lateral dimension and a bottom portion having a second lateral dimension, the first lateral dimension being greater than or equal to the second lateral dimension; and replacing the dummy gate electrode with a metal gate electrode.

[0008] According to other embodiments of the present invention, a method for manufacturing a semiconductor device is also provided, the method comprising: forming a gate dielectric layer over a substrate; forming a dummy gate electrode layer over the gate dielectric layer; etching the dummy gate electrode layer with an etchant comprising fluorine and chlorine to form a dummy gate electrode, wherein the etching comprises increasing the fluorine content of the etchant as the etching penetrates deeper into the dummy gate electrode layer; forming spacers on the sidewalls of the dummy gate electrode; forming source / drain regions on opposite sides of the dummy gate electrode and in the substrate; and replacing the dummy gate electrode with a metal gate electrode.

[0009] According to further embodiments of the present invention, a semiconductor device is also provided, comprising: a high-k gate dielectric layer disposed above a substrate; and a metal gate electrode disposed above the high-k gate dielectric layer; wherein: the metal gate electrode has a top portion and a bottom portion, the bottom portion being closer to the high-k gate dielectric layer than the top portion; the top portion having a first lateral dimension; the bottom portion having a second lateral dimension; and the first lateral dimension being not less than the second lateral dimension. Attached Figure Description

[0010] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0011] Figure 1 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0012] Figure 2 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0013] Figure 2A This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0014] Figure 3 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0015] Figure 4 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0016] Figure 5 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0017] Figure 6 This is a schematic cross-sectional side view of a semiconductor device in the manufacturing stage according to various embodiments of the present invention.

[0018] Figure 7 Several suitable cross-sectional profiles of dummy gate electrodes manufactured according to various embodiments of the present invention are shown.

[0019] Figure 8 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0022] With advancements in semiconductor manufacturing technology, metal-gate transistors (MTTs) have been used in recent years to enhance IC performance. MMTs utilize metal gate electrodes instead of traditional polysilicon gate electrodes. The manufacturing process for MMTs can include a gate replacement process, where a polysilicon dummy gate electrode is replaced with a metal gate electrode after the source / drain regions are formed. However, due to the scaling down of semiconductor devices, critical dimensions (e.g., gate width) are becoming increasingly smaller, while aspect ratios (e.g., the ratio between gate height and gate width) can increase. Small gate diameters (CDs) and high aspect ratios can lead to problems or difficulties in replacing polysilicon dummy gate electrodes with metal gate electrodes. For example, a small CD and high aspect ratio can result in a "dangling" condition, where an opening is partially blocked (formed by removing the dummy polysilicon gate electrode). This can lead to voids in the subsequently formed metal gate electrode within the opening. Voids in the metal gate electrode degrade the performance of the transistor device (e.g., excessive resistivity), which is undesirable.

[0023] To overcome the aforementioned problems, this invention employs a novel etching process in the formation of the dummy gate electrode. This novel etching process alters the contour / shape of the dummy gate electrode, causing the top portion of the dummy gate electrode to be wider than (or at least not narrower than) the bottom portion. This contrasts sharply with conventionally manufactured dummy gate electrodes, where the top is narrower than the bottom. As will become more apparent from the following discussion, the unique contour of the dummy gate electrode results in openings (formed through their removal) being more easily filled with metallic material in subsequent processes, leading to a substantially void-free metallic gate electrode. (Refer to below...) Figures 1 to 8 The details of this invention will be discussed.

[0024] Figures 1 to 6 This is a simplified schematic partial cross-sectional side view of the semiconductor device 35 during various manufacturing stages. The semiconductor device 35 may be part of an integrated circuit (IC) chip, a system-on-a-chip (SoC), or a portion thereof. It may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, laterally diffused MOS transistors (LDMOS), high-power MOS transistors, or other types of transistors. It should be understood that simplifications have been made for a better understanding of the inventive concept of the present invention. Figures 1 to 6 Therefore, it should be noted that it is possible to... Figures 1 to 6 Additional processes are provided before, during, and after the process shown to complete the fabrication of semiconductor device 35, and only a few other processes may be briefly described herein.

[0025] refer to Figure 1The semiconductor device 35 has a substrate 40. The substrate 40 is a silicon substrate doped with a P-type dopant such as boron (e.g., a P-type substrate). Optionally, the substrate 40 can be other suitable semiconductor materials. For example, the substrate 40 can be a silicon substrate doped with an N-type dopant such as phosphorus or arsenic (an N-type substrate). The substrate 40 can optionally be made of some other suitable elemental semiconductor such as diamond or germanium; suitable compound semiconductors such as silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. Furthermore, the substrate 40 may include an epitaxial layer (epi layer) that can be strained for performance enhancement and may include a silicon-on-insulator (SOI) structure.

[0026] Still referencing Figure 1 A shallow trench isolation (STI) component 45 is formed in a substrate 40. The STI component 45 is formed by etching recesses (or trenches) in the substrate 45 and filling the recesses with a dielectric material. In this embodiment, the dielectric material of the shallow trench isolation component 45 includes silicon oxide. In alternative embodiments, the dielectric material of the STI component 45 may include silicon nitride, silicon oxynitride, fluorine-doped silicate (FSG), and / or low-k dielectric materials known in the art. In other embodiments, a deep trench isolation (DTI) component may be formed instead of or in combination with the STI component 45.

[0027] An interface layer may optionally be formed above the substrate 40. The interface layer may be formed by an atomic layer deposition (ALD) process and may include silicon oxide (SiO2).

[0028] A gate dielectric layer 60 is formed above the upper surface of the substrate 40 (or above the interface layer if an interface layer is formed). In some embodiments, the gate dielectric layer 60 can be formed by an ALD process. In some embodiments, the gate dielectric layer 60 comprises a high-k dielectric material. A high-k dielectric material is a material having a dielectric constant greater than that of SiO2 (about 4). In an embodiment, the gate dielectric layer 60 comprises hafnium oxide (HfO2) having a dielectric constant in the range of about 18 to about 40. In alternative embodiments, the gate dielectric layer 60 may comprise one of ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, and SrTiO.

[0029] A capping layer 70 is formed over the gate dielectric layer 60. The formation of the capping layer 70 includes one or more deposition and patterning processes. In some embodiments, the capping layer 70 comprises lanthanum oxide (LaO) material. x(where x is an integer), but it should be understood that the covering layer may include other suitable materials (e.g., such as LaO2). x GdO x D y O x Or ErO x (Rare earth oxides). In some embodiments, the material of the capping layer can be selected such that it helps to adjust the work function of the transistor gate (formed later) to achieve the desired threshold voltage for the transistor. It should be understood that during this fabrication stage, both the gate dielectric layer 60 and the capping layer 70 are formed over both the NMOS transistor region and the PMOS transistor region. In some embodiments, the thickness of the capping layer is in the range of about 5 angstroms to about 20 angstroms.

[0030] A polysilicon layer 80 is formed over the capping layer 70. The polysilicon layer 80 is then patterned to form a dummy gate electrode. A patterned hard mask layer 90 is formed over the polysilicon layer 80. In some embodiments, the patterned hard mask layer 90 comprises multiple layers with different material compositions. For example, the patterned hard mask layer 90 may include a silicon nitride layer formed over the polysilicon layer 80, and may also include a silicon oxide layer formed over the silicon nitride layer. The patterned hard mask layer 90 can be patterned into multiple segments, such as segments 90A and 90B, using a photolithography process.

[0031] Now for reference Figure 2 Sections 90A and 90B of the patterned hard mask layer 90 can be used as masks to define the gate structure of the transistor. More specifically, an etching process 100 is performed to etch the polysilicon layer 80. Sections 90A and 90B of the patterned hard mask layer 90 are used as etching masks in the etching process 100 to protect portions of the underlying layers (including the polysilicon layer 80, the capping layer 70, and the gate dielectric layer 60) from being etched.

[0032] Etching process 100 forms gate structures 120A and 120B separated by opening 130. Gate structure 120A includes segment 90A, the remaining portion 80A of the polysilicon layer, the remaining portion 70A of the capping layer, and the remaining portion 60A of the gate dielectric layer. Gate structure 120B includes segment 90B, the remaining portion 80B of the polysilicon layer, the remaining portion 70B of the capping layer, and the remaining portion 60B of the gate dielectric layer. It should be understood that the remaining portions 80A and 80B of the polysilicon layer are used here as dummy gate electrodes and will be removed in a subsequent dummy gate replacement process.

[0033] According to an embodiment of the invention, etching process 100 is configured to form dummy gate electrodes 80A-80B with their sidewall profiles inclined inward. For example, dummy gate electrodes 80A (or 80B) have a lateral dimension 140 near their upper surface and a lateral dimension 141 near their bottom surface. The lateral dimension 140 is greater than or equal to (or not less than) the lateral dimension 141. In some embodiments, the lateral dimension 140 is at least 5% larger than the lateral dimension 141, for example, about 5%-20%, therefore, Figure 2 The dummy gate electrodes 80A and 80B shown both have a loosely similar cross-sectional profile / shape to an inverted or upside-down trapezoid. However, it should be understood that in real-world manufacturing, the sidewall surfaces of the dummy gate electrodes 80A-80B may not resemble such a shape. Figure 2 As shown, it is straight or smooth because Figure 2 Only simplified illustrations are provided.

[0034] The inverted trapezoidal shape of the dummy gate electrodes 80A-80B is obtained by configuring the lateral etching characteristics of the etching process 100. For example, the etching process 100 may be configured to have increasingly stronger lateral etching characteristics as the etching proceeds deeper (i.e., closer to the substrate 40). In some embodiments, the etching process 100 includes multiple etching steps, wherein each etching step has an associated lateral etching rate, and each subsequent etching step has a greater lateral etching rate than the previous etching step.

[0035] The etching process (or the various etching steps included therein) may include the simultaneous application of a highly electronegative etchant and a chlorine etchant within an etching chamber, with the wafer undergoing etching process 100 placed in the etching chamber. In some embodiments, the chlorine etchant may include a Cl2 gas or plasma having a flow rate in the range of about 30 standard cubic centimeters per minute (sccm) to about 36 sccm, and the highly electronegative etchant may include a fluorinated gas or plasma having a flow rate in the range of about 80 sccm to about 120 sccm. As a non-limiting example, the fluorinated gas or plasma may include, for example, C x F y (Where x and y are positive integers, such as CF4 or C2F6), fluorine-rich materials such as CHF3, HBr, or NF3. The etching mechanism is as follows:

[0036] A fluorinated etchant reacts with surface oxides (e.g., those formed on the sidewalls of dummy gate electrodes 80A-80B when etched) to produce silicon- and oxygen-containing gases, which can be removed from the etching chamber by a purification mechanism. For example, using CF4 as the etchant, the surface oxides react with CF4 according to the following chemical formula: SiO2 + CF4 => SiF4 + CO2, where SiF4 + CO2 is a gas that can be removed from the etching chamber.

[0037] • A chlorine-containing etchant reacts with the polycrystalline silicon material of the dummy gate electrodes 80A-80B to form another gas (e.g., SiCl) that can be removed from the etching chamber through a purification mechanism. x (where x is a positive integer).

[0038] The flow rate of the fluorinated etchant can be related to the lateral etching characteristics of the etching process 100. For example, increasing the flow rate of the fluorinated etchant enhances the lateral etching rate of the etching process 100. Therefore, to achieve the desired top-wide and bottom-narrow profile of the dummy gate electrodes 80A-80B, the etching process 100 can be configured such that the fluorine content increases as deeper portions of the polysilicon layer 80 are etched (e.g., by increasing the flow rate of the fluorinated etchant). For example, in the first etching step that etches the top of the dummy gate electrodes 80A / 80B, the flow rate of the fluorinated etchant can be configured to X sccm. In the second etching step that etches the middle portion of the dummy gate electrodes 80A / 80B, the flow rate of the fluorinated etchant can be configured to Y sccm. In the third etching step that etches the bottom of the dummy gate electrodes 80A / 80B, the flow rate of the fluorinated etchant can be configured to Z sccm. Z is greater than Y, and Y is greater than X, and X is not less than 80 sccm. Of course, the three etching steps are merely an example, and the etching process 100 can be configured to have two or four or more etching steps in other embodiments, as long as the fluorine content in the etchant increases with each etching step.

[0039] Because the etchant used herein is rich in fluorine, fluorine particles 150 may remain on the surface of the substrate 40, the STI component 45, or even on the sides of the gate structures 120A-120B after etching process 100 is completed. Due to the high fluorine content in etching process 100, these fluorine particles may still remain after various cleaning processes are performed. In other words, the removal of fluorine particles 150 may be incomplete, and some traces of them may be found in the actually manufactured semiconductor device. The presence of fluorine particles 150 can be detected by specific semiconductor manufacturing inspection tools. Fluorine residue can be evidence of an etching process similar to etching process 100 for manufacturing semiconductor devices according to the present invention.

[0040] In some embodiments, the passivation gas may also be applied together with the etchant to promote the formation of dummy gate electrodes 80A-80B with a profile that is wide at the top and narrow at the bottom. As the etching process 100 occurs, the passivation gas forms a passivation material on the exposed surface of the polysilicon layer 80. The passivation material helps prevent further etching of the polysilicon material. A simplified embodiment of this is shown below. Figure 2A As shown. Reference Figure 2AAs the top of the polysilicon layer 80 is etched, passivation gas forms passivation material 170A-170B on the sidewalls of the dummy gate electrodes 80A-80B near the top. This allows the etching process 100 to proceed downwards and continue laterally etching the lower part of the polysilicon layer 80 without further laterally etching the dummy gate electrodes 80A-80B at the top, as they are protected by the passivation material 170A-170B.

[0041] It should also be noted that, since the dummy gate electrodes 80A-80B have a profile that is wide at the top and narrow at the bottom, the opening 130 separating the dummy gate electrodes 80A-80B has a profile that is narrow at the top and wide at the bottom.

[0042] Now for reference Figure 3 Gate spacers 190A-190B are formed on the sidewalls of gate structures 120A-120B. Gate spacers 190A-190A comprise a dielectric material. In some embodiments, gate spacers 190A-190B comprise silicon nitride. In alternative embodiments, gate spacers 190A-190B may comprise silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof.

[0043] Subsequently, heavily doped source and drain regions 200A and 200B (also referred to as S / D regions) are formed in the NMOS and PMOS portions of substrate 40, respectively. The S / D regions 200A-200B can be formed by ion implantation or by diffusion. The NMOS S / D region 200B can be formed using N-type dopants such as phosphorus or arsenic, and the PMOS S / D region 200A can be formed using P-type dopants such as boron. Figure 3 As shown, S / D regions 200A-200B are aligned with the outer boundaries of gate spacers 190A-190B, respectively. Since no photolithography process is required to define the regions or boundaries of S / D regions 200A-200B, it can be said that S / D regions 200A-200B are formed in a “self-aligned” manner. One or more annealing processes are performed on semiconductor device 35 to activate S / D regions 200A-200B. It should also be understood that in some embodiments, lightly doped source / drain (LDD) regions may be formed in the NMOS and PMOS regions of substrate 40 prior to the formation of gate spacers 190A-190B. For simplicity, LDD regions are not specifically shown herein.

[0044] Now for reference Figure 4An interlayer (or inter-layer dielectric) layer 220 is formed over the substrate 40 and the gate structure 220. The ILD layer 220 can be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. For example, the ILD layer 220 fills the opening 130. In one embodiment, the ILD layer 220 comprises silicon oxide. In other embodiments, the ILD layer 220 may comprise silicon oxynitride, silicon nitride, or a low-k material. A polishing process (e.g., chemical mechanical polishing (CMP)) can be performed on the ILD layer 220 to planarize it. Polishing is performed until the top surface of the dummy gate electrode 80A of the gate structures 120A-120B is exposed. The hard mask 90A-90B is also removed by the polishing process.

[0045] Still referencing Figure 4 After the formation of the ILD layer 200 and subsequent planarization, an etching process 260 is performed to remove the dummy gate electrodes 80A-80B. In some embodiments, the etching process 260 may include a dry etching process. In the illustrated embodiment, the gate dielectric layers 60A-60B and the capping layers 70A-70B are not removed by the etching process 260. As a result of the etching process 260, trenches or openings 270A-270B are formed. Since the dummy gate electrodes 80A-80B are formed with a profile that is wider at the top and narrower at the bottom (e.g., dimension 140 >= dimension 141), the trenches 270A-270B also inherit this profile, meaning that the trenches may also have a wider lateral dimension 140 at the top and a narrower dimension 141 at the bottom. This particular configuration of the shape / profile of the trenches 270A-270B makes them easier to fill, even though the trenches 270A-270 have a small CD and a high aspect ratio.

[0046] Now for reference Figure 5 Multiple metal deposition processes 280 are performed to deposit metal layers 290 and 291. Metal layer 290 is formed above the exposed surfaces of ILD layer 220, spacers 190A-190B, and capping layers 70A-70B, and partially fills trenches 270A-270B. Metal layer 291 is formed above metal layer 290. In some embodiments, metal layer 290 includes a work function metal that helps adjust the work function of the MOS transistor, thereby enabling the achievement of a desired threshold voltage for the MOS transistor. In some embodiments, the work function metal may include a P-type work function metal; for example, the P-type work function metal may include tungsten (W), tungsten nitride (WN), or aluminum tungsten (WAl). In some embodiments, the work function metal may include an N-type work function metal; for example, the N-type work function metal may comprise titanium nitride (TiN).

[0047] In some embodiments, metal layer 291 includes a filler metal that serves as the primary conductive portion of the gate electrode. In some embodiments, the filler metal layer includes tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), or combinations thereof. In other embodiments, a barrier layer may be formed between the filler metal layer and the work function metal to reduce diffusion between the work function metal and the filler metal. The barrier layer may include TiN or TaN. Furthermore, a wetting layer (e.g., containing Ti) may optionally be formed between the barrier layer and the filler metal layer to enhance the formation of the filler metal layer.

[0048] Now for reference Figure 6 A planarization process 300 is performed to polish metal layers 291 and 290 until the upper surfaces of metal layers 291 and 290 are substantially coplanar with the upper surface of ILD layer 220. In some embodiments, planarization process 300 includes a CMP process. After planarization process 300, the remaining portions 290A and 291A of the metal layer filling trench 270A together constitute the metal gate electrode for PMOS, and the remaining portions 290B and 291B of the metal layer filling trench 270B together constitute the metal gate electrode for NMOS.

[0049] For the reasons described above, the contours of trenches 270A-270B allow metal layers 290-291 to easily fill trenches 270A-270B without gaps or voids. In contrast, in conventional gate replacement processes, overhangs present near the top of the opening (i.e., the opening formed by removing the dummy gate electrode) can hinder the formation of the metal gate. Overhangs are formed as a result of conventional manufacturing because the etched dummy gate electrode has a tapered shape that is narrower at the top than at the bottom. Therefore, the resulting trench is narrower at the top and wider at the bottom, resulting in overhangs. Overhangs can cause difficulties in filling the trench with metal layers, leading to voids / gaps within the metal electrode. This problem is overcome by the present invention, as referenced above. Figure 2 The etching process 100 discussed is specifically configured (e.g., by increasing the lateral etch rate as the etching deepens) to form dummy gate electrodes 80A-80B that are wider at the top and narrower at the bottom, thereby allowing easy filling of trenches 270A-270B without a large number of voids or gaps in the formed metal electrodes. This improves semiconductor performance.

[0050] It should be understood that, despite Figures 2-6 The diagram shows an approximate inverted trapezoidal profile (i.e., loosely resembling an inverted trapezoid) of the dummy gate electrodes 80A-80B used for etching (and therefore having the same profile as the metal gate electrodes used to replace the dummy gate electrodes). This specific profile / shape is not required but can be varied in different embodiments. For example, Figure 7Several other suitable cross-sectional profiles / shapes 400-405 for the dummy gate electrodes 80A-80B (and therefore metal gate electrodes) are shown. Profile 400 is shaped like a rectangle, wherein its lateral dimensions at the top and at the bottom are similar to each other. Profile 401 is shaped to have side surfaces, each side surface including concave and convex segments. Profile 402 is shaped to have more curved or rounded sidewall surfaces. Profile 403 is shaped like two combined rectangles, wherein the upper rectangle is wider than the lower rectangle. Profile 404 is shaped like three combined rectangles, wherein the upper rectangle is wider than the middle rectangle, which in turn is wider than the lower rectangle. Profile 405 is shaped like two combined inverted trapezoids, wherein the upper trapezoid is wider than the lower trapezoid.

[0051] For all profiles 400-405, they share a common factor: the lateral dimension at the top is greater than or equal to the lateral dimension at the bottom. Furthermore, this configuration allows for easy filling to form a void-free metal gate electrode. This can be achieved by adjusting the process formulation or process parameters of the etching process 100 described above. Figure 7 These contours or shapes are shown as 400-405. In fact, other suitable contours / shapes (not shown here) can be obtained according to various aspects of the invention for use with dummy gate electrodes (and therefore metal gate electrodes).

[0052] The gate replacement process discussed above relates to a "post-gate" process, in which a high-k gate dielectric is formed and a dummy gate electrode is formed, which is then replaced by a metal gate electrode. However, it should be understood that various aspects of the present invention can also be applied to a "post-high-k" gate replacement process. In a "post-high-k" gate replacement process, a dummy gate dielectric (e.g., silicon oxide) is formed first, instead of a high-k gate dielectric, and a dummy gate electrode (e.g., polysilicon) is formed on the dummy gate dielectric. After the source / drain regions are formed, the dummy gate dielectric is replaced with a high-k gate dielectric, and the dummy gate electrode is replaced with a metal gate electrode. In any case, the above etching process is still suitable for forming the dummy gate electrode and dummy gate dielectric with a profile wider at the top than at the bottom to facilitate filling the opening using the high-k dielectric and the metal gate electrode. Furthermore, it should be understood that various aspects of the present invention can be applied to "2D" planar devices or "3D" FinFET devices.

[0053] It should also be understood that additional processes may be implemented to complete the fabrication of semiconductor device 35. For example, these additional processes may include forming contact holes for gate structures, forming interconnect structures (e.g., lines and vias providing electrical interconnects to a device including a formed metal gate, metal layers and interlayer dielectrics), depositing passivation layers, packaging, testing, etc. For simplicity, these additional processes are not described herein. It should also be understood that some of the fabrication processes used in the various embodiments described above may be combined, depending on design needs and manufacturing requirements.

[0054] Figure 8 This is a flowchart of a method 600 for manufacturing a semiconductor device according to various aspects of the present invention. Method 600 includes step 610 of forming a high-k gate dielectric layer over a substrate.

[0055] Method 600 includes step 620 of forming a polysilicon layer over a high-k gate dielectric layer.

[0056] Method 600 includes step 630 of etching a polysilicon layer to form a dummy gate electrode having a top portion having a first lateral dimension and a bottom portion having a second lateral dimension. The second lateral dimension is greater than or equal to the first lateral dimension.

[0057] Method 600 includes step 640 of replacing the dummy gate electrode with a metal gate electrode.

[0058] In some embodiments, the top of the dummy gate electrode is formed when etching is performed at a first lateral etch rate, and the bottom of the dummy gate electrode is formed when etching is performed at a second lateral etch rate greater than the first lateral etch rate.

[0059] In some embodiments, etching includes using a fluorinated etchant, and wherein etching is performed by increasing the fluorine content of the etchant as the etching penetrates deeper into the polysilicon layer. In some embodiments, increasing the fluorine content includes increasing the flow rate of the fluorinated etchant. In some embodiments, the flow rate is not less than 80 standard cubic centimeters per minute (sccm) throughout the etching process. In some embodiments, the flow rate is in the range of about 80 sccm and about 120 sccm. In some embodiments, etching includes applying a chlorinated etchant simultaneously with the fluorinated etchant.

[0060] In some embodiments, etching includes applying a passivation gas while etching the top of the dummy gate electrode.

[0061] In some embodiments, etching is performed such that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.

[0062] In some embodiments, the first lateral dimension is at least 20% larger than the second lateral dimension.

[0063] It should be understood that additional process steps may be performed before, during, or after steps 610-640 discussed above to complete the fabrication of the semiconductor device. For example, before replacing the dummy gate electrode, method 600 may include the steps of forming spacers on the sidewalls of the dummy gate electrode, forming source / drain regions on the opposite side of the dummy gate electrode and in the substrate, and forming an interlayer dielectric (ILD) over the substrate. For simplicity, other process steps are not discussed herein.

[0064] Based on the discussion above, it can be seen that the present invention provides advantages over conventional systems and methods for forming rail structures. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. One advantage is the reduction or elimination of the dangling problem that plagues existing gate replacement processes. By carefully configuring the etching process, the resulting dummy gate electrode is formed with a profile that is wider at the top and narrower at the bottom. Once the dummy gate electrode is removed, the trench formed at the removed dummy gate electrode also inherits this profile. This profile makes the trench easy to fill with a metal material used to form the metal gate electrode. Therefore, the formed metal gate electrode is essentially void-free or gap-free, thus exhibiting better performance than conventionally formed metal gates.

[0065] One aspect of the present invention includes a method of manufacturing a semiconductor device. A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion having a first lateral dimension and a bottom portion having a second lateral dimension. The first lateral dimension is greater than or equal to the second lateral dimension. The gate electrode is replaced with a metal gate electrode.

[0066] Another aspect of the present invention relates to a method of manufacturing a semiconductor device. A gate dielectric layer is formed over a substrate. A dummy gate electrode layer is formed over the gate dielectric layer. The dummy gate electrode layer is etched with an etchant containing fluorine and chlorine to form a dummy gate electrode. The etching involves increasing the fluorine content of the etchant as the etching penetrates deeper into the dummy gate electrode layer. Spacers are formed on the sidewalls of the dummy gate electrode. Source / drain regions may be formed on opposite sides of the dummy gate electrode and in the substrate. The gate electrode is replaced with a metal gate electrode.

[0067] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a high-k gate dielectric layer disposed above a substrate. The semiconductor device includes a metal gate electrode disposed above the high-k gate dielectric layer. The metal gate electrode has a top portion and a bottom portion. The bottom portion is closer to the high-k gate dielectric layer than the top portion. The top portion has a first lateral dimension. The bottom portion has a second lateral dimension. The first lateral dimension is not less than the second lateral dimension.

[0068] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a polysilicon layer over a substrate; etching the polysilicon layer to form a dummy gate electrode, the dummy gate electrode including a top portion having a first lateral dimension and a bottom portion having a second lateral dimension, the first lateral dimension being greater than or equal to the second lateral dimension; and replacing the dummy gate electrode with a metal gate electrode.

[0069] The above method further includes: forming a high-k gate dielectric layer over the substrate before forming the polysilicon layer, wherein the polysilicon layer is formed over the high-k gate dielectric layer.

[0070] In the above method, before replacing the dummy gate electrode, the method further includes: forming a spacer on the sidewall of the dummy gate electrode; forming source / drain regions on opposite sides of the dummy gate electrode and in the substrate; and forming an interlayer dielectric (ILD) above the substrate.

[0071] In the above method, when the etching is performed at a first lateral etching rate, the top portion of the dummy gate electrode is formed; and when the etching is performed at a second lateral etching rate, the bottom portion of the dummy gate electrode is formed, wherein the second lateral etching rate is greater than the first lateral etching rate.

[0072] In the above method, the etching includes the use of a fluorinated etchant, and the etching is carried out by increasing the fluorine content of the etchant as the etching penetrates deeper into the polysilicon layer.

[0073] In the above method, increasing the fluorine content includes increasing the flow rate of the fluorine-containing etchant.

[0074] In the above method, the flow rate is in the range of 80 sccm and 120 sccm.

[0075] In the above method, the etching includes applying a chlorine-containing etchant simultaneously with the fluorine-containing etchant.

[0076] In the above method, the etching includes applying a passivation gas while etching the top portion of the dummy gate electrode.

[0077] In the above method, the etching is performed so that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.

[0078] In the above method, the first lateral dimension is at least 20% larger than the second lateral dimension.

[0079] According to other embodiments of the present invention, a method for manufacturing a semiconductor device is also provided, the method comprising: forming a gate dielectric layer over a substrate; forming a dummy gate electrode layer over the gate dielectric layer; etching the dummy gate electrode layer with an etchant comprising fluorine and chlorine to form a dummy gate electrode, wherein the etching comprises increasing the fluorine content of the etchant as the etching penetrates deeper into the dummy gate electrode layer; forming spacers on the sidewalls of the dummy gate electrode; forming source / drain regions on opposite sides of the dummy gate electrode and in the substrate; and replacing the dummy gate electrode with a metal gate electrode.

[0080] In the above method, the fluorine content is increased such that the top portion of the dummy gate electrode is wider than the bottom portion of the dummy gate electrode.

[0081] In the above method, the etching is performed such that the dummy gate electrode has a cross-sectional profile similar to an inverted trapezoid.

[0082] In the above method, the etchant includes a fluorinated etchant and a chlorinated etchant; and increasing the fluorine content includes increasing the flow rate of the fluorinated etchant.

[0083] In the above method, the etching further includes applying a passivation gas when forming the top portion of the dummy gate electrode.

[0084] According to further embodiments of the present invention, a semiconductor device is also provided, comprising: a high-k gate dielectric layer disposed above a substrate; and a metal gate electrode disposed above the high-k gate dielectric layer; wherein: the metal gate electrode has a top portion and a bottom portion, the bottom portion being closer to the high-k gate dielectric layer than the top portion; the top portion having a first lateral dimension; the bottom portion having a second lateral dimension; and the first lateral dimension being not less than the second lateral dimension.

[0085] The semiconductor device described above also includes fluorine particles disposed on the upper surface of the substrate.

[0086] In the aforementioned semiconductor device, the metal electrode has a cross-sectional profile similar to an inverted trapezoid.

[0087] In the aforementioned semiconductor device, the first lateral dimension is at least 20% larger than the second lateral dimension.

[0088] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A dummy gate electrode layer is formed on the gate dielectric layer; A patterned mask layer is formed above the dummy gate electrode layer; Using the patterned mask layer as a mask, the pseudo gate electrode layer is patterned into a plurality of patterned pseudo gate electrodes, the patterned pseudo gate electrodes being spaced apart from each other, such that each patterned pseudo gate electrode has a top-wide and bottom-narrow profile in a cross-sectional view, wherein the patterning includes etching the pseudo gate electrode layer with increasingly stronger lateral etching characteristics. Gate spacers are formed on the sidewalls of the patterned dummy gate electrode; and The patterned dummy gate electrode is replaced with a metal-containing gate electrode. Patterning the dummy gate electrode layer involves etching the dummy gate electrode layer in an etching chamber while applying an electronegative etchant, the electronegative etchant including a fluorine-containing gas or plasma. The etching of the dummy gate electrode layer with increasingly stronger lateral etching characteristics includes increasing the fluorine content of the fluorine-containing gas or plasma as it reaches deeper portions of the dummy gate electrode layer.

2. The method of claim 1, wherein, Etching the dummy gate electrode layer includes performing multiple etching steps, wherein each subsequent etching step etches the dummy gate electrode layer at a faster lateral etching rate than the previous etching step.

3. The method according to claim 1, wherein, The gate spacer includes silicon oxide, silicon carbide, silicon oxynitride, or a combination thereof.

4. The method according to claim 1, wherein, The fluorine-containing gas or plasma includes CF4, C2F6, CHF3, HBr, or NF3.

5. The method according to claim 1, wherein, The fluorinated gas or plasma is applied at a flow rate ranging from 80 standard cubic centimeters per minute to 120 standard cubic centimeters per minute.

6. The method according to claim 1, wherein, Increasing the fluorine content of the fluorine-containing gas or plasma as it reaches deeper portions of the dummy gate electrode layer includes increasing the flow rate of the fluorine-containing gas or plasma.

7. The method according to claim 1, wherein, Etching the dummy gate electrode layer includes etching the dummy gate electrode layer in an etching chamber while applying a chlorine-containing etchant.

8. The method according to claim 7, wherein, The chlorine-containing etchant is applied at a flow rate ranging from 30 standard cubic centimeters per minute to 36 standard cubic centimeters per minute.

9. The method according to claim 1, wherein, The patterning also includes applying a passivating gas during the patterning process.

10. The method according to claim 9, wherein, The step of applying the passivation gas is performed such that a passivation layer is formed on the upper part, but not all, of the side of each patterned dummy gate electrode during the etching process.

11. The method according to claim 1, wherein, Forming the dummy gate electrode layer includes forming a polysilicon gate electrode layer over a high-k gate dielectric layer, and the method further includes: A capping layer is formed over the gate dielectric layer, wherein the dummy gate electrode layer is formed over the capping layer, and the capping layer comprises lanthanum oxide; and An interlayer dielectric is formed after the gate spacers are formed, wherein a portion of the interlayer dielectric is formed between the gate spacers.

12. The method according to claim 11, wherein, The pseudo-gate electrode layer is patterned, as are the capping layer and the gate dielectric layer.

13. A method for manufacturing a semiconductor device, comprising: A gate dielectric layer is formed above the substrate; A dummy gate electrode layer is formed above the gate dielectric layer; The dummy gate electrode layer is patterned into multiple patterned dummy gate electrodes through a multi-etching process, wherein the lateral etching characteristics of the multi-etching process become stronger and stronger, so that each patterned dummy gate electrode has a tapered cross-sectional profile, and the upper part of the patterned dummy gate electrode is wider than the lower part of the patterned dummy gate electrode. A gate spacer is formed on the sidewall of the patterned dummy gate electrode; Remove the patterned dummy gate electrode to form a plurality of openings at least partially defined by the gate spacer; and The plurality of openings are filled with a metal-containing gate electrode layer. The process involves multiple etching steps performed within an etching chamber, simultaneously applying an electronegative etchant and a chlorine-containing etchant. The electronegative etchant may include a fluorine-containing gas or plasma. As the dummy gate electrode layer is etched deeper, multiple etching processes are performed, at least in part, by increasing the fluorine content of the fluorine-containing gas or plasma.

14. The method according to claim 13, wherein, The fluorine-containing gas or plasma includes CF4, C2F6, CHF3, HBr, or NF.

15. The method according to claim 13, wherein, Performing multiple etching processes, at least in part, by increasing the fluorine content of the fluorine-containing gas or plasma, includes performing multiple etching processes, at least in part, by increasing the flow rate of the fluorine-containing gas or plasma.

16. The method according to claim 15, wherein, The fluorinated gas or plasma is applied at a flow rate ranging from 80 standard cubic centimeters per minute to 120 standard cubic centimeters per minute; and The chlorine-containing etchant is applied at a flow rate ranging from 30 standard cubic centimeters per minute to 36 standard cubic centimeters per minute.

17. The method according to claim 13, wherein, The patterning also includes partially forming a passivation layer on the side of the dummy gate electrode layer during the etching process.

18. A method for manufacturing a semiconductor device, comprising: An unpatterned pseudo-gate structure is formed above the substrate; A first etching process is performed on the unpatterned pseudo-gate structure, wherein the first etching process has a first lateral etching characteristic. After the first etching process, a second etching process is performed on the unpatterned pseudo-gate structure, wherein the second etching process has a second lateral etching characteristic that is greater than the first lateral etching characteristic. After the second etching process, a third etching process is performed on the unpatterned pseudo-gate structure, wherein the third etching process has a third lateral etching characteristic that is greater than the second lateral etching characteristic, and after the third etching process is completed, the unpatterned pseudo-gate structure is etched into a plurality of patterned pseudo-gate structures, the patterned pseudo-gate structures being separated from each other. A gate spacer is formed on the sidewall of the patterned pseudo-gate structure; and The patterned pseudo-gate structure is replaced with a metal-containing gate structure. The first etching process, the second etching process, and the third etching process are all performed using at least a fluorine-containing gas or plasma as the etchant. As the fluorine content of the fluorine-containing gas or plasma increases as it reaches deeper portions of the unpatterned dummy gate structure, the third etching process, the second etching process, and the first etching process etch the unpatterned dummy gate structure with increasingly stronger lateral etching characteristics.

19. The method according to claim 18, wherein, The first etching process is performed at a first fluorinated etchant flow rate; The second etching process is performed at a second fluorinated etchant flow rate that is faster than the first fluorinated etchant flow rate; and The third etching process is performed at a third fluorinated etchant flow rate that is faster than that of the second fluorinated etchant.

20. The method according to claim 18, wherein, The fluorine-containing gas or plasma includes CF4, C2F6, CHF3, HBr, or NF.

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