Half-bridge topology integration method and chip for co-packaged gallium nitride power devices

Abstract

Embodiments of the present invention relate to a half-bridge topology integration method and chip for co-packaged gallium nitride power devices, including: a drive control module, a first gallium nitride power transistor, and a second gallium nitride power transistor; the drive control module includes a logic control circuit and a half-bridge drive circuit; the half-bridge drive circuit includes a high-voltage startup circuit, a high-side driver, and a low-side driver; the logic control circuit is connected to the half-bridge drive circuit, the first gallium nitride power transistor and the second gallium nitride power transistor are connected in series, the drive outputs of the half-bridge drive circuit are respectively connected to the drive ends of the first gallium nitride power transistor and the second gallium nitride power transistor, and the half-bridge drive circuit drives the first gallium nitride power transistor and the second gallium nitride power transistor to alternately turn on and off according to the control signal output by the logic control circuit; the logic control circuit, the half-bridge drive circuit, the first gallium nitride power transistor, and the second gallium nitride power transistor are packaged in a single chip to form the co-packaged gallium nitride half-bridge topology integrated chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a half-bridge topology integration method and chip for co-packaged gallium nitride power devices. Background Art

[0002] Half-bridge drive circuits are widely used in electronic ballasts, pulse width modulation (PWM) motor drives, and inverter circuits. There are discrete component drives, pulse trigger transformer drives, and dedicated integrated chip drives for half-bridge drive circuits. Among them, the discrete component drive has the advantage of low price, but its application is limited due to its poor integration; the trigger transformer drive has the advantage of convenient implementation, but due to its manufacturing errors, it is easy to cause distortion of the two drive signals, and the transformer has a large volume and generates a lot of heat; the dedicated integrated chip has the advantages of small volume, high reliability, and high efficiency.

[0003] The half-bridge topology of power switching devices is a commonly used structure in medium and high power switching power supplies. It can reduce the voltage stress of the power switching devices on the primary side of the transformer. In order to reduce the switching loss, soft-switching zero-voltage switching (ZVS) technology is often used in half-bridge topologies such as active clamping and LLC resonance, which can increase the switching frequency and reduce the product volume.

[0004] The third-generation semiconductor material gallium nitride (GaN) has the characteristics of high switching frequency, large bandgap, and low on-resistance. Moreover, the high-frequency characteristics of GaN can naturally match the soft-switching ZVS control technology of the half-bridge topology, which can significantly increase the switching frequency without increasing the switching loss, further improving the power density, and well conforming to the development trend of small size, light weight, and high efficiency of switching power supplies.

[0005] The threshold voltage Vth and the gate-source breakdown voltage of high-voltage enhancement-mode GaN power devices are lower than those of silicon-based (Si) power devices, and higher precision of the gate-source drive voltage is required. In the prior art, the driver and the GaN power device are discrete, and are connected by printed circuit board (PCB) wiring externally. As Figure 1 shown, K1 and K2 are respectively discrete low- and high-end GaN power devices, the driver is also an independent chip, L1 to L10 are the wire bonding parasitic inductances during packaging, L11 to L14 are the PCB wiring parasitic inductances, and the parasitic inductance of the drive loop of the high-end power device K2 is composed of the series connection of L1, L11, L5, L6, L12, and L2. The inductance of the drive loop of the low-end power device is composed of the series connection of L3, L13, L8, L10, L14, and L4. As Figure 1 can be seen, the parasitic inductances of the high- and low-end drive loops are relatively large, and the gate-source voltage difference, that is, the drive voltage VGS, of K1 and K2 will generate a ringing phenomenon, as Figure 2As shown, both the overshoot and undershoot of VGS are very obvious. Since the breakdown voltage between the gate and source of GaN is relatively low, if the ringing peak voltage VGSmax of the drive exceeds the breakdown voltage between the gate and source of GaN, the device will be damaged. Summary of the Invention

[0006] The object of the present invention is to provide a half-bridge topology integration method and chip for co-packaged gallium nitride power devices, which integrate a high-voltage start-up circuit, a logic control circuit, a drive circuit dedicated to GaN power devices, and GaN power devices of a half-bridge topology in one chip, and perform reasonable layout, reducing the parasitic parameters in the drive loop, while ensuring the heat dissipation of the power device, significantly reducing the number of external devices of the power supply chip, improving the power density, being easy to debug, and saving the application cost.

[0007] To this end, in a first aspect, an embodiment of the present invention provides a half-bridge topology integration method for co-packaged gallium nitride power devices, and the method includes:

[0008] Encapsulate a drive control module, a first gallium nitride power transistor, and a second gallium nitride power transistor in one chip to form the co-packaged gallium nitride half-bridge topology integration chip; wherein, the drive control module includes a logic control circuit and a half-bridge drive circuit; the half-bridge drive circuit includes a high-voltage start-up circuit, a high-side driver, and a low-side driver;

[0009] Isolate a first base island area and a second base island area in the chip with an insulating layer; arrange the drive control module and the second gallium nitride power transistor in the first base island area, and arrange the first gallium nitride power transistor in the second base island area;

[0010] Connect the logic control circuit to the half-bridge drive circuit, connect the first gallium nitride power transistor and the second gallium nitride power transistor in series, and connect the drive outputs of the half-bridge drive circuit to the drive ends of the first gallium nitride power transistor and the second gallium nitride power transistor respectively, so that the half-bridge drive circuit drives the first gallium nitride power transistor and the second gallium nitride power transistor to alternately turn on and off according to the control signal output by the logic control circuit.

[0011] Preferably, the encapsulation specifically adopts a quad flat no-lead (QFN) package structure, and the method further includes: arranging the pins connecting high-voltage signals in the chip on one side of the QFN package, and arranging the pins connecting low-voltage signals on the other side of the QFN package;

[0012] Among them, the pins connecting high-voltage signals include a high-voltage input positive terminal V+, a high-side driver power input terminal VCCH, a high-voltage start-up circuit input terminal HV, and a half-bridge output pin HB; the pins connecting low-voltage signals include a chip power input terminal VCC and a plurality of input / output I / O terminals;

[0013] The pins of the chip further include: a high-voltage input negative terminal V-; the high-voltage input negative terminal V- is arranged on the other side or the third side of the PDNF package.

[0014] Further preferably, the power input terminal VCC of the chip is respectively connected to the logic control circuit, the high-voltage startup circuit, the high-side driver, and the low-side driver;

[0015] The input terminal HV of the high-voltage startup circuit is connected to the high-voltage startup circuit, and the output terminal of the high-voltage startup circuit is respectively connected to the logic control circuit, the high-side driver, and the low-side driver;

[0016] The logic control circuit is connected to the multiple input / output I / O terminals;

[0017] The first control signal output terminal of the logic control circuit is connected to the drive signal input terminal of the high-side driver; the signal output terminal of the high-side driver is connected to the gate of the first gallium nitride power transistor;

[0018] The second control signal output terminal of the logic control circuit is connected to the drive signal input terminal of the low-side driver; the signal output terminal of the low-side driver is connected to the gate of the second gallium nitride power transistor;

[0019] The high-voltage input positive terminal V+ is connected to the drain of the first gallium nitride power transistor, and the source of the second gallium nitride power transistor is connected to the high-voltage input negative terminal V-; the source of the first gallium nitride power transistor is connected to the drain of the second gallium nitride power transistor and connected to the half-bridge output pin HB.

[0020] Further preferably, the logic control circuit outputs a first control signal PWMH and a second control signal PWML according to the input signals of the multiple input / output I / O terminals;

[0021] The high-side driver outputs a first gate drive signal of the first gallium nitride power transistor according to the first control signal PWMH; the low-side driver outputs a second gate drive signal of the second gallium nitride power transistor according to the second control signal PWML; under the drive of the first gate drive signal and the second gate drive signal, the first gallium nitride power transistor and the second gallium nitride power transistor are alternately turned on and off;

[0022] Wherein, the first control signal and the second control signal are complementary pulse width modulation signals.

[0023] Preferably, the method further includes:

[0024] Connect the ground terminals of the logic control circuit, high-voltage startup circuit, high-side driver, and low-side driver to the negative terminal V- of the high-voltage input respectively; connect the feedback terminal of the high-side driver to the half-bridge output pin HB.

[0025] Preferably, isolate the pins of the chip with the insulating layer.

[0026] Preferably, expose the copper on the back of the chip corresponding to the first base island region and the second base island region.

[0027] Preferably, the package is specifically a DNF8*8 package.

[0028] In a second aspect, an embodiment of the present invention further provides a half-bridge topology integrated chip obtained by the half-bridge topology integration method of the co-packaged gallium nitride power device described in the first aspect above.

[0029] The half-bridge topology integration method of the co-packaged gallium nitride power device provided by the embodiment of the present invention, in view of the characteristics of the GaN power device, integrates the high-voltage startup circuit, logic control circuit, drive circuit dedicated to the GaN power device, and GaN power device of the half-bridge topology in one chip, realizes isolation by separating the base island regions with an insulating layer, and arranges the pins of the low-voltage signal on one side and the pins of the high-voltage signal on the other side by using the package architecture, ensuring physical space isolation of the high- and low-voltage signals; by exposing the copper on the back of the base island region, the chip can be directly soldered on the PCB board during application, ensuring the heat dissipation performance of the chip. Compared with the prior art, the half-bridge topology integrated chip of the present invention not only reduces the parasitic parameters in the drive loop, but also significantly reduces the number of peripheral devices of the power supply chip while ensuring the heat dissipation of the power device, improves the power density, is easy to debug, and saves the application cost. Description of the Drawings

[0030] Figure 1 Schematic diagram of the parasitic inductance distribution of discrete GaN power devices and driver chips provided by the prior art;

[0031] Figure 2 Schematic diagram of the gate-source drive voltage VGS waveform of the GaN power device;

[0032] Figure 3 Schematic diagram of the half-bridge topology integrated chip of the co-packaged gallium nitride power device provided by the present invention;

[0033] Figure 4 Physical diagram of a chip prepared by the half-bridge topology integration method proposed by the embodiment of the present invention

[0034] Figure 5 Schematic diagram of a specific way of the pin setting of the chip provided by the present invention;

[0035] Figure 6 A schematic diagram of the half-bridge drive signal provided by the present invention;

[0036] Figure 7 A schematic diagram of the parasitic inductance distribution in the half-bridge topology integrated chip of the co-packaged gallium nitride power device provided by the present invention;

[0037] Figure 8 For the present invention and Figure 2 A comparison diagram of the gate-source drive voltage VGS waveforms;

[0038] Figure 9 A half-bridge drive chip structure applied to the LLC series resonant architecture specifically implemented by using the half-bridge topology integration method of the present invention;

[0039] Figure 10 A half-bridge drive chip structure applied to the active clamped flyback architecture specifically implemented by using the half-bridge topology integration method of the present invention. Specific implementation manners

[0040] The technical solutions of the present invention will be further described in detail below with reference to the drawings and embodiments.

[0041] The embodiments of the present invention provide a half-bridge topology integration method for co-packaged gallium nitride power devices, including:

[0042] Encapsulating the drive control module 1, the first gallium nitride power transistor K1, and the second gallium nitride power transistor K2 in a single chip to form a co-packaged gallium nitride half-bridge topology integrated chip; the specific encapsulation can adopt a quad flat no-lead (QFN) package structure.

[0043] The chip structure is as Figure 3 shown. The following will be described in conjunction with Figure 3 for illustration.

[0044] The drive control module 1 includes; a logic control circuit 11 and a half-bridge drive circuit; the half-bridge drive circuit includes: a high-voltage start-up circuit 12, a high-side driver 13, and a low-side driver 14;

[0045] The pins of the chip include: high-voltage input positive terminal V+, high-voltage input negative terminal V-, high-side driver power input terminal VCCH, high-voltage startup circuit input terminal HV, chip power input terminal VCC, multiple input / output I / O terminals, and half-bridge output pin HB. In order to achieve physical space isolation of high-voltage and low-voltage signals in the packaging architecture, the low-voltage signal ground pins are arranged on one side, and the high-voltage signal pins are arranged on the other side. In addition, in the physical implementation of the chip, an insulating layer is used to isolate the first base island region and the second base island region, and the drive control module 1 and the second gallium nitride power transistor K2 are arranged in the first base island region, and the first gallium nitride power transistor K1 is arranged in the second base island region, achieving isolation and at the same time optimizing the bonding. In addition, the pins of the chip are also isolated by an insulating layer in the physical implementation.

[0046] A physical chip prepared by the half-bridge topology integration method proposed in the embodiment of the present invention is as Figure 4 shown. It can be seen that the drive control module 1 and the second gallium nitride power transistor K2 are arranged in the first base island region A, and the first gallium nitride power transistor K1 is arranged in the second base island region B, and are isolated by the insulating layer C.

[0047] In the chip, the pins connected to the high-voltage signals include: high-voltage input positive terminal V+, high-side driver power input terminal VCCH, high-voltage startup circuit input terminal HV, and half-bridge output pin HB; the pins connected to the low-voltage signals include: chip power input terminal VCC and multiple input / output I / O terminals; in addition, the pins of the chip also include: high-voltage input negative terminal V-; the high-voltage input negative terminal V- can be arranged on the other side or the third side of the PDNF package. In a specific implementation, the arrangement of the pins is as Figure 5 shown.

[0048] Preferably, the package adopts DNF8*8 package. In the pin arrangement, the pins of the chip connected to the high-voltage signals are arranged on one side of the DNF8*8 package, and the pins connected to the low-voltage signals are arranged on the other side of the DNF8*8 package.

[0049] Inside the chip, following the above structure, the logic control circuit 11 is connected to the half-bridge drive circuit, the first gallium nitride power transistor K1 and the second gallium nitride power transistor K2 are connected in series, and the drive outputs of the half-bridge drive circuit are respectively connected to the drive ends of the first gallium nitride power transistor K1 and the second gallium nitride power transistor K2, so that the half-bridge drive circuit drives the first gallium nitride power transistor and the second gallium nitride power transistor to turn on and off alternately according to the control signal output by the logic control circuit.

[0050] Specifically, the power input terminal VCC of the chip is respectively connected to the logic control circuit 11, the high-voltage startup circuit 12, the high-side driver 13, and the low-side driver 14;

[0051] Connect the input terminal HV of the high-voltage startup circuit to the high-voltage startup circuit 12, and connect the output terminals of the high-voltage startup circuit 12 to the logic control circuit 11, the high-side driver 13, and the low-side driver 14 respectively;

[0052] Connect the logic control circuit 11 to multiple input / output I / O terminals, shown as I / O_1 to I / O_n in the figure;

[0053] Connect the first control signal output terminal of the logic control circuit 11 to the drive signal input terminal of the high-side driver 13; connect the signal output terminal of the high-side driver 13 to the gate of the first gallium nitride power transistor K1;

[0054] Connect the second control signal output terminal of the logic control circuit 11 to the drive signal input terminal of the low-side driver 14; connect the signal output terminal of the low-side driver 14 to the gate of the second gallium nitride power transistor K2;

[0055] Connect the high-voltage input positive terminal V+ to the drain of the first gallium nitride power transistor K1, and connect the source of the second gallium nitride power transistor K2 to the high-voltage input negative terminal V-; connect the source of the first gallium nitride power transistor K1 to the drain of the second gallium nitride power transistor K2 and connect to the half-bridge output pin HB.

[0056] In addition, connect the ground terminals of the logic control circuit 11, the high-voltage startup circuit 12, the high-side driver 13, and the low-side driver 14 to the high-voltage input negative terminal V- respectively; connect the feedback terminal of the high-side driver 13 to the half-bridge output pin HB, and connect the feedback terminal of the low-side driver 14 to the high-voltage input negative terminal V-.

[0057] The input / output I / O terminals of the logic control circuit can be configured according to the application architecture of the half-bridge topology, and can be configured as feedback signal input, control signal input / output, protection signal input / output, etc. in specific applications.

[0058] Therefore, in actual applications, the first control signal PWMH and the second control signal PWML can be output according to the input signals of the multiple input / output I / O terminals; in a specific application, the first control signal PWMH and the second control signal PWML can be complementary pulse width modulation signals.

[0059] The high-side driver 13 outputs the first gate drive signal GTH of the first gallium nitride power transistor K1 according to the first control signal PWMH; the low-side driver 14 outputs the second gate drive signal GTL of the second gallium nitride power transistor K2 according to the second control signal PWML.

[0060] Both the high-side driver 13 and the low-side driver 14 can contain a level shift circuit and a drive circuit. The first control signal PWMH enters the high-side driver 13 to generate the first gate drive signal GTH, and the potential difference between the first gate drive signal GTH and the half-bridge output pin HB controls the turn-on and turn-off of the first gallium nitride power transistor K1; the second control signal PWML enters the low-side driver 14 to generate the second gate drive signal GTL, and the potential difference between the second gate drive signal GTL and the negative terminal of the high-voltage input V- controls the turn-on and turn-off of the second gallium nitride power transistor K2. Under the condition that the first control signal PWMH and the second control signal PWML are complementary pulse width modulation signals, the first gate drive signal GTH and the second gate drive signal GTL drive the first gallium nitride power transistor K1 and the second gallium nitride power transistor K2 to alternately turn on and turn off. According to the alternately turn-on and turn-off driving, half-bridge drive signals VgH and VgL are generated, and there is a dead time T_dt during the alternation process. Figure 6 It is a schematic diagram of the half-bridge drive signal provided by the present invention.

[0061] The present invention also exposes the copper on the back of the chip corresponding to the first base island region and the second base island region physically. When applied, the back of the chip is soldered on the PCB board, which is beneficial to the heat dissipation of the chip, especially can improve the heat dissipation of the drive control module 1, the first gallium nitride power transistor K1 and the second gallium nitride power transistor K2.

[0062] Figure 7 It is a schematic diagram of the parasitic inductance distribution in the half-bridge topology integrated chip of the co-packaged gallium nitride power device provided by the present invention. It can be seen that compared with the discrete GaN power device and the drive chip, the parasitic inductance is greatly reduced. Compared with Figure 1 the parasitic inductance of the drive loop is reduced from 12 of the discrete GaN power device and the drive chip to 6.

[0063] Figure 8 It is a comparison diagram of the gate-source drive voltage VGS waveforms between the present invention and Figure 2 The dotted line is the gate-source drive voltage VGS of the discrete GaN power device and the drive chip, and the solid line is the gate-source drive voltage VGS of the integrated chip of the present invention. It can be seen from the figure that after reducing the parasitic inductance, the ringing of the gate-source drive voltage VGS almost disappears, effectively protecting the power device.

[0064] Figure 9 It is a half-bridge drive chip structure applied to the LLC series resonant architecture specifically implemented by the half-bridge topology integration method of the present invention; Figure 10 It is a half-bridge drive chip structure applied to the active clamp flyback architecture specifically implemented by the half-bridge topology integration method of the present invention.

[0065] According to the above two specific structures, based on the half-bridge topology integration method proposed by the present invention, the specific frame type and size to be selected can be determined according to the application environment and system parameter requirements. The pin positions, the number and definition of I / O ports can all be determined according to the actual application requirements. The above two are only examples of specific implementation manners and do not serve as a limitation on the actual application implementation of the present invention.

[0066] The half-bridge topology integration method and chip of the co-packaged gallium nitride power device provided by the embodiment of the present invention integrate the high-voltage startup circuit, logic control circuit, dedicated drive circuit for GaN power device and GaN power device of the half-bridge topology in one chip in view of the characteristics of GaN power device. The drive circuit and the power device are directly connected through internal wire bonding (Bonding), reducing the wire bonding parasitic inductance. At the same time, the PCB parasitic inductance is removed, greatly reducing the parasitic inductance of the drive loop and effectively preventing the damage of GaN power device. At the same time, the full integration technology makes the peripheral application more concise and further reduces the volume of the application product. The isolation is achieved by separating the base island area with an insulating layer, and the pins of the low-voltage signal are arranged on one side and the pins of the high-voltage signal are arranged on the other side by using a packaging architecture, ensuring the physical space isolation of high- and low-voltage signals. By copper-plating the back of the base island area, the chip can be directly soldered to the PCB board during application, ensuring the heat dissipation performance of the chip. Compared with the prior art, the half-bridge topology integrated chip of the present invention not only reduces the parasitic parameters in the drive loop, but also while ensuring the heat dissipation of the power device, greatly reduces the number of peripheral devices of the power supply chip, improves the power density, is easy to debug, and saves the application cost.

[0067] Those skilled in the art should also further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0068] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be implemented by hardware, software modules executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0069] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only for the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A half-bridge topology integration method for co-packaged gallium nitride power devices, characterized in that, The method includes: Encapsulating a drive control module, a first gallium nitride power transistor, and a second gallium nitride power transistor in a single chip to form the co-packaged gallium nitride half-bridge topology integrated chip; wherein, the drive control module includes a logic control circuit and a half-bridge drive circuit; the half-bridge drive circuit includes a high-voltage startup circuit, a high-side driver, and a low-side driver. Isolating a first base island region and a second base island region in the chip with an insulating layer; disposing the drive control module and the second gallium nitride power transistor in the first base island region, and disposing the first gallium nitride power transistor in the second base island region for physical space isolation of high-voltage signals and low-voltage signals. Connecting the logic control circuit to the half-bridge drive circuit, wherein the first control signal output terminal of the logic control circuit is connected to the drive signal input terminal of the high-side driver, and the second control signal output terminal of the logic control circuit is connected to the drive signal input terminal of the low-side driver; connecting the first gallium nitride power transistor and the second gallium nitride power transistor in series; connecting the drive outputs of the half-bridge drive circuit to the drive terminals of the first gallium nitride power transistor and the second gallium nitride power transistor respectively, wherein the signal output terminal of the high-side driver is connected to the gate of the first gallium nitride power transistor, and the signal output terminal of the low-side driver is connected to the gate of the second gallium nitride power transistor; enabling the half-bridge drive circuit to drive the first gallium nitride power transistor and the second gallium nitride power transistor to alternately turn on and off according to the control signal output by the logic control circuit. The encapsulation specifically adopts a quad flat no-lead (QFN) package structure. The method further includes: disposing the pins in the chip for connecting high-voltage signals on one side of the QFN package, and disposing the pins for connecting low-voltage signals on the other side of the QFN package; the pins of the chip further include a high-voltage input negative terminal V-; disposing the high-voltage input negative terminal V- on the other side or the third side of the QFN package.

2. The method according to claim 1, wherein The pins for connecting high-voltage signals include a high-voltage input positive terminal V+, a high-side driver power input terminal VCCH, a high-voltage startup circuit input terminal HV, and a half-bridge output pin HB; the pins for connecting low-voltage signals include a chip power input terminal VCC and multiple input / output (I / O) terminals.

3. The method according to claim 2, wherein Connecting the chip power input terminal VCC to the logic control circuit, the high-voltage startup circuit, the high-side driver, and the low-side driver respectively. Connecting the high-voltage startup circuit input terminal HV to the high-voltage startup circuit, and connecting the output terminal of the high-voltage startup circuit to the logic control circuit, the high-side driver, and the low-side driver respectively. Connecting the logic control circuit to the multiple input / output I / O terminals. Connecting the high-voltage input positive terminal V+ to the drain of the first gallium nitride power transistor, connecting the source of the second gallium nitride power transistor to the high-voltage input negative terminal V-; connecting the source of the first gallium nitride power transistor to the drain of the second gallium nitride power transistor and connecting them to the half-bridge output pin HB.

4. The method according to claim 2, characterized in that, The logic control circuit outputs a first control signal PWMH and a second control signal PWML according to the input signals of the multiple input / output I / O terminals. The high-side driver outputs a first gate drive signal of the first gallium nitride power transistor according to the first control signal PWMH; the low-side driver outputs a second gate drive signal of the second gallium nitride power transistor according to the second control signal PWML; under the drive of the first gate drive signal and the second gate drive signal, the first gallium nitride power transistor and the second gallium nitride power transistor are alternately turned on and off; Wherein, the first control signal and the second control signal are complementary pulse width modulation signals.

5. The method according to claim 1, characterized in that The method further includes: Connecting the ground terminals of the logic control circuit, the high-voltage start-up circuit, the high-side driver and the low-side driver to the negative terminal V- of the high-voltage input respectively; connecting the feedback terminal of the high-side driver to the half-bridge output pin HB.

6. The method according to claim 1, wherein Isolating the pins of the chip with the insulating layer.

7. The method according to claim 1, characterized in that Exposing the back copper of the chip corresponding to the first base island region and the second base island region.

8. The method according to claim 1, characterized in that The packaging is specifically DNF8*8 packaging.

9. A half-bridge topology integrated chip obtained by a half-bridge topology integration method of a co-packaged gallium nitride power device according to claim 1 above.

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