Vertical structure power device, manufacturing method and electronic equipment

Abstract

The application belongs to the technical field of semiconductor devices, and provides a vertical structure power device, a preparation method and electronic equipment. The vertical structure power device comprises a drain doped layer, a drift layer, a reverse type super junction, a doped semiconductor column, a surface work function metal, a dielectric layer and a source doped layer. The reverse withstand voltage of the power device is improved by the lower doped drift layer, then the reverse type super junction is arranged in the drift layer to change the electric field distribution in the drift layer, reduce the maximum electric field at the channel and the drift layer interface, and avoid the problem that the device reliability is reduced due to the avalanche effect caused by the high electric field when the reverse bias voltage is connected.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a vertical structure power device, a preparation method and an electronic device. BACKGROUND

[0002] With the progress of process level and the popularization of horizontal three-dimensional structure field effect transistors (such as Fin Field-Effect Transistor (FinFET), Gate-all-around (GAA) and Nano-sheet), a vertical three-dimensional structure power device is proposed, such as a tunnel field effect transistor.

[0003] However, the vertical multi-layer structure process still has the problem of low reverse withstand voltage. SUMMARY

[0004] The present application aims to provide a vertical structure power device, a preparation method and an electronic device, and aims to solve the problem of low reverse withstand voltage in the vertical multi-layer structure process.

[0005] The present application provides a vertical structure power device, which comprises:

[0006] a drain doped layer doped with first type doping ions;

[0007] a drift layer arranged on the drain doped layer, wherein the doping type of the drift layer is the same as the doping type of the drain doped layer, and the doping concentration of the drift layer is less than the doping concentration of the drain doped layer;

[0008] a reverse type super junction arranged in the drift layer, wherein the reverse type super junction is doped with second type doping ions;

[0009] a doped semiconductor column arranged on the drift layer and doped with second type doping ions;

[0010] a surface work function metal formed on the side surface of the doped semiconductor column;

[0011] a dielectric layer arranged on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column;

[0012] a source doped layer arranged on the dielectric layer and connected with the doped semiconductor column.

[0013] In one embodiment, the number of the doped semiconductor columns is multiple, and the number of the reverse type super junctions is one or multiple.

[0014] In one embodiment, the source doped layer has the same doping type as the drift layer, and the source doped layer has a higher doping concentration than the drift layer.

[0015] In one embodiment, the depth of the inversion super junction is greater than 1 / 2 of the thickness of the drift layer.

[0016] In one embodiment, the vertical structure power device further comprises a gate electrode, and the doped semiconductor pillar is connected to the gate electrode through a contact hole.

[0017] The second aspect of the embodiments of the present application further provides a manufacturing method of a vertical structure power device, the manufacturing method comprising:

[0018] forming a drain doped layer, the drain doped layer being doped with first type doping ions;

[0019] forming a drift layer on the drain doped layer, wherein the drift layer has the same doping type as the drain doped layer, and the drift layer has a lower doping concentration than the drain doped layer;

[0020] forming an inversion super junction in the drift layer, the inversion super junction being doped with second type doping ions;

[0021] forming a doped semiconductor pillar on the drift layer;

[0022] forming a surface work function metal on the side surface of the doped semiconductor pillar;

[0023] forming a dielectric layer on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor pillar;

[0024] forming a source doped layer on the dielectric layer, the source doped layer being connected to the doped semiconductor pillar.

[0025] In one embodiment, the forming an inversion super junction in the drift layer comprises:

[0026] determining a super junction doping region on the drift layer by using a first mask layer;

[0027] forming the inversion super junction in the drift layer by injecting second type doping ions into the super junction doping region.

[0028] In one embodiment, the forming a doped semiconductor pillar on the drift layer comprises:

[0029] determining a semiconductor pillar etching region on the drift layer by using a second mask layer, and forming the semiconductor pillar by an etching process;

[0030] injecting a second type of ions into the semiconductor pillar to form the doped semiconductor pillar.

[0031] In one embodiment, the forming the dielectric layer on the drift layer comprises:

[0032] forming a third mask in the region of the doped semiconductor pillar;

[0033] forming a dielectric layer on the drift layer by depositing a dielectric material and etching the dielectric layer under the protection of the third mask.

[0034] A third aspect of the embodiments of the present application further provides an electronic device comprising the vertical structure power device as described in any one of the above.

[0035] Compared with the prior art, the embodiments of the present application have the beneficial effects that: by comprising the drain doped layer, the drift layer, the reverse-type super junction, the doped semiconductor pillar, the surface work function metal, the dielectric layer and the source doped layer, the reverse withstand voltage of the power device is improved by the low-doped drift layer, then the electric field distribution in the drift layer is changed by setting the reverse-type super junction in the drift layer, the maximum electric field at the channel and the drift layer interface is reduced, and the problem that the device reliability is reduced due to the avalanche effect caused by the high electric field when the reverse bias voltage is connected is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0037] Figure 1 a structure schematic diagram of the vertical structure power device provided by an embodiment of the present application;

[0038] Figure 2 a flowchart of the preparation method of the vertical structure power device provided by an embodiment of the present application;

[0039] Figure 3 a schematic diagram of forming the drain doped layer provided by an embodiment of the present application;

[0040] Figure 4 a schematic diagram of forming the drift layer and the reverse-type super junction provided by an embodiment of the present application;

[0041] Figure 5 a schematic diagram of forming the doped semiconductor pillar provided by an embodiment of the present application;

[0042] Figure 6 a schematic diagram of forming the dielectric layer provided by an embodiment of the present application;

[0043] Figure 7 A schematic diagram of forming a source doped layer is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0045] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0047] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0048] Many commonly used power devices (insulated gate bipolar transistor IGBT / vertical double diffused metal oxide semiconductor field effect transistor VDMOS) devices move the device drain to the bottom of the device to improve the withstand voltage, however, other structures still consume a lot of valuable wafer area in the horizontal direction.

[0049] Figure 1 A structure schematic diagram of a vertical structure power device provided by an embodiment of the present application is shown, only the parts related to the present embodiment are shown for the purpose of illustration, and the details are as follows:

[0050] The vertical structure power device includes a drain doped layer 10, a drift layer 12, an inversion super junction 13, a doped semiconductor column 15, a surface work function metal 17, a dielectric layer 14 and a source doped layer 16.

[0051] Specifically, a drain doped layer 10 can be disposed on the substrate, the drain doped layer 10 is doped with first type of doping ions, and a drift layer 12 is disposed on the drain doped layer, wherein the doping type of the drift layer 12 is the same as the doping type of the drain doped layer 10, and the doping concentration of the drift layer 12 is less than the doping concentration of the drain doped layer 10.

[0052] In one specific application, the substrate can be a silicon-based substrate, or other compound semiconductor substrates, such as gallium nitride, silicon carbide, gallium arsenide, etc.

[0053] A reverse-type super junction 13 is disposed in the drift layer 12, and is disposed in the drift layer 12 between adjacent doped semiconductor pillars 15, wherein the reverse-type super junction 13 is doped with second type of doping ions, which is different from the first type of doping ions in the drift layer, for example, the first type of doping ions can be N-type doping ions, and the second type of doping ions are P-type doping ions.

[0054] The doped semiconductor pillars 15 are disposed on the drift layer 12 and are doped with the second type of doping ions, and a surface work function metal 17 is formed on the doped semiconductor pillars 15; a dielectric layer 14 is disposed on the drift layer 12, wherein the dielectric layer 14 fills the gaps between the doped semiconductor pillars 15, the depth of the dielectric layer 14 is less than the height of the doped semiconductor pillars 15, and a source doped layer 16 is disposed on the dielectric layer 14 and connected to the doped semiconductor pillars 15.

[0055] In the embodiment, by setting the doping concentration of the drift layer 12 to be less than the doping concentration of the drain doped layer 10, the reverse voltage of the power device is improved by the lower doped drift layer 12, and then by setting the reverse-type super junction 13 in the drift layer 12, the electric field distribution in the drift layer 12 is changed, the maximum electric field at the channel and the drift layer 12 interface is reduced, and the problem of device reliability reduction caused by avalanche effect due to high electric field when the reverse bias voltage is applied is avoided.

[0056] In one embodiment, the number of doped semiconductor pillars 15 is multiple, and the number of reverse-type super junctions 13 is one or multiple.

[0057] In one embodiment, the number of doped semiconductor pillars 15 is multiple, and the multiple doped semiconductor pillars 15 are arrayed on the drift layer 12, and the reverse-type super junction 13 is disposed between adjacent doped semiconductor pillars 15.

[0058] In one embodiment, the distance between adjacent doped semiconductor pillars 15 is the same, and the reverse-type super junction 13 is not in contact with the doped semiconductor pillars 15.

[0059] In one embodiment, in combination with Figure 1As shown, the doping type of the source doped layer 16 is the same as that of the drift layer 12, and the doping concentration of the source doped layer 16 is greater than that of the drift layer 12.

[0060] In a specific application, the second type of doping ions is different from the first type of doping ions, for example, the second type of doping ions is P-type doping, and the first type of doping ions is N-type doping, or the second type of doping ions is N-type doping, and the first type of doping ions is P-type doping.

[0061] In an embodiment, the first type of doping ions doped in the drift layer and the drain doped layer 10 can be N-type doping ions, such as aluminum ions, boron ions, etc.

[0062] In an embodiment, the second type of doping ions doped in the anti-type super junction 13 and the doped semiconductor column can be P-type doping ions, such as phosphorus ions, nitrogen ions, etc.

[0063] In an embodiment, the depth of the anti-type super junction 13 is greater than 1 / 2 of the thickness of the drift layer 12.

[0064] In this embodiment, by setting the anti-type super junction in the drift layer 12, the internal electric field distribution of the power device can be changed in the reverse bias application scenario of the power device, so as to reduce the maximum electric field in the power device and avoid avalanche effect of the device.

[0065] In an embodiment, the shape of the anti-type super junction 13 can be rectangular, which is perpendicular to the connecting line between the anti-type super junction and the doped semiconductor column.

[0066] In this embodiment, the anti-type super junction 13 can be rectangular, which divides the upper part of the drift layer 12 into several regions, and the anti-type super junction is arranged between adjacent doped semiconductor columns 15, so that the maximum electric field in the power device is reduced.

[0067] In an embodiment, the doping concentration of the doped semiconductor column 15 is greater than that of the anti-type super junction.

[0068] In an embodiment, the vertical structure power device further comprises a gate electrode, and the doped semiconductor column 15 is connected to the gate electrode through a contact hole.

[0069] In this embodiment, the doped semiconductor column 15 as the gate region of the power device can be connected to the gate electrode by filling a metal wire in the contact hole, and the gate electrode can be arranged on the surface of the packaging layer.

[0070] In an embodiment, the dielectric layer 14 can be silicon oxide or silicon nitride.

[0071] In an embodiment, the surface work function metal 17 can be gold or palladium.

[0072] The embodiment of the present application also provides a manufacturing method of a vertical structure power device, referring to Figure 2 As shown in the figure, the manufacturing method comprises steps S101 to S107.

[0073] In step S101, a drain doped layer is formed, which is doped with first type doping ions.

[0074] In combination with Figure 3 As shown in the figure, first, a drain doped layer 10 is formed, which is doped with first type doping ions, for providing support for subsequent processes.

[0075] In specific applications, a drain electrode can also be arranged below the drain doped layer 10, which can serve as a drain of a MOS device, or a collector of an IGBT device.

[0076] Further, the drain doped layer 10 can be arranged on a substrate, and the drain doped layer 10 can be formed by injecting first type doping ions into the substrate, or by epitaxial growth on the substrate.

[0077] Specifically, the substrate can be a silicon-based substrate, or other compound semiconductor substrates, such as gallium nitride, silicon carbide, gallium arsenide, etc. In step S102, a drift layer is formed on the drain doped layer, wherein the doping type of the drift layer is the same as the doping type of the drain doped layer, and the doping concentration of the drift layer is less than the doping concentration of the drain doped layer.

[0078] In the embodiment, in combination with Figure 4 As shown in the figure, the drift layer 12 can be prepared on the drain doped layer 10 by epitaxial growth, or ion implantation, the doping type of the drift layer 12 is the same as the doping type of the drain doped layer 10, and the doping concentration of the drift layer 12 is less than the doping concentration of the drain doped layer.

[0079] In step S103, a reverse type super junction is formed in the drift layer, which is doped with second type doping ions.

[0080] In combination with Figure 4 As shown in the figure, the reverse type super junction 13 is arranged in the drift layer 12, wherein the reverse type super junction 13 is doped with second type doping ions, which are different from the first type doping ions in the drift layer 12, for example, the first type doping ions can be N-type doping ions, and the second type doping ions are P-type doping ions.

[0081] In one embodiment, in step S103, the reverse type super junction is formed in the drift layer, specifically comprising:

[0082] determining a super junction doping region on the drift layer by using a first mask layer;

[0083] forming the inverse type super junction in the drift layer by implanting second type doping ions into the super junction doping region.

[0084] Specifically, the super junction doping region is determined on the surface of the drift layer 12 by using the first mask layer, and then the inverse type super junction 13 is formed by implanting second type doping ions into the drift layer 12 under the protection of the first mask layer.

[0085] Specifically, the depth of ion implantation when forming the inverse type super junction 13 is less than the thickness of the drift layer 12, and greater than 1 / 2 of the thickness of the drift layer 12.

[0086] In this embodiment, by setting the inverse type super junction 13 in the drift layer 12, the internal electric field distribution of the power device can be changed under the reverse bias application scenario of the power device, so as to reduce the maximum electric field in the power device and avoid avalanche effect of the device.

[0087] In one embodiment, the shape of the inverse type super junction 13 can be a rectangle, which is perpendicular to the line between the doped semiconductor column.

[0088] In this embodiment, the inverse type super junction 13 can be a rectangle, which divides the upper part of the drift layer 12 into several regions. If multiple inverse type super junctions 13 are set in the drift layer 12, the space between adjacent inverse type super junctions 13 cannot be too small to accommodate the doped semiconductor column and reduce the maximum electric field in the power device.

[0089] In step S104, a doped semiconductor column is formed on the drift layer.

[0090] In this embodiment, in combination with Figure 5 As shown in FIG. 1, the columnar channel can be made by using a channel mask and a photoetching process, and then second type doping ions are implanted into the columnar channel to form the doped semiconductor column 15.

[0091] In one embodiment, the doped semiconductor column formed on the drift layer can specifically include:

[0092] A semiconductor column etching region is determined on the drift layer by using a second mask layer, and a semiconductor column is formed by an etching process;

[0093] Second type ions are implanted into the semiconductor column to form the doped semiconductor column.

[0094] In combination with Figure 5As shown, the second mask layer determines the semiconductor pillar etching area on the drift layer 12, and then the semiconductor pillars are formed by etching process, at this time, the semiconductor pillars are mainly doped with the first type of doping ions, and finally by injecting the second type of ions into the semiconductor pillars, the doped semiconductor pillars 15 can be formed, and the doping concentration of the doped semiconductor pillars 15 is greater than the doping concentration of the reverse type super junction 13.

[0095] In step S105, a surface work function metal is formed on the side surface of the doped semiconductor pillar.

[0096] In combination Figure 5 As shown, the surface work function metal 17 can be formed on the upper surface of the doped semiconductor pillar 15.

[0097] In a specific application, the surface work function metal 17 can be formed on the surface of the doped semiconductor pillar 15 and the drift layer by using a metal gate deposition process.

[0098] In step S106, a dielectric layer is formed on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor pillar.

[0099] In combination Figure 6 As shown, the dielectric layer 14 can be formed on the drift layer 12 by deposition process, and then part of the doped semiconductor pillar 15 is etched as needed to prepare for the subsequent source doping layer.

[0100] In one embodiment, forming a dielectric layer on the drift layer comprises:

[0101] Forming a third mask on the region of the doped semiconductor pillar;

[0102] Forming a dielectric layer on the drift layer by depositing dielectric material, and etching the dielectric layer under the protection of the third mask.

[0103] In combination Figure 6 As shown, the region of the doped semiconductor pillar 15 can be covered by the third mask to avoid the impact of the subsequent dielectric material deposition process on the doped semiconductor pillar 15.

[0104] Under the cover of the third mask, the dielectric layer 14 is formed on the drift layer 12 by depositing dielectric material, at this time, due to the protection of the third mask, chemical mechanical polishing (CMP) process and etching process can be used to thin the dielectric layer 14 to expose part of the doped semiconductor pillar 15.

[0105] In step S107, a source doping layer is formed on the dielectric layer, and the source doping layer is connected with the doped semiconductor pillar.

[0106] In combination Figure 1As shown, in the present embodiment, the source doped layer 16 can be formed on the dielectric layer 14 by epitaxial growth of the source material, which is connected with the doped semiconductor 15 exposed in step S106.

[0107] In one specific application embodiment, after the process of steps S101 to S107 is completed, the terminals of different kinds of devices can be respectively connected with metal wires through the contact holes to be connected with the electrodes on the surface of the packaging layer.

[0108] The present application also provides an electronic device comprising the vertical structure power device according to any one of the above embodiments.

[0109] The present application has the beneficial effect that: by comprising the drain doped layer, the drift layer, the inversion super-junction, the doped semiconductor column, the surface work function metal, the dielectric layer and the source doped layer, the reverse withstand voltage of the power device is improved by the low doped drift layer, then the electric field distribution in the drift layer is changed by setting the inversion super-junction in the drift layer, the maximum electric field at the interface between the channel and the drift layer is reduced, and the problem that the device reliability is reduced due to avalanche effect caused by high electric field when the reverse bias voltage is applied is avoided.

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned doped regions is exemplified, and in actual application, the above-mentioned functions can be allocated by different doped regions, i.e. the internal structure of the device is divided into different doped regions to complete all or part of the functions described above.

[0111] The doped regions in the embodiments can be integrated in one functional region, or each doped region can exist physically alone, or two or more doped regions can be integrated in one functional region, and the integrated functional region can be realized by the same kind of doping ions or by multiple kinds of doping ions. In addition, the specific names of the doped regions are only for the convenience of mutual differentiation, and are not used to limit the protection scope of the present application. The specific working process of the doped regions in the preparation method of the device can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0112] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that: the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A vertical structure power device, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. A drain doped layer doped with first type doping ions; A drift layer arranged on the drain doped layer, wherein the doping type of the drift layer is the same as that of the drain doped layer, and the doping concentration of the drift layer is less than that of the drain doped layer; A reverse type super junction arranged in the drift layer, wherein the reverse type super junction is doped with second type doping ions; A doped semiconductor column arranged on the drift layer and doped with second type doping ions; the distance between adjacent doped semiconductor columns is the same, and the reverse type super junction is not in contact with the doped semiconductor column; a plurality of the doped semiconductor columns are arranged on the drift layer, and the reverse type super junction is arranged between adjacent doped semiconductor columns; A surface work function metal formed on the side surface of the doped semiconductor column; A dielectric layer arranged on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column; A source doped layer arranged on the dielectric layer and connected with the doped semiconductor column.

2. The vertical structure power device of claim 1, wherein, The number of the doped semiconductor columns is a plurality, and the number of the reverse type super junction is one or more.

3. The vertical structure power device of claim 2, wherein, The doping type of the source doped layer is the same as that of the drift layer, and the doping concentration of the source doped layer is greater than that of the drift layer.

4. The vertical structure power device of claim 1, wherein, The depth of the reverse type super junction is greater than 1 / 2 of the thickness of the drift layer.

5. A method of fabricating a vertical structure power device, characterized by, The manufacturing method comprises: forming a drain doped layer doped with first type doping ions; forming a drift layer on the drain doped layer, wherein the doping type of the drift layer is the same as that of the drain doped layer, and the doping concentration of the drift layer is less than that of the drain doped layer; forming a reverse type super junction in the drift layer, wherein the reverse type super junction is doped with second type doping ions; forming a doped semiconductor column on the drift layer; the distance between adjacent doped semiconductor columns is the same, and the reverse type super junction is not in contact with the doped semiconductor column; a plurality of the doped semiconductor columns are arranged on the drift layer, and the reverse type super junction is arranged between adjacent doped semiconductor columns; forming a surface work function metal on the side surface of the doped semiconductor column; forming a dielectric layer on the drift layer, wherein the depth of the dielectric layer is less than the height of the doped semiconductor column; forming a source doped layer on the dielectric layer, wherein the source doped layer is connected with the doped semiconductor column.

6. The method of manufacturing a vertical structure power device according to claim 5, wherein The forming of the reverse type super junction in the drift layer comprises: determining a super junction doping area on the drift layer by using a first mask layer; injecting second type doping ions into the super junction doping area to form the reverse type super junction in the drift layer.

7. The method of manufacturing a vertical structure power device according to claim 5, wherein The forming of the doped semiconductor column on the drift layer comprises: determining a semiconductor column etching area on the drift layer by using a second mask layer, and forming a semiconductor column through an etching process; injecting second type ions into the semiconductor column to form the doped semiconductor column.

8. The method of fabricating a vertical structure power device according to claim 5, wherein The forming of the dielectric layer on the drift layer comprises: forming a third mask in the region of the doped semiconductor column; A dielectric layer is formed on the drift layer by depositing a dielectric material and etching the dielectric layer under the protection of the third mask.

9. An electronic device, comprising: The vertical structure power device according to any one of claims 1 to 4.

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