Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device comprising a substrate including a plurality of parallel active regions arranged in an array; an isolation structure located between the active regions; a buried word line located in the substrate and intersecting the isolation structure and the active regions; and an insulating pad layer disposed in the substrate directly below the buried word line and located between adjacent ends of the active regions. The bottom surface of the insulating pad layer is lower than the bottom surface of the isolation structure, thereby reducing leakage current between adjacent active regions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a dynamic random access memory (DRAM) and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell includes a transistor electrically connected to a capacitor. The transistor controls the storage or release of charge in the capacitor to store data. The control circuitry can access each memory cell to control data access via word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] To achieve higher density, dynamic random access memory (DRAM) structures are evolving toward three-dimensional architectures, employing buried wordline gates and stacked capacitors. As memory cells become increasingly dense, ensuring electrical isolation between them to minimize signal crosstalk has become a key research topic in this field. Summary of the Invention

[0004] The present invention aims to provide a semiconductor device and a method for manufacturing the same, in which an insulating pad is provided directly below the isolation structure between active regions, thereby improving the electrical isolation effect and reducing signal crosstalk.

[0005] One embodiment of the present invention provides a semiconductor device comprising a substrate including a plurality of parallel active regions arranged in an array; an isolation structure located between the plurality of active regions; a buried word line located in the substrate and intersecting the isolation structure and the plurality of active regions; and an insulating pad layer disposed in the substrate directly below the buried word line and located between adjacent ends of the plurality of active regions, wherein the bottom surface of the insulating pad layer is lower than the bottom surface of the isolation structure.

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. First, a substrate is provided, and then an isolation trench is formed in the substrate to define a plurality of active areas in the substrate. A first dielectric layer is then formed to fill the isolation trench, wherein the first dielectric layer includes a plurality of deep holes, each located between adjacent ends of the plurality of active areas. Next, an etching process is performed to extend the plurality of deep holes downward into the substrate to below the bottom surface of the isolation trench, and then a second dielectric layer is formed to fill the plurality of deep holes. Subsequently, a word line trench is formed, cutting through the first dielectric layer, the second dielectric layer and the plurality of active areas, wherein the remaining portion of the second dielectric layer forms a plurality of insulating pads located below the word line trench. Thereafter, a buried word line is formed in the word line trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0008] Figures 1 to 9 FIG is a schematic diagram of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 1 、 Figure 3 and Figure 7 For the plan view, Figure 2 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 8 and Figure 9 The left side is a cross-sectional view along the BB' tangent line in the plan view, and the right side is a cross-sectional view along the AA' tangent line in the plan view.

[0009] Figure 10 are cross-sectional views of semiconductor devices according to other embodiments of the present invention.

[0010] The description of the accompanying drawings is as follows:

[0011] 10 substrate

[0012] 12 Active region

[0013] 13 Hard Mask Layer

[0014] 14 Isolation trench

[0015] 20 First dielectric layer

[0016] 20a Isolation structure

[0017] 22 deep holes

[0018] 30 Second dielectric layer

[0019] 30a Insulation pad

[0020] 40-line groove

[0021] 42 gate dielectric layer

[0022] 44 conductive layer

[0023] 46 cap layer

[0024] E1 etching process

[0025] WL buried word line

[0026] BG buried gate

[0027] PG through the gate

[0028] AA' tangent

[0029] BB' tangent

[0030] D1 direction

[0031] D2 direction

[0032] D3 direction

[0033] W1 width

[0034] W2 width

[0035] W3 width

[0036] W4 width

[0037] a Angle

[0038] R1 Depth

[0039] R2 Depth

[0040] r Depth difference. DETAILED DESCRIPTION

[0041] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, reorganized, or combined to create other embodiments without departing from the spirit of the present invention.

[0042] Please refer to Figures 1 to 9 , is a schematic diagram of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, Figure 1 and Figure 2 As shown, a substrate 10 composed of a semiconductor material is provided. For example, it can be a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Substrate 10 may include a first conductivity type dopant to form a well region having the first conductivity type. According to one embodiment of the present invention, the first conductivity type is P-type. Suitable P-type dopants include, but are not limited to, boron (B), aluminum (Al), and gallium (Ga). Figure 1 Directions D1 and D2 are indicated as being perpendicular to the plane of substrate 10. A hard mask layer 13, such as, but not limited to, a silicon nitride layer, may be provided on the surface of substrate 10. Next, an etching process is performed on substrate 10 to form isolation trenches 14 therein, defining a plurality of active regions 12. Each active region 12 is elongated, with its major axis extending along direction D3, and is arranged parallel to one another in an array. According to one embodiment of the present invention, direction D3 is different from direction D1 and direction D2, and includes an angle between 30 and 75 degrees with direction D1. Figure 1 The AA' tangent line is a tangent line extending along the direction D3 and cutting through the active region 12, and the BB' tangent line is a tangent line extending along the direction D2 and cutting through the active region 12. Figure 2 As shown in the right figure, the isolation trench 14 between adjacent ends of the active region 12 may have a width W1 in the AA′ tangent direction and a depth R1 from the surface of the substrate 10 .

[0043] like Figure 3 and Figure 4 As shown, a first dielectric layer 20 is then formed on the substrate 10, and the thickness of the first dielectric layer 20 is controlled to be sufficient to fill the isolation trenches 14 between the sidewalls of the active region 12 but not to fill the isolation trenches 14 between the adjacent ends of the active region 12, thereby forming a deep hole 22 between the adjacent ends of the active region 12. It should be noted that Figure 3 The outline of the active area 12 is drawn to understand the relative position of the deep hole 22 and the active area 12. Figure 3 The active area 12 is now completely covered by the first dielectric layer 20. The first dielectric layer 20 is made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. According to one embodiment of the present invention, the first dielectric layer 20 is made of silicon oxide. The first dielectric layer 20 can be formed by a deposition process (such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process), or the substrate 10 can be oxidized by an oxidation process (such as a thermal oxidation process or an on-site steam oxidation process) to form the first dielectric layer 20. Figure 4In the right figure, the deep hole 22 may have a width W2 in the AA′ tangent direction. Since the first dielectric layer 20 covers the sidewalls of the isolation trench 14, the width W2 is smaller than the width W1.

[0044] like Figure 5 As shown, an etching process E1 is then performed to extend the depth of the deep hole 22 into the substrate 10. Etching process E1 can be a multi-stage etching process. For example, a first stage etching process is performed, in which a dry etching process is used to anisotropically remove the first dielectric layer 20 on the surface of the hard mask layer 13 and the first dielectric layer 20 at the bottom of the deep hole 22, until the surface of the hard mask layer 13 and the substrate 10 surface at the bottom of the deep hole 22 are exposed. Next, a second stage etching process is performed, in which a dry etching process or a wet etching process is used to selectively etch the exposed portion of the substrate 10 through the deep hole 22, thereby extending the bottom of the deep hole 22 downward into the substrate 10 and lowering the bottom surface of the deep hole 22 below the bottom surface of the isolation trench 14. During the second stage etching process, the hard mask layer 13 and the first dielectric layer 20 protect other portions of the substrate 10 from being etched. After etching process E1, the deep hole 22 may have a depth R2 from the surface of the substrate 10, with a depth difference r between the depth R2 and the depth R1 of the isolation trench 14. According to one embodiment of the present invention, the depth difference r may be between 1 / 5 and 1 / 10 of the depth R1, but is not limited thereto. After the etching process E1, another selective etching process may be performed to remove the hard mask layer 13 from the surface of the substrate 10, or the hard mask layer 13 may be retained as a polishing stop layer or polishing buffer layer for a subsequent planarization process. Figure 5 As shown, the portion of the first dielectric layer 20 remaining in the isolation trench 14 becomes the isolation structure 20a. The deep hole 22 is still surrounded by the isolation structure 20a, and the end sidewalls of the active area 12 are not exposed.

[0045] like Figure 6As shown, a deposition process (such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process) can then be performed to form a second dielectric layer 30 on the substrate 10 and fill the deep hole 22 with the second dielectric layer 30. A planarization process or an etching process is then performed to remove excess second dielectric layer 30 outside the deep hole 22. The second dielectric layer 30 is composed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. According to one embodiment of the present invention, the second dielectric layer 30 and the first dielectric layer 20 include different materials. For example, when the first dielectric layer 20 includes silicon oxide, the second dielectric layer 30 may include silicon nitride. The second dielectric layer 30 may optionally include a neutral or specific conductivity type dopant to serve as a solid state doping (SSD) source layer. In some embodiments, the second dielectric layer 30 may include a neutral dopant, such as carbon (C). In some embodiments, the second dielectric layer 30 may include a second conductivity type (e.g., N-type) dopant, such as phosphorus (P) or arsenic (As), but is not limited thereto.

[0046] like Figure 7 and Figure 8 As shown, the substrate 10 is then etched to form a plurality of parallel word line trenches 40, which extend along the direction D1 and cut through the active area 12, the isolation structure 20a (the first dielectric layer 20), and the second dielectric layer 30 located in the deep hole 22, thereby obtaining an insulating pad layer 30a located directly below and arranged along the word line trenches 40. Figure 8 As shown in the left figure, due to the difference in etching rates of the substrate 10, the first dielectric layer 20, and the second dielectric layer 30, the bottom surface of the word line trench 40 will have a concave-convex profile, wherein the insulating pad layer 30a and the isolation structure 20a are sunken relative to the substrate 10. In other words, the top surface of the insulating pad layer 30a and the isolation structure 20a is not coplanar with the surface of the substrate 10. Figure 8As shown in the right figure, the depth of the wordline trench 40 is less than that of the isolation trench 14, and the bottom surface of the isolation trench 14 is lower than the bottom surface of the wordline trench 40. The wordline trench 40 may have a width W3 along the AA' tangent direction. In this embodiment, width W3 is less than width W1 of the isolation trench 14 and greater than width W2 of the deep hole 22. In this case, the sidewalls of the active area 12 ends on both sides of the insulating pad 30a can remain covered by the isolation structure 20a and not protrude from the wordline trench 40. In other embodiments, when width W3 is substantially equal to or slightly greater than width W1 of the isolation trench 14, the ends of the active area 12 on both sides of the insulating pad 30a can protrude from the wordline trench 40. The insulating pad 30a is formed from the second dielectric layer 30 filling the bottom of the deep hole 22 and has a width W2. The upper sidewalls of the insulating pad 30a are in direct contact with the isolation structure 20a, while the lower sidewalls and bottom surface are in direct contact with the substrate 10. In some embodiments, an annealing step may be performed after forming wordline trenches 40 to propagate the doping of insulating pad layer 30a into substrate 10, forming doped regions 30b. Doped regions 30b may have a second conductivity type, such as N-type. Doped regions 30b have an opposite conductivity type to the well region of substrate 10.

[0047] like Figure 9 As shown, a deposition process (such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process) may then be performed to form a gate dielectric layer 42 along the sidewalls and bottom surface of the wordline trench 40. A conductive layer 44 and a capping layer 46 are then formed to fill the wordline trench 40, thereby obtaining a buried wordline WL. The gate dielectric layer 42 may be made of, but is not limited to, silicon oxide, silicon nitride, a high-k dielectric material, or a combination thereof. The conductive layer 44 may be made of, but is not limited to, titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), gold (Au), a work function metal, a low resistance metal, or a combination thereof. The capping layer 46 may be made of, but is not limited to, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, a barrier layer (not shown) may be included between the gate dielectric layer 42 and the conductive layer 44. The material may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (TiW), or a combination of the above materials, but is not limited thereto.

[0048] At this point in the process, the semiconductor device of the present invention is obtained, which can be used to fabricate a dynamic random access memory. The portion of the buried word line WL that cuts through the active region 12 between adjacent ends is called the passing gate PG, while the portion that cuts through the interior of the active region 12 is called the buried gate BG. The buried gate BG controls the conduction and cutoff of the current in the memory cell transistor, and the passing gate PG is used to connect the memory cells in series. As memory cell sizes continue to shrink, the spacing between active regions 12 becomes increasingly tighter. This makes it easy for the buried word line WL's passing gate PG to form parasitic elements at the ends of the active region 12 after repeated read and write operations. The resulting leakage current can cause signal crosstalk between memory cells. The present invention provides an insulating pad layer 30a that is deeper than the isolation structure 20a directly below the passing gate PG of the buried word line WL. This reduces leakage current between adjacent memory cells and thereby improves signal crosstalk. In some embodiments, solid state doping (SSD) technology may be used to form a doped region 30b around the insulating pad layer 30a. The doped region 30b has an opposite conductivity type to the substrate 10 (well region), thereby forming a depletion region to further enhance electrical isolation.

[0049] Please refer to Figure 10 , which are cross-sectional views of semiconductor devices according to other embodiments of the present invention. The insulating pad layer 30a is composed of a second dielectric layer 30 filling the bottom of the deep hole 22. Therefore, by adjusting the parameters of the etching process E1, deep holes 22 of different shapes and sizes can be produced, thereby obtaining insulating pad layers 30a with different cross-sectional profiles. For example, Figure 10 As shown in the upper figure, the dry etching process or wet etching process parameters of the second stage etching of the etching process E1 can be adjusted so that the bottom surface of the deep hole 22 has an arc-shaped profile, and thus the bottom surface of the insulating pad layer 30a obtained can have an arc-shaped profile. Figure 10As shown in the lower figure, a wet etching process can be performed in the second etching stage, using an etchant such as tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), and / or ethylenediamine pyrocatechol (EDP) to etch the substrate 10 (e.g., a silicon substrate). This causes the bottom sidewalls of the deep hole 22 to have a rhombus or diamond-shaped cross-sectional profile along a specific crystal plane of the substrate 10, and the subsequently formed insulating pad layer 30a also has a rhombus or diamond-shaped cross-sectional profile. In some embodiments, the sidewalls of the insulating pad layer 30a can have an angle a of approximately 54.7 degrees with respect to a direction parallel to the surface of the substrate 10. In some embodiments, the side etching during the wet etching process can cause the width W4 of the insulating pad layer 30a at its widest point to be greater than the width W3 of the buried word line WL. Other shapes of the insulating pad layer 30a not exemplified herein are also intended to be within the scope of the present invention.

[0050] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate of a first conductivity type, comprising a plurality of active regions parallel to each other and arranged in an array; an isolation structure located between the plurality of active regions; a buried word line located in the substrate and cutting through the isolation structure and the plurality of active areas; an insulating pad layer, disposed in the substrate directly below the buried word line and between adjacent ends of the plurality of active regions, wherein a bottom surface of the insulating pad layer is lower than a bottom surface of the isolation structure; as well as, A doped region is located in the substrate, directly contacts the sidewall and bottom surface of the insulating pad layer, and has a second conductive type opposite to the first conductive type.

2. The semiconductor device according to claim 1, wherein The isolation structure and the insulating pad layer include different materials.

3. The semiconductor device according to claim 1, wherein A bottom surface of the isolation structure is lower than a bottom surface of the buried word line.

4. The semiconductor device according to claim 1, wherein The sidewall of the insulating pad is in direct contact with the isolation structure.

5. The semiconductor device according to claim 1, wherein The buried word line comprises: a gate dielectric layer, directly contacting the insulating pad layer; a conductive layer located on the gate dielectric layer; and A cover layer is located on the conductive layer.

6. The semiconductor device according to claim 1, wherein The width of the insulating pad layer is smaller than the width of the buried word line.

7. The semiconductor device according to claim 1, wherein The width of the insulating pad layer is greater than the width of the buried word line.

8. The semiconductor device according to claim 1, wherein The insulating pad includes an included angle of 54.7 degrees.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate of a first conductivity type; forming an isolation trench in the substrate to define a plurality of active areas; forming a first dielectric layer to fill the isolation trench, wherein the first dielectric layer includes a plurality of deep holes respectively located between adjacent ends of the plurality of active regions; Performing an etching process to extend the plurality of deep holes downward into the substrate to a level lower than the bottom surface of the isolation trench; forming a second dielectric layer to fill the plurality of deep holes; forming a word line trench, cutting through the first dielectric layer, the second dielectric layer and the plurality of active areas, wherein a remaining portion of the second dielectric layer forms a plurality of insulating pads located below the word line trench; forming a doped region located in the substrate and in direct contact with the sidewalls and bottom surface of the insulating pad layer, wherein the doped region has a second conductivity type opposite to the first conductivity type; and forming a buried word line in the word line trench.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The first dielectric layer and the second dielectric layer include different materials.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: A bottom surface of the isolation trench is lower than a bottom surface of the buried word line.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: The etching process includes: performing a dry etching process to remove the first dielectric layer at the bottoms of the plurality of deep holes to expose the substrate; as well as A wet etching process is performed to etch the substrate exposed from the bottoms of the plurality of deep holes.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: The steps of forming the buried word line include: forming a gate dielectric layer along the bottom surface and sidewalls of the word line trench, wherein the gate dielectric layer is in direct contact with the plurality of insulating pad layers; forming a conductive layer on the gate dielectric layer; and A capping layer is formed on the conductive layer and fills the word line trench.

14. The method for manufacturing a semiconductor device according to claim 9, wherein: The width of the insulating pad layer is smaller than the width of the buried word line.

15. The method for manufacturing a semiconductor device according to claim 9, wherein: The width of the insulating pad layer is greater than the width of the buried word line.

16. The method for manufacturing a semiconductor device according to claim 9, wherein: After the etching process, portions of the plurality of deep holes located in the substrate include a rhombus or diamond-shaped cross-sectional profile.

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