Silicon-passivated p-GaN gate enhancement-mode MIS-HEMT device and its preparation method

Abstract

The present invention discloses a p-GaN gate-enhanced MIS-HEMT device based on silicon passivation and a method for preparing the same. The device comprises a substrate layer, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, arranged sequentially from bottom to top. Isolation regions are provided on either side of the barrier layer, extending from the upper surface of the barrier layer to the upper surface of the buffer layer. A cap layer, a passivation layer, an oxide layer, and a gate electrode are sequentially arranged in the middle of the upper surface of the barrier layer, from bottom to top. A source electrode and a drain electrode are provided on either side of the upper surface of the barrier layer. By depositing a passivation layer on the cap layer, the present invention isolates the oxide layer from the barrier layer, significantly passivating the surface states and defects of the p-GaN material, effectively improving the p-GaN gate voltage resistance, improving the device's threshold voltage drift, increasing output current, and reducing gate leakage current.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a p-GaN gate enhancement type MIS-HEMT device based on silicon passivation and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN)-based High Electron Mobility Transistors (HEMTs) utilize a two-dimensional electron gas structure to form a conductive channel, resulting in excellent performance with high electron mobility and high breakdown voltage. Due to the wide bandgap of GaN material, GaN-based HEMT devices exhibit excellent high-temperature and radiation resistance, making them popular in harsh applications such as high-frequency, high-voltage, and high-power applications.

[0003] The p-GaN gate enhancement mode HEMT device depletes the two-dimensional electron gas under the gate region through the built-in electric field generated by the p-GaN gate structure. It has a high threshold voltage, saturation current and small on-resistance. In recent years, it has been used in the field of fast charging of electronic products such as mobile phones and computers.

[0004] The gate oxide layer of p-GaN gate-enhancement MIS (metal-insulator-semiconductor)-HEMT devices can effectively reduce gate leakage current. However, because the epitaxial growth process of GaN material proceeds in a non-thermodynamic equilibrium state, a large number of defects and dangling bonds are generated on the material surface. The interface states between GaN and the oxide layer can capture or release electrons, causing problems such as device threshold voltage drift, gain reduction, and cutoff frequency reduction. This leads to device parameter degradation and reduced reliability. As a result, p-GaN gate-enhancement MIS-HEMT devices have not been commercialized. Summary of the Invention

[0005] To address the above-mentioned problems in the prior art, the present invention provides a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation and a method for manufacturing the same. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0006] One aspect of the present invention provides a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation, comprising a substrate layer, a nucleation layer, a buffer layer, a channel layer, and a barrier layer arranged in sequence from bottom to top, wherein isolation regions are respectively provided on both sides of the barrier layer, and the isolation regions extend from the upper surface of the barrier layer to the upper surface of the buffer layer;

[0007] A cap layer, a passivation layer, an oxide layer and a gate electrode are sequentially arranged in order from bottom to top at the middle position of the upper surface of the barrier layer, and a source electrode and a drain electrode are respectively arranged on both sides of the upper surface of the barrier layer.

[0008] In one embodiment of the present invention, the nucleation layer is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer is an AlGaN buffer layer with a thickness of 200-8000 nm, the channel layer is a GaN channel layer with a thickness of 50-500 nm, and the barrier layer is an AlGaN layer with a thickness of 10-30 nm. x Ga 1-x N barrier layer, where x=0.1~0.5.

[0009] In one embodiment of the present invention, the cap layer is a Mg-doped p-GaN cap layer with a thickness of 80 to 150 nm, wherein the Mg doping concentration is 10 18 ~10 20 cm -3 .

[0010] In one embodiment of the present invention, the isolation region is an N ion implantation region formed by implanting N ions into the buffer layer and the channel layer.

[0011] In one embodiment of the present invention, the passivation layer is a Si passivation layer with a thickness of 1 to 5 nm, and the oxide layer is a SiO2 oxide layer with a thickness of 0.5 to 2 nm.

[0012] In one embodiment of the present invention, the upper surface of the barrier layer is covered with a surface passivation layer, and at least a portion of the upper surfaces of the source electrode, the drain electrode, and the gate electrode are not covered by the surface passivation layer.

[0013] Another aspect of the present invention provides a method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation, comprising:

[0014] S1: Select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer on the substrate;

[0015] S2: performing ion implantation on both sides of the cap layer to form an isolation region extending to the upper surface of the buffer layer;

[0016] S3: growing a passivation layer and an oxide layer in sequence on the upper surface of the cap layer;

[0017] S4: etching away the passivation layer, the oxide layer, and the cap layer outside the gate region, leaving only the passivation layer, the oxide layer, and the cap layer in the gate region;

[0018] S5: depositing a gate electrode on the upper surface of the oxide layer in the gate region;

[0019] S6: depositing source metal and drain metal in the source region and the drain region respectively, and forming ohmic contacts after annealing.

[0020] In one embodiment of the present invention, the S1 includes:

[0021] S11: Select a Si, SiC or sapphire substrate and clean it;

[0022] S12: On the substrate, an AlN nucleation layer with a thickness of 50-500 nm, an AlGaN buffer layer with a thickness of 200-8000 nm, a GaN channel layer with a thickness of 50-500 nm, an AlGaN layer with a thickness of 10-30 nm, and a GaN layer with a thickness of 100-150 nm are sequentially grown. x Ga 1-x N barrier layer, Mg-doped p-GaN cap layer with a thickness of 80~150nm, where x=0.1~0.5.

[0023] In one embodiment of the present invention, the S3 includes:

[0024] A Si passivation layer with a thickness of 1 to 5 nm is grown on the upper surface of the p-GaN cap layer, and then the upper surface of the Si passivation layer is partially thermally oxidized to form a SiO2 oxide layer with a thickness of 0.5 to 2 nm.

[0025] In one embodiment of the present invention, the S5 includes:

[0026] A gate metal is deposited on the upper surface of the oxide layer in the gate region by a magnetron sputtering process to form a gate MIS structure, wherein the gate metal is Ti, TiN or Al.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention proposes a p-GaN gate-enhancement-mode MIS-HEMT device based on silicon passivation. Since a large number of interface states usually exist between the gate oxide dielectric and the gallium nitride barrier layer, the charging and discharging of the interface states leads to phenomena such as threshold voltage drift. By depositing a Si passivation layer on the p-GaN cap layer and then partially thermally oxidizing a thin SiO2 layer, the SiO2 layer grown by Si thermal oxidation has higher uniformity, density, and dielectric constant than a directly deposited SiO2 oxide layer. It significantly passivates the surface states and defects of the p-GaN material, inhibits the capture or release of charges by traps in the gate dielectric, effectively improves the p-GaN gate withstand voltage, improves the device's threshold voltage drift, increases the output current, and reduces the gate leakage current, thereby obtaining a p-GaN gate-enhancement-mode MIS-HEMT device with excellent reliability.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1Schematic diagram of the structure of a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation provided by an embodiment of the present invention;

[0031] Figure 2 This is a schematic flow chart of a method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation provided by an embodiment of the present invention;

[0032] Figures 3a-3g This is a schematic diagram of the fabrication process of a silicon-passivated p-GaN gate-enhanced MIS-HEMT device provided by an embodiment of the present invention.

[0033] Description of reference numerals:

[0034] 1-substrate layer; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-barrier layer; 6-cap layer; 7-isolation region; 8-passivation layer; 9-oxide layer; 10-gate electrode; 11-source electrode; 12-drain electrode; 13-surface passivation layer. DETAILED DESCRIPTION

[0035] To further illustrate the technical means and effects employed by the present invention to achieve the intended purpose, a p-GaN gate-enhancement-mode MIS-HEMT device based on silicon passivation and a method for fabricating the same, according to the present invention, will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0037] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0038] Example 1

[0039] See Figure 1 , Figure 11 is a schematic structural diagram of a p-GaN gate-enhanced MIS-HEMT device based on silicon passivation provided by an embodiment of the present invention. The p-GaN gate-enhanced MIS-HEMT device includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5, which are arranged in sequence from bottom to top. Isolation regions 7 are respectively provided on both sides of the barrier layer 5, and the isolation regions 7 extend from the upper surface of the barrier layer 5 to the upper surface of the buffer layer 3. A cap layer 6, a passivation layer 8, an oxide layer 9, and a gate electrode 10 are sequentially arranged in sequence from bottom to top in the middle position of the upper surface of the barrier layer 5. A source electrode 11 and a drain electrode 12 are respectively provided on both sides of the upper surface of the barrier layer 5.

[0040] In this embodiment, the material selected for the substrate layer 1 is Si, SiC or sapphire.

[0041] Furthermore, the nucleation layer 2 is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer 3 is an AlGaN buffer layer with a thickness of 200-8000 nm, the channel layer 4 is a GaN channel layer with a thickness of 50-500 nm, and the barrier layer 5 is an AlGaN layer with a thickness of 10-30 nm. x Ga 1-x N barrier layer, where x = 0.1 to 0.5. The cap layer 6 is a Mg-doped p-GaN cap layer with a thickness of 80 to 150 nm, where the Mg doping concentration is 10 18 ~10 20 cm -3 Specifically, the cap layer 6 is located in the gate region on the upper surface of the barrier layer 5 .

[0042] Isolation region 7 is an N-ion implanted region formed by N-ion implantation in buffer layer 3 and channel layer 4. N-ion implantation in isolation region 7 forms a high-resistance region for device isolation. Passivation layer 8 is a Si passivation layer with a thickness of 1 to 5 nm, and oxide layer 9 is a SiO2 oxide layer with a thickness of 0.5 to 2 nm.

[0043] Preferably, the gate electrode 10 , the source electrode 11 and the drain electrode 12 are made of the same material, namely Ti, TiN or Al.

[0044] In addition, the upper surface of the barrier layer 5 is covered with a surface passivation layer 13, and at least a portion of the upper surfaces of the source electrode 11, the drain electrode 12, and the gate electrode 10 are not covered by the surface passivation layer 13. In other words, holes are etched in the surface passivation layer 13 on the upper surfaces of the source electrode 11, the drain electrode 12, and the gate electrode 10 to form interconnection contact holes for the source electrode, the drain electrode, and the gate electrode.

[0045] This embodiment proposes a p-GaN gate enhancement-mode MIS-HEMT device based on silicon passivation. By depositing a Si passivation layer on the p-GaN cap layer and then partially thermally oxidizing a thin SiO2 layer, the surface states and defects of the p-GaN material are significantly passivated, effectively improving the p-GaN gate withstand voltage, improving the device's threshold voltage drift, increasing output current, and reducing gate leakage current, thereby obtaining a p-GaN gate enhancement-mode MIS-HEMT device with excellent reliability.

[0046] Example 2

[0047] Based on the above embodiment, this embodiment provides a method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation, see Figure 2 、 Figures 3a to 3g , the preparation method comprises:

[0048] S1: Select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer on the substrate.

[0049] Specifically, a Si, SiC or sapphire substrate 1 is selected, and the surface of the substrate 1 is plasma cleaned and pretreated to keep the substrate surface clean; then, a metal organic chemical vapor deposition (MOCVD) process is used to sequentially grow an AlN nucleation layer 2 with a thickness of 50 to 500 nm, an AlGaN buffer layer 3 with a thickness of 200 to 8000 nm, a GaN channel layer 4 with a thickness of 50 to 500 nm, and an AlGaN layer with a thickness of 10 to 30 nm on the substrate. x Ga 1-x N barrier layer 5, Mg-doped p-GaN cap layer 6 with a thickness of 80~150nm, where x=0.1~0.5, such as Figure 3a shown.

[0050] S2: performing ion implantation on both sides of the cap layer to form an isolation region extending to the upper surface of the buffer layer.

[0051] Specifically, an ion implantation process is used to implant N ions into the isolation regions of the p-GaN cap layer 6, the GaN channel layer 5, and the AlGaN barrier layer 4 on both sides of the upper surface of the p-GaN cap layer 6. The N ion implantation concentration is 10 18 ~10 20 cm -3 , forming a high resistance region, namely the isolation region 7, to achieve device isolation, such as Figure 3b shown.

[0052] S3: sequentially growing a passivation layer and an oxide layer on the upper surface of the cap layer.

[0053] Specifically, ultra-high vacuum chemical vapor deposition (HUV-CVD) technology is used. SF6 plasma gas is introduced into the HUV-CVD epitaxial equipment to remove native oxides on the upper surface of the p-GaN cap layer 6. Si2H6 gas is introduced in a low-temperature growth environment. After the Si2H6 gas decomposes, it grows into a Si passivation layer 8 with a thickness of 1 to 5 nm. Subsequently, the upper surface of the Si passivation layer is partially thermally oxidized to form a SiO2 oxide layer 9 with a thickness of 0.5 to 2 nm. Figure 3c shown.

[0054] S4: etching away the passivation layer, the oxide layer and the cap layer outside the gate region, leaving only the passivation layer, the oxide layer and the cap layer in the gate region.

[0055] Specifically, the Si passivation layer and the SiO2 oxide layer are etched by reactive ion etching (RIE) technology, and the p-GaN cap layer is etched by inductively coupled plasma (ICP) technology. The Si passivation layer 8 and the SiO2 oxide layer 9 outside the gate area are dry-etched by RIE. The surface of the material is treated with hydrogen ion plasma using an ICP system, and then the p-GaN cap layer 6 outside the gate area is dry-etched. Figure 3d shown.

[0056] S5: depositing a gate electrode on the upper surface of the oxide layer in the gate region;

[0057] Specifically, a magnetron sputtering process or a physical vapor deposition (PVD) process is used to deposit a gate metal on the upper surface of the oxide layer in the gate region to form a gate electrode 10, thereby forming a gate MIS (metal-insulator-semiconductor) structure. Figure 3e As shown, the gate metal is Ti, TiN or Al.

[0058] S6: depositing source metal and drain metal in the source region and the drain region respectively, and forming ohmic contacts after annealing.

[0059] Specifically, see Figure 3f In this embodiment, a magnetron sputtering process is used to sputter source metal and drain metal in the source and drain regions, respectively, to form source electrode 11 and drain electrode 12. The source metal and drain metal are then annealed to achieve low-resistance ohmic contact between the source and drain electrodes. Preferably, similar to the gate metal, the source and drain metals of this embodiment are both Ti, TiN, or Al.

[0060] Furthermore, after step S6, the method further includes:

[0061] A dielectric is deposited on the surface of the above material and the surface is passivated to form a surface passivation layer 13. Subsequently, the source, drain and gate regions on the surface of the passivated material are opened and etched to form source, drain and gate interconnection contact holes, such as Figure 3g shown.

[0062] Specifically, the source, drain and gate contact holes are etched in the source region, drain region and gate region of the surface passivation layer 13 by adopting an inductive plasma coupling (ICP) process.

[0063] The preparation method of the embodiment of the present invention deposits a Si passivation layer on the p-GaN cap layer and then partially thermally oxidizes a thin SiO2 layer. Compared with the directly deposited SiO2 oxide layer, the SiO2 layer grown by Si thermal oxidation has higher uniformity, density and dielectric constant, significantly passivates the surface states and defects of the p-GaN material, inhibits the capture or release of charges by traps in the gate dielectric, effectively improves the p-GaN gate withstand voltage, improves the threshold voltage drift of the device, increases the output current, and reduces the gate leakage current, thereby obtaining a p-GaN gate enhancement mode MIS-HEMT device with excellent reliability.

[0064] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation, characterized in that: The invention comprises a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5) arranged in sequence from bottom to top, wherein isolation regions (7) are respectively provided on both sides of the barrier layer (5), and the isolation regions (7) extend from the upper surface of the barrier layer (5) to the upper surface of the buffer layer (3); A cap layer (6), a passivation layer (8), an oxide layer (9) and a gate electrode (10) are sequentially arranged in order from bottom to top at the middle position of the upper surface of the barrier layer (5); a source electrode (11) and a drain electrode (12) are respectively arranged on both sides of the upper surface of the barrier layer (5); wherein the passivation layer (8) is a Si passivation layer with a thickness of 1 to 5 nm, and the oxide layer (9) is a SiO2 oxide layer with a thickness of 0.5 to 2 nm.

2. The p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to claim 1, characterized in that: The nucleation layer (2) is an AlN nucleation layer with a thickness of 50 to 400 nm, the buffer layer (3) is an AlGaN buffer layer with a thickness of 200 to 8000 nm, the channel layer (4) is a GaN channel layer with a thickness of 50 to 500 nm, and the barrier layer (5) is an AlGaN layer with a thickness of 10 to 30 nm. x Ga 1-x N barrier layer, where x=0.1-0.

5.

3. The p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to claim 1, characterized in that: The cap layer (6) is a Mg-doped p-GaN cap layer with a thickness of 80 to 150 nm, wherein the Mg doping concentration is 10 18 ~10 20 cm -3 .

4. The p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to claim 1, characterized in that: The isolation region (7) is an N ion implantation region where N ions are implanted in the buffer layer (3) and the channel layer (4).

5. The p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to any one of claims 1 to 4, characterized in that: The upper surface of the barrier layer (5) is covered with a surface passivation layer (13), and at least a portion of the upper surfaces of the source electrode (11), the drain electrode (12), and the gate electrode (10) are not covered by the surface passivation layer (13).

6. A method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation, characterized in that: include: S1: Select a substrate and sequentially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer on the substrate; S2: performing ion implantation on both sides of the cap layer to form an isolation region extending to the upper surface of the buffer layer; S3: sequentially growing a passivation layer and an oxide layer on the upper surface of the cap layer; comprising: growing a Si passivation layer with a thickness of 1 to 5 nm on the upper surface of the p-GaN cap layer, and then partially thermally oxidizing the upper surface of the Si passivation layer to form a SiO2 oxide layer with a thickness of 0.5 to 2 nm; S4: etching away the passivation layer, the oxide layer, and the cap layer outside the gate region, leaving only the passivation layer, the oxide layer, and the cap layer in the gate region; S5: depositing a gate electrode on the upper surface of the oxide layer in the gate region; S6: depositing source metal and drain metal in the source region and the drain region respectively, and forming ohmic contacts after annealing.

7. The method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to claim 6, characterized in that: Said S1 comprises: S11: Select a Si, SiC or sapphire substrate and clean it; S12: On the substrate, an AlN nucleation layer with a thickness of 50 to 500 nm, an AlGaN buffer layer with a thickness of 200 to 8000 nm, a GaN channel layer with a thickness of 50 to 500 nm, an AlGaN layer with a thickness of 10 to 30 nm, and a GaN layer with a thickness of 100 to 150 nm are sequentially grown. x Ga 1-x N barrier layer, Mg-doped p-GaN cap layer with a thickness of 80 to 150 nm, wherein x=0.1 to 0.

5.

8. The method for preparing a p-GaN gate enhancement mode MIS-HEMT device based on silicon passivation according to any one of claims 6 to 7, characterized in that: The S5 includes: A gate metal is deposited on the upper surface of the oxide layer in the gate region by a magnetron sputtering process to form a gate MIS structure, wherein the gate metal is Ti, TiN or Al.

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