Display device

Abstract

The display device comprises, in order: a substrate; a first insulating layer; first and second lower electrodes; a second insulating layer having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a first trench located between the first and second openings; an organic layer including a light-emitting layer; and an upper electrode. The first trench has a bottom surface and first and second side surfaces rising from the bottom surface, wherein the distance between the first and second side surfaces of the upper portion of the first trench is smaller than the distance between the first and second side surfaces of the bottom surface of the first trench. The organic layer comprises: a first portion covering the first lower electrode located in the first opening and covering the first surface of the second insulating layer located between the first trench and the first opening; a second portion covering the second lower electrode located in the second opening and covering the second surface of the second insulating layer located between the first trench and the second opening; and a third portion disposed on the bottom surface of the first trench and separated from the first and second portions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2021-008036, filed on January 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become increasingly practical. Display elements include an organic layer between a pixel electrode and a common electrode. In addition to a light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer. These organic layers are formed, for example, by vacuum deposition.

[0005] The organic layer is preferably divided and arranged for each pixel, for example, in order to suppress crosstalk between adjacent pixels. For example, a method of forming the organic layer for each pixel by a vapor deposition method without using a mask is under study. Summary of the Invention

[0006] According to this embodiment, a display device is provided, comprising: a substrate; a first insulating layer disposed on the substrate; a first lower electrode and a second lower electrode disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, the second opening having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a first groove located between the first opening and the second opening; an organic layer including a light-emitting layer; and an upper electrode covering the organic layer, wherein the first groove has a bottom surface, a first side surface rising from the bottom surface, and a second side surface, wherein a distance between the first side surface and the second side surface of the upper portion of the first groove is smaller than a distance between the first side surface and the second side surface of the bottom surface of the first groove, and the organic layer has a first portion covering the first lower electrode located in the first opening and covering a first surface of the second insulating layer located between the first groove and the first opening; a second portion covering the second lower electrode located in the second opening and covering a second surface of the second insulating layer located between the first groove and the second opening; and a third portion disposed on the bottom surface of the first groove and separated from the first portion and the second portion.

[0007] This embodiment can provide a display device capable of suppressing degradation in display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1It is a plan view showing a configuration example of a display device according to this embodiment.

[0009] Figure 2 is a top view showing a pixel.

[0010] Figure 3 It is along Figure 2 The cross-sectional view of the display device is shown along line AA'.

[0011] Figure 4 It is a cross-sectional view showing a groove, an organic layer, etc.

[0012] Figure 5 It is a top view showing the organic layer.

[0013] Figure 6 It is along Figure 1 A cross-sectional view of the display device taken along line BB' is shown.

[0014] Figure 7 It is a cross-sectional view showing a first modified example of this embodiment.

[0015] Figure 8 It is a plan view showing a second modified example of this embodiment.

[0016] Figure 9 It is a plan view showing a third modified example of the present embodiment. DETAILED DESCRIPTION

[0017] Below, with reference to the attached Figure 1 The present embodiment is described while the disclosure is made. In addition, the disclosure is merely an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main purpose of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings schematically show the width, thickness, shape, etc. of each part compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference figure numerals are sometimes marked for components that perform the same or similar functions as the components described in the figures that have already appeared, and repeated detailed descriptions are appropriately omitted.

[0018] The display device DSP of this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and is mounted in a television, a personal computer, a mobile terminal, a mobile phone, or the like.

[0019] Figure 1 It is a plan view showing a configuration example of the display device DSP according to this embodiment.

[0020] The first direction X, second direction Y, and third direction Z shown in the drawings are mutually orthogonal. Furthermore, the first direction X, second direction Y, and third direction Z may intersect at angles other than 90 degrees. In this specification, the direction toward the tip of the arrow indicating the third direction Z is referred to as "up," and the direction away from the tip of the arrow is referred to as "down." Furthermore, assuming that there is an observation position for viewing the display device DSP at the tip of the arrow indicating the third direction Z, viewing from this observation position toward the X-Y plane defined by the first direction X and the second direction Y is referred to as a top view.

[0021] The display device DSP includes an insulating substrate 10. The substrate 10 may be glass or a flexible resin film. The display device DSP includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

[0022] The display device DSP includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y in a display area DA. Each pixel PX includes a plurality of sub-pixels SP1, SP2, and SP3. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Alternatively, the pixel PX may include four or more sub-pixels, including sub-pixels of other colors, such as white, in addition to the three aforementioned sub-pixels.

[0023] A configuration example of one sub-pixel SP included in the pixel PX will be briefly described.

[0024] That is, the sub-pixel SP includes a pixel circuit 1 and a display element 20 driven and controlled by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0025] The pixel switch 2 has a gate electrode connected to the scanning line GL, a source electrode connected to the signal line SL, and a drain electrode connected to one electrode of the capacitor 4 and the gate electrode of the drive transistor 3. The drive transistor 3 has a source electrode connected to the other electrode of the capacitor 4 and the power supply line PL, and a drain electrode connected to the anode of the display element 20. The cathode of the display element 20 is connected to the power supply line FL. The configuration of the pixel circuit 1 is not limited to the example shown in the figure.

[0026] The display element 20 is an organic light-emitting diode (OLED) serving as a light-emitting element. For example, sub-pixel SP1 includes a display element that emits light corresponding to a red wavelength, sub-pixel SP2 includes a display element that emits light corresponding to a green wavelength, and sub-pixel SP3 includes a display element that emits light corresponding to a blue wavelength. The structure of the display element 20 will be described later.

[0027] The display device DSP includes power lines 51 and 52, a plurality of peripheral electrodes 6, and pads PD1 and PD2 located in the non-display area NDA. Furthermore, the non-display area NDA includes a first area N1 and a second area N2 extending along the second direction Y, and a third area N3 extending along the first direction X. The first area N1, the display area DA, and the second area N2 are arranged in this order along the first direction X. A flexible wiring substrate (not shown) is mounted in the third area N3.

[0028] The power line 51 is located in the first region N1 and the power line 52 is located in the second region N2. The peripheral electrodes 6 are arranged in the first region N1 and the second region N2 along the second direction Y. The pads PD1 and PD2 are located in the third region N3.

[0029] The power supply line 51 is electrically connected to the peripheral electrodes 6 located in the first region N1. The power supply line 51 is also electrically connected to the pad PD1. The power supply line 52 is electrically connected to the peripheral electrodes 6 located in the second region N2. The power supply line 52 is also electrically connected to the pad PD2.

[0030] Figure 2 1 is a plan view showing a pixel PX.

[0031] exist Figure 2 , the figure shows the lower electrodes E11 , E12 , and E13 and the insulating layer 12 included in the display device DSP.

[0032] A lower electrode (first lower electrode) E11 is disposed in sub-pixel SP1. A lower electrode (second lower electrode) E12 is disposed in sub-pixel SP2. A lower electrode E13 is disposed in sub-pixel SP3. Lower electrodes E11 to E13 are arranged along a first direction X. The lower electrodes, including lower electrodes E11 to E13, are disposed for each sub-pixel or each display element and are sometimes referred to as pixel electrodes, anodes, etc.

[0033] The insulating layer 12 is formed in a lattice pattern when viewed from above. The insulating layer 12 is formed to partition the display elements or sub-pixels and is sometimes referred to as a rib or partition wall. The insulating layer 12 has a first opening OP1 that overlaps with the lower electrode E11, a second opening OP2 that overlaps with the lower electrode E12, and a third opening OP3 that overlaps with the lower electrode E13. The insulating layer 12 covers the periphery of each of the lower electrodes E11 to E13, with the center of each of the lower electrodes E11 to E13 exposed from the insulating layer 12 at the first opening OP1, the second opening OP2, and the third opening OP3.

[0034] In addition, the insulating layer 12 includes trenches T11, T12, T13, and T14 extending along the second direction Y and aligned along the first direction X, and trenches T21 and T22 extending along the first direction X and aligned along the second direction Y. Trench (first trench) T12 is located between the first opening OP1 and the second opening OP2. Trench T13 is located between the second opening OP2 and the third opening OP3. Trench T11 is located on the opposite side of trench T12 across the first opening OP1. Trench T14 is located on the opposite side of trench T13 across the third opening OP3. Trench T21 is connected to trenches T11 to T14. Trench T22 is connected to trenches T11 to T14. Trench T21 is located on the opposite side of trench T22 across the first opening OP1, the second opening OP2, and the third opening OP3.

[0035] Each trench does not overlap with adjacent lower electrodes when viewed from above. Lower electrode E11 is located between trenches T11 and T12, lower electrode E12 is located between trenches T12 and T13, and lower electrode E13 is located between trenches T13 and T14. Furthermore, lower electrodes E11 to E13 are located between trenches T21 and T22.

[0036] Here, the external shape of the sub-pixel corresponds to, for example, the external shape of the lower electrode. Specifically, the sub-pixel SP1, sub-pixel SP2, and sub-pixel SP3 that constitute a pixel PX are each formed into a substantially rectangular shape extending along the second direction Y and arranged along the first direction X. Adjacent sub-pixels arranged along the first direction X emit different colors. Furthermore, the areas of the sub-pixels SP1, SP2, and SP3 may be the same or different, as described below. Furthermore, the external shape of the sub-pixels may be determined by the external shape of the light-emitting area of ​​the display element.

[0037] Figure 3 It is along Figure 2 The cross-sectional view of the display device DSP is shown along line AA'.

[0038] The display device DSP includes a substrate 10, switching elements SW1 and SW2, an insulating layer 11, lower electrodes E11 and E12, an insulating layer 12, an organic layer OR, and an upper electrode E2. Furthermore, the display element 20A is composed of the lower electrode E11, the first portion OR1 of the organic layer OR, and the upper electrode E2. The display element 20B is composed of the lower electrode E12, the second portion OR2 of the organic layer OR, and the upper electrode E2.

[0039] The switching elements SW1 and SW2 are arranged on the substrate 10. The switching elements SW1 and SW2 correspond to, for example, Figure 1The driving transistor 3 is shown. The insulating layer (first insulating layer) 11 is arranged on the substrate 10 to cover the switching elements SW1 and SW2. The insulating layer 11 corresponds to the base layer of the display elements 20A and 20B, for example, an organic insulating layer. Figure 1 The pixel switch 2 and other components of the pixel circuit 1 are arranged on a substrate 10 and covered with an insulating layer 11 , but are not shown in the figure.

[0040] Lower electrodes E11 and E12 are disposed on insulating layer 11. Lower electrode E11 is electrically connected to switching element SW1 via contact hole CH1 formed in insulating layer 11. Lower electrode E12 is electrically connected to switching element SW2 via contact hole CH2 formed in insulating layer 11.

[0041] The lower electrodes E11 and E12 are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the lower electrodes E11 and E12 may be metal electrodes formed of a metal material such as silver or aluminum. Furthermore, the lower electrodes E11 and E12 may be a stack of transparent electrodes and metal electrodes. For example, the lower electrodes E11 and E12 may be a stack of a transparent electrode, a metal electrode, and a transparent electrode stacked in this order, or may be a stack of three or more layers.

[0042] The insulating layer (second insulating layer) 12 is arranged on the insulating layer 11 and covers the peripheral portions of each of the lower electrodes E11 and E12. The insulating layer 12 is, for example, an organic insulating layer. The insulating layer 12 has the above-mentioned first opening OP1, second opening OP2, trench T12, first surface SF1, and second surface SF2. The first opening OP1 penetrates the insulating layer 12 to the lower electrode E11. The second opening OP2 penetrates the insulating layer 12 to the lower electrode E12. The first surface SF1 is located between the trench T12 and the first opening OP1. The second surface SF2 is located between the trench T12 and the second opening OP2. In addition, the insulating layer 12 has a thickness TH. In the example shown in the figure, the thickness TH corresponds to the distance between the highest point of the insulating layer 12 and the insulating layer 11, and is, for example, 1.5 μm to 2.0 μm.

[0043] Trench T12 includes a bottom surface BS, a first side surface SS1 rising from bottom surface BS, and a second side surface SS2. First side surface SS1 and second side surface SS2 are spaced apart and opposed to each other in the first direction X. First side surface SS1 is connected to first surface SF1. Second side surface SS2 is connected to second surface SF2. Trench T12 corresponds to the space enclosed by first side surface SS1, second side surface SS2, and bottom surface BS. Trench T12 has a depth D. Depth D is, for example, 0.5 μm to 1.0 μm.

[0044] Trench T12 has a spacing GP1 between first side surface SS1 and second side surface SS2 at its upper portion UP, and a spacing GP2 between first side surface SS1 and second side surface SS2 at its bottom surface BS. Spacing GP1 is smaller than spacing GP2. That is, trench T12 is formed so that its width along the first direction X decreases as it approaches upper portion UP from bottom surface BS. In other words, first side surface SS1 is inclined relative to the normal direction of bottom surface BS so as to overlap with bottom surface BS. Similarly, second side surface SS2 is inclined relative to the normal direction of bottom surface BS so as to overlap with bottom surface BS.

[0045] The organic layer OR has a first portion OR1 , a second portion OR2 , and a third portion OR3 .

[0046] The first portion OR1 covers the lower electrode E11 located in the first opening OP1 and the first surface SF1 .

[0047] The second portion OR2 covers the lower electrode E12 located in the second opening OP2 and the second surface SF2. The third portion OR3 is located at the bottom surface BS of the trench T12. The third portion OR3 is separated from the first portion OR1 and the second portion OR2. As described later, the organic layer OR includes a light-emitting layer EL. The first portion OR1, the second portion OR2, and the third portion OR3 include light-emitting layers EL of the same color. In addition to the light-emitting layer EL, the organic layer OR also includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

[0048] The upper electrode E2 covers the organic layer OR. That is, the upper electrode E2 covers the first portion OR1, the second portion OR2, and the third portion OR3 respectively. The upper electrode E2 covers the third portion OR3 inside the groove T12 and is in contact with the bottom surface BS. In addition, the upper electrode E2 is in contact with the first side surface SS1 and the second side surface SS2 inside the groove T12. The upper electrode E2 is a transparent electrode formed of a transparent conductive material such as ITO or IZO. The upper electrode E2 is located at Figure 1 The upper electrode E2 is electrically connected to the power supply line FL in the display area DA shown. The upper electrode E2 is an electrode commonly provided for multiple sub-pixels or multiple display elements and is sometimes referred to as a common electrode, counter electrode, cathode, etc. The upper electrode E2 may also be covered by a transparent protective layer (including at least one of an inorganic insulating layer and an organic insulating layer).

[0049] In display element 20A, the first portion OR1 is located between the lower electrode E11 and the upper electrode E2, thereby forming a light-emitting region. In display element 20B, the second portion OR2 is located between the lower electrode E12 and the upper electrode E2, thereby forming a light-emitting region. Furthermore, the third portion OR3 is located between the insulating layer 12 and the upper electrode E2, completely separated from the first and second portions OR1 and OR2, and therefore does not emit light. Furthermore, the area of ​​the first portion OR1 that covers the first surface SF1 is located between the insulating layer 12 and the upper electrode E2, thereby emitting almost no light. Similarly, the area of ​​the second portion OR2 that covers the second surface SF2 is located between the insulating layer 12 and the upper electrode E2, thereby emitting almost no light.

[0050] The organic layer OR is formed by, for example, vacuum evaporation. In the figure, the dot-dashed line indicates that the organic material for forming the organic layer OR is released from the evaporation source.

[0051] After forming the insulating layer 12 having the first opening OP1, the second opening OP2, and the trench T12, an organic material for forming the organic layer OR is evaporated. The first side surface SS1 is inclined so as to overlap with the bottom surface BS, so that the organic layer OR is hardly formed on the first side surface SS1. Thus, the organic layer OR is separately formed into a first portion OR1 and a third portion OR3. Similarly, the second side surface SS2 is inclined so as to overlap with the bottom surface BS, so that the organic layer OR is hardly formed on the second side surface SS2. Thus, the organic layer OR is separately formed into a second portion OR2 and a third portion OR3. In addition, the organic layer OR is hardly formed in the area of ​​the bottom surface BS that overlaps with the first side surface SS1 and the second side surface SS2 in the third direction Z. In addition, the upper electrode E2 is formed by sputtering, and is thus continuously formed on the bottom surface BS, the first side surface SS1, and the second side surface SS2 above the organic layer OR.

[0052] According to this embodiment, the insulating layer 12 has a groove T12. Furthermore, the groove T12 is formed so that its width along the first direction X decreases as it moves from the bottom surface BS toward the upper portion UP. Therefore, the organic layer OR can be separated and formed in the groove T12 into a first portion OR1 located in the sub-pixel SP1 and a second portion OR2 located in the sub-pixel SP2. In other words, by performing full-surface vapor deposition without using a mask, the organic layer OR can be formed separately for each sub-pixel. This can suppress crosstalk between adjacent sub-pixels. Furthermore, since no additional components are required to separate the organic layer OR, manufacturing costs can be reduced.

[0053] In addition, the distance between the first side surface SS1 and the second side surface SS2 can also be referred to as the width of the trench T12. Figure 3In the example shown, the first side surface SS1, the second side surface SS2, and the bottom surface BS are all flat surfaces, but they may also be curved surfaces. When the first side surface SS1, the second side surface SS2, and the bottom surface BS are flat surfaces, the maximum width of the trench T12 is equivalent to the width of the bottom surface BS. However, when the first side surface SS1, the second side surface SS2, and the bottom surface BS include curved surfaces, the maximum width of the trench T12 is not necessarily equivalent to the width of the bottom surface BS. In some cases, the width of the trench T12 is greatest above the bottom surface BS. In this case, for example, the width of the trench T12 is greatest at a position less than half, or more preferably less than one-third, of the height of the trench T12.

[0054] Furthermore, when the potential of the lower electrodes E11 and E12 is relatively higher than that of the upper electrode E2, the lower electrodes E11 and E12 function as anodes, and the upper electrode E2 functions as a cathode. When the potential of the upper electrode E2 is relatively higher than that of the lower electrodes E11 and E12, the upper electrode E2 functions as an anode, and the lower electrodes E11 and E12 function as a cathode.

[0055] Furthermore, for example, an organic layer OR including a light-emitting layer EL of the same color is disposed on all sub-pixels SP in the display area DA. When each display element emits white light, multi-color display can be achieved by disposing a color filter opposite the display element. Furthermore, when each display element emits ultraviolet light, multi-color display can be achieved by disposing a light conversion layer opposite the display element.

[0056] Figure 4 It is a cross-sectional view showing the trench T12 , the organic layer OR, and the like.

[0057] The organic layer OR includes a stacked first layer L1, a second layer L2, and a third layer L3. Specifically, the first portion OR1, the second portion OR2, and the third portion OR3 include the stacked first layer L1, the second layer L2, and the third layer L3, respectively. As described above, the organic layer OR includes a light-emitting layer EL. For example, the light-emitting layer EL is any one of the first layer L1, the second layer L2, and the third layer L3.

[0058] The first portion OR1 is connected to the first side surface SS1. On the first side surface SS1, the end EG11 of the first layer L1 is covered by the second layer L2, and the end EG21 of the second layer L2 is covered by the third layer L3. The second portion OR2 is connected to the second side surface SS2. On the second side surface SS2, the end EG12 of the first layer L1 is covered by the second layer L2, and the end EG22 of the second layer L2 is covered by the third layer L3.

[0059] In this embodiment, the first side surface SS1 and the second side surface SS2 are each tilted to overlap with the bottom surface BS. Therefore, the second layer L2 is deposited so that the first layer L1 is covered, and the third layer L3 is deposited so that the first layer L1 and the second layer L2 are covered. This prevents the first layer L1 and the second layer L2 from being exposed from the third layer L3, and prevents the upper electrode E2 from contacting the first layer L1 and the second layer L2. This also suppresses current leakage from the first layer L1 and the second layer L2 to the upper electrode E2, thereby preventing degradation in the performance of the display element.

[0060] For example, the first layer L1 and the third layer L3 are functional layers, and the second layer L2 is the light-emitting layer EL. The first layer L1 and the third layer L3 may be, for example, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, or an electron blocking layer, but may also be other functional layers. Furthermore, each of the first layer L1 and the third layer L3 is not limited to a single layer and may be a laminate formed by stacking multiple functional layers. Furthermore, at least one of the first layer L1 and the third layer L3 may be omitted.

[0061] As an example, when the lower electrode is equivalent to the anode, the first layer L1 between the light-emitting layer EL and the lower electrode includes at least one of a hole injection layer and a hole transport layer, and the third layer L3 between the light-emitting layer EL and the upper electrode E2 includes at least one of an electron transport layer and an electron injection layer.

[0062] Figure 5 is a top view showing the organic layer OR. Figure 5 In FIG. 1 , the region where the organic layer OR is arranged is indicated by oblique lines.

[0063] The first portion OR1 is disposed in the sub-pixel SP1 , and the second portion OR2 is disposed in the sub-pixel SP2 . The first portion OR1 and the second portion OR2 are arranged along the first direction X.

[0064] The third portion OR3 is formed in a lattice pattern when viewed from above. The third portion OR3 includes portions OR31, OR32, and OR33 extending along the second direction Y and arranged along the first direction X, and portions OR34 and OR35 extending along the first direction X and arranged along the second direction Y. Portion OR32 is located between the first portion OR1 and the second portion OR2. Portion OR31 is located on the opposite side of portion OR32 across from the first portion OR1. Portion OR33 is located on the opposite side of portion OR32 across from the second portion OR2. Portion OR34 is connected to portions OR31 to OR33. Portion OR35 is connected to portions OR31 to OR33. Portion OR34 is located on the opposite side of portion OR35 across from the first portion OR1 and the second portion OR2.

[0065] Portions OR31 to OR33 are located in trenches T11 to T13, respectively. Portions OR34 and OR35 are located in trenches T21 and T22, respectively.

[0066] The outer shape of the first portion OR1 is formed to be larger than the outer shape of the lower electrode E11 in a plan view. The outer shape of the second portion OR2 is formed to be larger than the outer shape of the lower electrode E12 in a plan view.

[0067] Figure 6 It is along Figure 1 The cross-sectional view of the display device DSP is shown along line BB'.

[0068] The peripheral electrode 6 and the power line 52 are located on the insulating layer 11. The insulating layer 12 covers the peripheral electrode 6 and the power line 52. The organic layer OR is not formed in the non-display area NDA. The upper electrode E2 covers the insulating layer 12 in the non-display area NDA and is connected to the peripheral electrode 6 via a contact hole CH3 formed in the insulating layer 12. In the illustrated example, the peripheral electrode 6 and the power line 52 are located on the same layer as the lower electrode E10, but they may also be located on a different layer from the lower electrode E10.

[0069] Figure 7 It is a cross-sectional view showing a first modified example of this embodiment. Figure 7 The composition shown is Figure 3 The structure shown is different in that the trench T12 penetrates the insulating layer 12 and reaches the insulating layer 11 .

[0070] In the example shown in the figure, the bottom surface BS corresponds to the upper surface of the insulating layer 11. Therefore, the third portion OR3 and the upper electrode E2 are in contact with the insulating layer 11 in the trench T12.

[0071] In this first modification as well, the same effects as described above can be obtained.

[0072] Figure 8 It is a plan view showing a second modified example of the present embodiment. Figure 8 The composition shown is Figure 2 Compared with the illustrated configurations, the layouts of the sub-pixels SP1 , SP2 , and SP3 are different.

[0073] The lower electrodes E11 and E12 are arranged along the second direction Y. The lower electrode E13 is arranged along the first direction X of the lower electrodes E11 and E12.

[0074] The insulating layer 12 includes trenches T15, T16, and T17 extending along the second direction Y and aligned along the first direction X, and trenches T23, T24, and T25 extending along the first direction X and aligned along the second direction Y. Trench T16 is located between the first opening OP1, the second opening OP2, and the third opening OP3. Trench T15 is located on the opposite side of trench T16 across the first opening OP1 and the second opening OP2. Trench T17 is located on the opposite side of trench T16 across the third opening OP3. Trench T23 is connected to trenches T15 to T17. Trench T24 is connected to trenches T15 and T16. Trench T25 is connected to trenches T15 to T17. Trench T23 is located on the opposite side of trench T25 across the first opening OP1, the second opening OP2, and the third opening OP3. The trench T24 is located between the first opening OP1 and the second opening OP2 .

[0075] Each trench does not overlap with an adjacent lower electrode when viewed from above. In the first direction X, lower electrodes E11 and E12 are located between trenches T15 and T16, and lower electrode E13 is located between trenches T16 and T17. Furthermore, in the second direction Y, lower electrode E11 is located between trenches T23 and T24, lower electrode E12 is located between trenches T24 and T25, and lower electrode E13 is located between trenches T23 and T25.

[0076] Sub-pixels SP1 and SP2 are arranged along the second direction Y, sub-pixels SP1 and SP3 are arranged along the first direction X, and sub-pixels SP2 and SP3 are arranged along the first direction X. Sub-pixel SP1 is formed into a substantially rectangular shape extending along the first direction X, and sub-pixels SP2 and SP3 are formed into substantially rectangular shapes extending along the second direction Y. Sub-pixels SP1 to SP3 emit different luminous colors. Furthermore, sub-pixels SP1 to SP3 have different areas. Sub-pixel SP2 has a larger area than sub-pixel SP1, and sub-pixel SP3 has a larger area than sub-pixel SP2. Alternatively, the area of ​​sub-pixel SP1 may be the same as the area of ​​sub-pixel SP2.

[0077] In this second modification, the same effects as described above can also be obtained.

[0078] Figure 9 It is a plan view showing a third modified example of the present embodiment. Figure 9 The composition shown is Figure 2 Compared with the illustrated configurations, the layouts of the sub-pixels SP1 , SP2 , and SP3 are different. Figure 9 The direction DR1 shown is tilted counterclockwise at an angle θ1 relative to the second direction Y. Figure 9 The direction DR2 shown is inclined clockwise relative to the second direction Y at an angle θ2.

[0079] The insulating layer 12 has a plurality of trenches T1 extending in direction DR1 and arranged in direction DR2, and a plurality of trenches T2 extending in direction DR2 and arranged in direction DR1. The plurality of lower electrodes E11 and the plurality of first openings OP1 are located in the plurality of red sub-pixels SP1. The plurality of lower electrodes E12 and the plurality of second openings OP2 are located in the plurality of green sub-pixels SP2. The plurality of lower electrodes E13 and the plurality of third openings OP3 are located in the plurality of blue sub-pixels SP3.

[0080] The plurality of lower electrodes E11 and E12 are alternately arranged along the direction DR1 between two adjacent trenches T1. Furthermore, the plurality of lower electrodes E12 and E13 are alternately arranged along the direction DR1 between two adjacent trenches T1. The plurality of lower electrodes E11 and E12 are alternately arranged along the direction DR2 between two adjacent trenches T2. Furthermore, the plurality of lower electrodes E12 and E13 are alternately arranged along the direction DR2 between two adjacent trenches T2. Each trench T1 and T2 does not overlap with an adjacent lower electrode when viewed from above.

[0081] Sub-pixels SP1 and SP3 are formed into a generally square shape. Some sub-pixels SP2 are formed into a generally rectangular shape extending in direction DR1, while other sub-pixels SP2 are formed into a generally rectangular shape extending in direction DR2. Furthermore, the areas of sub-pixels SP1 to SP3 differ from one another. The area of ​​sub-pixel SP3 is larger than that of sub-pixel SP1, and the area of ​​sub-pixel SP1 is larger than that of sub-pixel SP2.

[0082] In this third modification, the same effects as described above can also be obtained.

[0083] As described above, according to this embodiment, a display device capable of suppressing a decrease in display quality can be obtained.

[0084] In addition, although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A display device comprising: substrate; A first insulating layer is disposed on the substrate; A first lower electrode and a second lower electrode are disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, comprising a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a first trench located between the first opening and the second opening; an organic layer comprising a light-emitting layer; and an upper electrode covering the organic layer, The first groove has a bottom surface and a first side surface and a second side surface rising from the bottom surface. The distance between the first side surface and the second side surface in the upper portion of the first groove is smaller than the distance between the first side surface and the second side surface in the bottom surface of the first groove. The organic layer has: a first portion covering the first lower electrode located in the first opening and covering the first surface of the second insulating layer located between the first trench and the first opening; a second portion covering the second lower electrode located in the second opening and covering the second surface of the second insulating layer located between the first trench and the second opening; as well as a third portion, disposed on the bottom surface of the first groove and separated from the first portion and the second portion; The first portion includes a first layer, a second layer, and a third layer stacked together, and end surfaces of the first layer, the second layer, and the third layer are in contact with the first side surface. The end of the first layer is covered by the second layer on the first side, The end of the second layer is covered by the third layer on the first side, The light-emitting layer is any one of the first layer, the second layer, and the third layer.

2. The display device according to claim 1, The first portion, the second portion, and the third portion include the light-emitting layer of the same color.

3. The display device according to claim 1, The upper electrode covers the third portion inside the first trench and is in contact with the first side surface and the second side surface.

4. The display device according to claim 1, The second insulating layer further comprises: a second groove located on an opposite side of the first groove across the first opening; and The third groove and the fourth groove are connected to the first groove and the second groove respectively. The third trench is located on the opposite side of the fourth trench across the first opening.

5. The display device according to claim 1, The display device includes a display area for displaying an image and a non-display area surrounding the display area. The display device comprises: a power line located in the non-display area; and The peripheral electrode is located in the non-display area and is electrically connected to the power line. The second insulating layer covers the peripheral electrode, The upper electrode is connected to the peripheral electrode in the non-display region via a contact hole formed in the second insulating layer.

6. The display device according to claim 1, The organic layer further includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

7. The display device according to claim 1, The first trench passes through the second insulating layer and extends to the first insulating layer.

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