Linear DAC modified by input code

Abstract

The present disclosure relates to a DAC circuit for outputting a voltage, comprising a plurality of current providing devices connected so that the output current of each current providing device is half the output current of a subsequent current providing device; a plurality of first switching devices connected to each current providing device, respectively, wherein each first switching device is used to transfer each current to a first path or a second path based on a control signal; a control device connected to the plurality of first switching devices and used to: receive a binary input signal, the binary input signal comprising a plurality of bits ranging from an MSB to an LSB, each bit being associated with a switching device in the plurality of first switching devices; receive an error associated with the MSB; modify the binary input signal when the MSB is set to 1 to generate a control signal based on the binary input signal and the error associated with the MSB, so that the current transferred by at least one first switching device compensates for the error associated with the MSB; and the output voltage is generated based on the currents of the first path and the second path.

Description

[0001] This application claims priority from European patent application number EP21216106.1 filed with the European Patent Office on December 20, 2021, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to a digital-to-analog converter (DAC) circuit. Background Art

[0003] Over the past decade, smartphone cameras have evolved rapidly, becoming increasingly compact while improving quality and resolution. The movement of the lens allows the image to be focused, zoomed, and stabilized. Auto-focus (AF) has now become an essential function. The AF driver typically applies direct current (DC) to a so-called voice coil motor (VCM). The VCM is driven in response to a voltage that is typically regulated by a digital-to-analog converter (DAC) circuit, and the resolution of the DAC circuit gives the granularity of the lens position. Typically, the resolution of a DAC circuit is given by the number of bits N and indicates the smallest increment of output that the DAC circuit can produce.

[0004] It is known (e.g., WO2011081966A2) that in an R-2R ladder DAC circuit, which includes a single resistor rung for each bit of a digital input signal, the successive resistor rungs are of decreasing size from the most significant bit (MSB) to the least significant bit (LSB). Therefore, the area of ​​the R-2R ladder DAC circuit can be reduced based on the significant reduction in the physical size of the resistors due to the size reduction. When more resistor rungs (bits) are added to an already R-2R ladder DAC circuit, the newly added resistor rungs increase the error that is corrected by adding more electrical components as current sources. These additional electrical components increase the physical size of the DAC circuit. Summary of the Invention

[0005] According to the present invention, a DAC circuit for outputting a voltage is provided, comprising: a plurality of current supply devices connected such that the output current of each current supply device is half the output current of a subsequent current supply device; a plurality of first switching devices connected to each current supply device; each first switching device configured to divert each current to a first path or a second path based on a control signal; and a control device connected to the plurality of first switching devices and configured to: receive a binary input signal comprising a plurality of bits ranging from a most significant bit (MSB) to a least significant bit (LSB), wherein each bit is associated with a switch device in the plurality of first switching devices; receive an error associated with the MSB; and, when the MSB is set to 1, modify the binary input signal to generate a control signal based on the binary input signal and the error associated with the MSB such that the current diverted by at least one first switching device compensates for the error associated with the MSB; wherein an output voltage is generated based on the currents of the first and second paths. By controlling the switching devices, errors can be effectively compensated. This arrangement is believed to be more versatile in minimizing the required size of the DAC circuit while increasing resolution. As a result, the increase in resolution does not require an increase in the size of the DAC circuit for compensating for errors, thereby reducing the cost of such a DAC circuit.

[0006] In one example of the present disclosure, the control device compensates for the error associated with the MSB by controlling at least one first switching device among the plurality of first switching devices, wherein the at least one first switching device provides a current corresponding to the binary input signal and the error associated with the MSB.

[0007] In one example of the present disclosure, the plurality of current providing devices are a plurality of shunts connected such that an output current from each shunt is an input current of a subsequent shunt.

[0008] In one example of the present disclosure, the control device is connected to a plurality of current sources and corresponding second switching devices, and the control device is further configured to control the second switching devices so that the currents generated by the plurality of current sources compensate for the error associated with the MSB. Optionally, each current source in the plurality of current sources generates a current equivalent to the current provided by the shunt corresponding to the LSB.

[0009] In one example of the present disclosure, the control device is further used to: receive an error associated with the next MSB; and further generate a control signal based on the error associated with the next MSB, so that when the next MSB is set to 1, current is transmitted by the multiple shunts that compensate for the error associated with the next MSB.

[0010] In one example of the present disclosure, the control device is configured to reduce the current provided by the shunt corresponding to the MSB. Alternatively, the control device may be configured to reduce the current provided by the shunt corresponding to the next MSB. By reducing the current, it is ensured that the current can be corrected by increasing the current corresponding to the error.

[0011] In one example of the present disclosure, the plurality of current supply devices and switching devices form an R-2R ladder. By using the R-2R ladder, the DAC circuit is easier to accurately construct because only two types of resistors are required, and the number of bits can be expanded by adding segments of the same type of resistor.

[0012] In one example of the present disclosure, the multiple current providing devices are: multiple current sources, so that the current of the current source is twice the current of the continuous current source; and a shunt for dividing the input current into a first output current and a second output current, wherein the first output current is twice the second output current, and the second output current is twice the current of the first current source among the multiple current sources.

[0013] In one example of the present disclosure, the error is a multiple of a current delivered to a switching device corresponding to the LSB.

[0014] In one example of the present disclosure, the error associated with the MSB is stored in non-volatile memory. Optionally, the error associated with the next MSB is stored in the non-volatile memory. Storing the error in such memory ensures that the error value is available even after power is turned off. Therefore, there is no need to store the error value every time power is turned off, saving time and eliminating the need to enter the value each time the DAC circuit is used.

[0015] In one example of the present disclosure, the first path and the second path are connected to an operational amplifier (OPAMP) for outputting an output current.

[0016] In one example of the present disclosure, a voice coil motor (VCM) is provided, wherein the VCM includes a DAC circuit, such that the VCM is configured to be controllable by an output current of the DAC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will now be described in more detail with reference to preferred embodiments shown in the accompanying drawings, in which:

[0018] Figure 1 shows a block diagram of the DAC circuit.

[0019] Figure 2 A DAC circuit implemented by an R-2R ladder architecture for 10 bits is shown.

[0020] Figure 3 A DAC circuit implemented by an R-2R ladder architecture for 12 bits is shown.

[0021] Figure 4 The MSB and MSB-1 transition errors and DNL errors are shown for all conversions.

[0022] Figure 5A and Figure 5B The dynamic nonlinearity (DNL) errors for the MSB transition and the MSB-1 transition are shown.

[0023] Figure 6A and Figure 6B The DNL error of the MSB transition is shown when the DNL error of the MSB-1 transition has been corrected.

[0024] Figure 7A and Figure 7B The MSB transition and the MSB-1 transition are shown when their DNL errors are both corrected.

[0025] Figure 8 Another DAC circuit implemented by an R-2R ladder architecture is shown.

[0026] Figure 9 A DAC circuit implemented by a binary-weighted current architecture is shown.

[0027] Figure 10 A diagram illustrating a method (1000) for a digital-to-analog converter (DAC) circuit (10) for outputting a voltage. DETAILED DESCRIPTION

[0028] Aspects of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments of the disclosure are shown.

[0029] A digital-to-analog converter (DAC) circuit is used to convert digital data into an analog signal. There are several architectures for digital-to-analog conversion. Figures 2 to 3 as well as Figure 8 shows the R-2R ladder network architecture, Figure 9 A binary weighted current architecture is shown. Although the present disclosure will be described with reference to these two architectures, those skilled in the art will appreciate that other architectures may be used. Furthermore, although the DAC circuit is described with respect to Figures 2 to 8Examples are shown, but the present disclosure is intended to be implemented in analog-to-digital converter (ADC) circuits, coder-decoder (CODEC) circuits, radio-frequency (RF) circuits, power amplifier circuits, voltage regulator circuits, and the like.

[0030] Figure 1 A block diagram of a DAC circuit 10 for outputting a voltage is shown. The DAC circuit 10 includes a plurality of current supply devices 11, a plurality of first switching devices 30, and a control device 12. The plurality of current supply devices 11 are connected such that the output current of each current supply device is half the output current of the subsequent current supply device. A plurality of first switching devices 30 are connected to each current supply device. Each first switching device is configured to divert each current to a first path or a second path based on a control signal. The control device 12 is connected to the plurality of first switching devices. The control device 12 is configured to receive a binary input signal comprising a plurality of bits ranging from a most significant bit (MSB) to a least significant bit (LSB), wherein each bit is associated with a switching device in the plurality of first switching devices; receive an error associated with the MSB; and, when the MSB is set to 1, modify the binary input signal to generate a control signal based on the binary input signal and the error associated with the MSB, such that the current diverted by at least one first switching device 30 compensates for the error associated with the MSB. The output voltage is generated based on the currents in the first and second paths.

[0031] Figure 2 and Figure 3 DAC circuits implemented using an R-2R ladder architecture for 10-bit and 12-bit DACs, respectively. The DAC circuit 10 includes a plurality of shunts 20 and a plurality of first switching devices 30. The plurality of first switching devices 30 are connected to each shunt 20, respectively. Each first switching device 30 is configured to divert each second output current to either the first path 40 or the second path 50 based on a control signal.

[0032] Each shunt 20 receives an input current and outputs a first output current and a second output current. The multiple shunts 20 are connected such that the first output current from each shunt serves as the input current for the subsequent shunt. Each shunt 20 includes a node 21. Node 21 is connected to the node of the subsequent shunt via a first resistor 22 and to a first switching device 30 via a second resistor 23. The resistance of the first resistor 22 is R, and the resistance of the second resistor 23 is 2R. In other words, the resistance of the second resistor 23 is twice that of the first resistor 22. The node 21 of the first shunt in the multiple shunts is connected to a voltage source that generates a reference voltage Vref. The node 21 of the last shunt in the multiple shunts is connected to ground via a last second resistor 24. The resistance of the last second resistor 24 is the same as that of all other second resistors 23, that is, it also has a resistance of 2R. The value of R can be any value as long as the ratio R:2R is satisfied. For example, R can be 1 ohm and 2R can be 2 ohms. This ratio between the resistance values ​​of the first resistor 22 and the second resistor 23 is due to the fact that the equivalent resistance Req of the circuit, viewed from the right side of each first resistor 22, also has a resistance value of R. Due to the equivalent resistance Req having a resistance value of R, the plurality of shunts 20 are connected so as to continuously divide the input current by 2 into two equal output currents, i.e., the first output current (i.e., the current flowing through the first resistor 22) is equal to the second output current (i.e., the current flowing through the second resistor 23). Figure 2 As shown in the example, the current flowing through the first resistor 22 of the first shunt is I, the current flowing through the first resistor 22 of the second shunt is I / 2, the current flowing through the first resistor 22 of the third shunt is I / 4, and so on (I is an arbitrary current value).

[0033] The DAC circuit 10 includes a control device (not shown). The control device is configured to receive a binary input signal having N bits, where N is a positive integer. The total number of shunts is equal to N. The binary input signal is configured to store N bits ranging from the most significant bit (MSB) to the least significant bit (LSB). The MSB corresponds to the bit <n-1>(hereinafter referred to as b N-1 ), the least significant bit (LSB) corresponds to the bit <0> (hereinafter referred to as b0). The next most significant bit is hereinafter referred to as MSB-1, which can refer to the bit <n-2>(hereinafter referred to as b N-2 ).

[0034] The plurality of first switching devices 30 are configured to be controlled by a control device such that each first switching device is controlled based on a binary input signal such that each switching device diverts the second output current to either the first path 40 or the second path 50. For example, when the binary input signal is 1012 (sub-index 2 indicates that the number is a base-2 number), then b2 = 1, b1 = 0, and b0 = 1. The first switching devices corresponding to b2, b1, and b0 are controlled such that the second output current of the switching devices corresponding to b2 and b0 is diverted to the first path, while the second output current of the first switching device corresponding to b1 is diverted to the second path.

[0035] The DAC circuit 10 includes an operational amplifier (OPAMP) 60 for outputting an output voltage Vout. Each switching device 30 can be controlled to be connected to the (+) input terminal, i.e., the non-inverting input terminal, of the OPAMP via a first path 40, or to the (-) input terminal, i.e., the inverting input terminal, of the OPAMP via a second path 50. The output voltage Vout of the OPAMP 60 is Vout=Vref·(RF / 2R), where RF is the resistance of a feedback resistor 62 connected between the (-) input terminal and the output terminal of the amplifier 60. The resistance value of the feedback resistor 62 is R / 5. The output voltage Vout of the DAC only takes specific values, such as 2 of Vout. N possible voltage levels, where N is the number of bits in the binary input signal. Therefore, in this sense, it represents a digital value. However, by increasing the number of bits in the binary input signal, the number of different possible output levels can be increased, and the difference between consecutive values ​​can be reduced. This allows the generation of an analog output that varies continuously over a range of values. Each binary input signal contributes a different amount to the analog output. Starting from the LSB, the weight of each bit is successively doubled.

[0036] The resolution of a DAC circuit is defined as the smallest change that can occur in the analog output due to a change in the digital input. The resolution is always equal to the weight of the LSB. A DAC is monotonic if its output voltage (e.g., Vout) increases as the binary input signal increments from one value to the next.

[0037] Ideally, all first resistors 22 and all second resistors 23 have the same resistance value, R, and 2R, respectively. However, circuit manufacturing processes can cause slight variations in the resistance matching level (σ) of each first resistor 22 and second resistor 23 within a shunt 20 relative to the resistance matching levels of other shunts. Generally, the mismatch between resistors is inversely proportional to the square root of the resistor area. This variation in the resistance matching level of the resistors can cause differential nonlinearity (DNL) errors in the amplitude of the output voltage (Vout). Specifically, DNL error is the difference between the actual amplitude of the output voltage Vout and the ideal amplitude. To maintain sufficient resolution of the R-2R DAC circuit, it is desirable to keep the DNL error within a predetermined fraction (e.g., + / - 0.5) of the amplitude of one LSB. Generally, the DNL error of an R-2R DAC circuit is proportional to the resistor matching level. For example, by using a resistor matching level of 0.1%, 10-bit linearity is achieved, so the DNL error is kept within 1 LSB.

[0038] To increase the resolution of a 10-bit R-2R DAC circuit to a 12-bit R-2R DAC circuit, two more bits can be added. This increase in bits can be achieved by adding two R-2R sections. The R-2R section includes a shunt and a switching device (e.g., a first switching device). As a result, due to the 2-bit increment from 10 bits to 12 bits, the level of resistor matching between the resistors needs to increase by a factor of 4. Therefore, the 2-bit increment results in a 16-fold increase in area.

[0039] An MSB transition is one in which the MSB is set to 1 and all remaining bits are set to 0; an MSB-1 transition is one in which the next MSB is set to 1 and the MSB and all remaining lower bits are set to 0. This can be thought of as the switch corresponding to the MSB being activated when the MSB is set to 1 and deactivated when the MSB is set to 0. For example, for a 10-bit input signal, an MSB transition is a transition from 01111111112 to 10000000002, while an MSB-1 transition is a transition from 001111111112 to 01000000002. Sub-index 2 indicates that the number is represented in base 2. Similarly, sub-index 10 indicates that the number is represented in base 10. As previously mentioned, setting the MSB bit to 1 and the remaining bits to 0 should ideally result in an increase of 1 LSB. One LSB is the voltage value equal to the DAC output voltage when only the LSB is set to 1 and the remaining bits are set to 0. For example, when adding two R-2R sections to increase 10 bits to 12 bits, with the lower 10 bits having 10-bit accuracy, the first added bit (corresponding to the first R-2R section) can have a 2LSB error, while the second added bit can have a 4LSB error due to matching errors. The actual MSB and MSB-1 currents can be too low or too high, which will also result in a non-monotonic DAC at the MSB and MSB-1 transitions.

[0040] Figure 4 The left graph shows the MSB and MSB-1 conversion errors of a 12-bit DAC, and the right graph shows the DNL error of all conversions of the 12-bit DAC. The MSB and MSB-1 are shown for a random experiment with a resistor matching level (also called matching standard deviation) of σ = 0.001. In this experiment, both currents are too large, which will result in a non-monotonic DAC, such as Figure 4 As shown in the left figure, the output voltage (Vout) increases as the binary input increases. Figure 4 The right graph of Figure 1 shows the DNL error for all MSB transitions. The lowest transitions (MSB-2 transitions, ..., MSB-11) have lower DNL errors than the MSB and MSB-1 transitions. That is, the DNL errors for the MSB and MSB-1 transitions are greater than 1LSB, while the DNL errors for the MSB-2 transitions, ..., and MSB-11 are less than 1LSB. When the DNL error is between the minimum value (e.g., -1LSB) and the maximum value (e.g., 1LSB), the DNL error can be ignored because it cannot be corrected. When the DNL error is greater than the maximum value (e.g., 1LSB) or less than the minimum value (e.g., >-1LSB), the DNL error can be corrected.

[0041] Based on the binary input signal, a 12-bit DAC can have 2 12 (i.e., 4096) possible output voltages Vout, and each output voltage is 1LSB higher than the previous output voltage. This can be seen as a staircase wave, with each step increasing by 1LSB. Figure 5A and Figure 5B In the example, the MSB transition has a DNL error of +5LSB, while the MSB-1 transition has a DNL error of -10LSB. That is, when the 10 (0111111111112) converts to 2048 10 (1000000000002), which corresponds to the MSB transition, corresponding to 2048 10 The output voltage of (1000000000002) is 5 times the ideal value. In the case of MSB-1 conversion, Figure 5B As shown, when the 10 (0011111111112) converted to 1024 10 (0100000000002), there is an error of -10LSB, so it corresponds to 1024 10 The output voltage of (0100000000002) is 1 / 10 of the ideal value.

[0042] like Figure 6A and Figure 6B As shown in Figure 1, when the DNL error of the MSB-1 conversion is corrected, the MSB conversion has a DNL error of -5LSB. This is because the DNL error of the MSB conversion is affected by the DNL error of the MSB-1 conversion. Therefore, the DNL error of the MSB-1 conversion needs to be considered when correcting the MSB conversion.

[0043] exist Figure 7A and Figure 7B In this example, when the DNL errors for both the MSB transition and the MSB-1 transition are corrected, the DAC circuit's output voltage, Vout, exhibits an increasing linear trend relative to the binary input signal, indicating that the DAC circuit is monotonic. Therefore, when correcting the MSB-1, the output voltage is corrected based on the DNL error for the MSB-1 transition, and when correcting the MSB, the output voltage is corrected based on the DNL errors for both the MSB transition and the MSB-1 transition. In this example, the DNL errors for the MSB transition and the MSB-1 transition are +5 LSB and -10 LSB, respectively. However, this disclosure is intended to encompass and include any other values, as these values ​​depend on the circuit manufacturing process.

[0044] Back to Figure 3 , the DNL error of the lower 10 bits is within 1LSB, while the DNL error of the two added bits corresponding to the MSB and the next MSB is greater than 1LSB. The MSB increases the DNL by +4LSB, and the next MSB increases the DNL by +2LSB. To correct the error, the control device is connected to a plurality of current sources (70) and corresponding second switching devices, and is used to control the second switching devices so that the current generated by the plurality of current sources compensates for the error associated with the MSB. The DNL error is corrected by adding the current source 70 to compensate for the DNL error associated with the MSB and / or MSB-1. However, due to the components of the current source 70 and the second switching device, this increases the area.

[0045] The DNL errors for the MSB and MSB-1 are intentionally made smaller. For example, if the DNL error for the MSB conversion is 4LSB and the DNL error for the MSB-1 conversion is 2LSB, the voltage of the MSB is at least 4LSB smaller, and the voltage of the MSB-1 is at least 2LSB smaller. Because the MSB and MSB-1 values ​​are made smaller, they can be corrected by adding the DNL errors in the digital domain. If the current is larger, it cannot be corrected by subtracting the current, as this would cause the MSB to transition. In this case, the current needs to be added for all less significant bits, which makes it less elegant and more complex.

[0046] During industrial testing of DAC circuits, the DNL errors for the MSB and MSB-1 transitions are measured and stored in memory as multiples of the LSB. By storing the DNL errors as multiples of the LSB, it is known how many times the output voltage corresponding to the MSB is higher or lower than the ideal 1 LSB. Thus, a control device can easily control at least one of the plurality of first switching devices to provide a current corresponding to the binary input signal and the error associated with the MSB. For example, if the input signal is 101012 (i.e., b4 = 1, b3 = 1, b2 = 0, b1 = 0, and b0 = 1) and the DNL error associated with the MSB is -3 LSB, the control device controls the first switching device to 110002 (101012 + 112 = 110002). The memory is typically nonvolatile memory. This type of memory retains stored data even after power is removed. Examples of nonvolatile memories are nonvolatile random-access memory (RAM), read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and the like.

[0047] In the present invention, correction is performed by binary signal (or code) correction, which increases the LSB value by a factor equal to the DNL. This allows increasing the number of R-2R sections from two to ten, all with the same dimensions, without increasing the area and without having to calibrate individual resistors.

[0048] The correction process can be performed by hardware or firmware using a code stream such as the one shown below. When the DNL of MSB-1 is, for example, -2LSB, -2 will be stored in memory associated with the MSB-1 error. When binary codes are introduced into the stream, the error will increase when MSB-1 is set to "1". For example, the binary signal is 1023 10 , the binary signal sent to the DAC is 1023 10 , but when the binary signal is 1024 10 When the binary signal sent to the DAC is 1024 10 +2 10 =1026 10 This means that 2 10 Need to be in 1024 10 and 2047 10 Add between, but also need to 3072 10 and 4095 10 In principle, MSB-1 correction = -1×DNL MSB-1 and MSB correction = -1×(DNL MSB -1+DNL MSB ), where DNL MSB-1 is the DNL error of MSB-1, DNL MSB is the DNL error of the MSB. That is, the error correction is equal to the DNL error but has the opposite sign. If the DNL error is positive, the error correction is negative, and vice versa.

[0049] Flow code:

[0050] 1.Retrieve OTP value of MSB and MSB-1, being DNLMSB and DNLMSB-1

[0051] 2. Loop

[0052] 3.Get InputCode;

[0053] 4.If InputCode<1024OutputCode=InputCode;

[0054] 5.If 1023 <InputCode<2048OutputCode=InputCode–DNL MSB-1 ;

[0055] 6.If InputCode>2047OutputCode=InputCode-DNL MSB-1 –DNL MSB ;

[0056] 7.If InputCode>3071OutputCode=InputCode-2*DNL MSB-1 –DNL MSB 8.WriteOutputCode to DAC

[0057] 9.End Loop

[0058] When the stream code is on line 5, MSB-1 is set to '1', so it is active (or on), when the stream code is on line 6, MSB is set to '1', so it is active (or on), and when the stream code is on line 7, MSB and MSB-1 are set to '1', so both are active (or on).

[0059] This flow can be used for digital hardware implementation when there is no processor on board, or for firmware implementation when the DAC is directly coupled to a processor.

[0060] Figure 8 Another DAC circuit is shown that includes a control device (not shown). The control device is connected to a plurality of first switching devices 30. The plurality of first switching devices (30) are configured to divert each current to a first path (40) or a second path (50) based on a control signal generated by the control device. A decrease in current 80 indicates that the current (or voltage) flowing through the first switching device 30 associated with the MSB has decreased by at least 4 LSBs, while a decrease in current 82 indicates that the current (or voltage) flowing through the first switching device 30 associated with MSB-1 has decreased by at least 2 LSBs. By reducing the current, a DNL error of the MSB and / or MSB-1 can be corrected. The control device is configured to compensate for the error associated with the MSB by modifying a binary input signal to generate a control signal that controls a current provided by at least one first switching device of the plurality of first switching devices that corresponds to the binary input signal and the error associated with the MSB. During operation of the DAC circuit, a DNL error value stored in a memory is retrieved, and correction of the error associated with the MSB and / or MSB-1 can be performed by the control device. Examples of the control device are hardware, software, and firmware.

[0061] Although Figure 2 The examples shown in FIGS. 0 to 6 are described for a 10-bit R-2R DAC circuit to a 12-bit R-2R DAC circuit, but they are also intended for a general M-bit R-2R DAC circuit to an N-bit R-2R DAC circuit, where M < N, and where the N-M most significant bits (MSBs) are corrected by adding a value to the binary input signal, the value being based on the error of the M-bit conversion. For example, an 8-bit R-2R DAC circuit to a 12-bit R-2R DAC circuit adds 4 sections in this case. Generally, the increase from M bits to N bits can be done by adding N-M sections, and the value of each added section is 2 1 (1 - x1 LSB), 2 2 (1 - x2 LSB), ……, 2 (N-M) (1 - x (N-M) LSB). Here x n is a value >= 1 to ensure that the added section is not larger than 2 n but only one bit smaller, so as to correct the differential non-linearity (DNL) error.

[0062] The present invention can be used in any multi-bit DAC architecture. Similarly for the binary weighted DAC shown in FIG. 7. When the resolution is increased from 15 bits to 16 bits (M = 15, N = 16), a mismatched current source can be added, which has a value 2 1( (1 - 1 LSB) times larger than bit 15. In addition to using the LSB of the original DAC itself, a separate current source can be made to compensate for the error. These LSB current sources can be coupled to one-time programmable (OTP) without modifying the code. However, this increases the area.

[0063] Figure 9 FIG. 21 shows a 10-bit DAC circuit implemented by a binary weighted current architecture. The binary weighted resistor DAC uses an operational amplifier (OPAMP) to sum the binary weighted currents obtained from a reference voltage VRref via current scaling resistors. The DAC circuit 100 includes eight current sources 125, a shunt 120, ten first switching devices 130, and control means (not shown). Each first switching device 130 is respectively connected to each current source and the shunt. Each first switching device 130 is used to transfer each current to a first path 140 or a second path 150 based on a control signal. Each current source 125 generates a current such that the current of the current source is twice the current of the adjacent current source. That is, the current corresponding to bit b7 is twice the current corresponding to bit b6, the current corresponding to bit b6 is twice the current corresponding to bit b5, and so on.

[0064] The shunt 120 is used to split the input current into a first output current and a second output current. A first switching device 130 is connected to each output current of the shunt. The shunt 120 includes a first resistor 121 and a second resistor 122. The resistance of the first resistor 121 is R, and the resistance of the second resistor 122 is 2R. This arrangement of resistors results in the first output current being twice the second output current. The second output current corresponding to bit b8 is twice the current corresponding to bit b7.

[0065] The control device is connected to the plurality of first switching devices 130 and generates a control signal based on the binary input signal and the error associated with the MSB such that when the MSB is set to 1, a current is provided that compensates for the error associated with the MSB.

[0066] DAC circuit 100 includes an OPAMP 160. A first path 140 and a second path 150 are connected to OPAMP 160 to output an output current Vout. Each switching device 130 can be controlled to connect to the (+) input terminal, i.e., the non-inverting input terminal, of the OPAMP via first path 140, or to the (-) input terminal, i.e., the inverting input terminal, of the OPAMP via second path 150. The output voltage Vout of OPAMP 160 is Vout = Vref·(RF / 2R), where RF is the resistance of a feedback resistor 162 connected between the (-) input terminal and the output terminal of amplifier 160. The resistance value of feedback resistor 162 is R / 5.

[0067] The DNL errors for bit b9 (ie, MSB) and bit b8 (ie, MSB-1) are due to the mismatch between the current sources. During industrial testing of the DAC circuit, these DNL errors are measured and stored in memory.

[0068] Figure 1 、 Figure 2 、 Figure 3 、 Figure 8 and Figure 9 DAC circuits can be used in many applications. Many motor control applications require voltage control signals, and DACs are ideal for applications that can be driven by a processor or controller. For example, a voice coil motor (VCM) can be controlled using a DAC circuit's output current.

[0069] Figure 10 A method (1000) for a digital-to-analog converter (DAC) circuit (10) for outputting a voltage is shown, the DAC circuit comprising: a plurality of current providing devices (11) connected so that the output current of each current providing device is half the output current of the subsequent current providing device; and a plurality of first switching devices (30) connected to each current providing device, respectively; each first switching device being configured to divert each current to a first path (40) or a second path (50) based on a control signal. Step S101 of the method 1000 comprises: receiving a binary input signal comprising a plurality of bits ranging from a most significant bit (MSB) to a least significant bit (LSB), wherein each bit is associated with a switching device in the plurality of first switching devices. Step S102 of the method 1000 comprises: receiving an error associated with the MSB. Step S103 of the method 1000 comprises: when the MSB is set to 1, modifying the binary input signal to generate a control signal based on the binary input signal and the error associated with the MSB so that the current diverted by at least one first switching device compensates for the error associated with the MSB. Step S104 of method 1000 includes generating an output voltage based on the currents of the first path and the second path.

[0070] The present invention should not be considered limited to the preferred embodiments described above; many further variations and modifications are possible without departing from the scope of the patent claims. An electric machine configured in accordance with the present invention may be used wherever a small and efficient electric machine is desired, for example for controlling valves on internal combustion engines.

Claims

1. A digital-to-analog converter (DAC) circuit for outputting a voltage, comprising: a plurality of current providing devices (11) connected so that the output current of each current providing device is half the output current of the subsequent current providing device; a plurality of first switching devices (30) connected to each current providing device, respectively, wherein each first switching device is used to transfer each current to the first path (40) or the second path (50) based on a control signal; and A control device (12) is connected to the plurality of first switching devices and is configured to: receiving a binary input signal comprising a plurality of bits ranging from a most significant bit (MSB) to a least significant bit (LSB), wherein each bit is associated with a switching device in the plurality of first switching devices; receiving an error associated with the MSB; as well as when the MSB is set to 1, modifying the binary input signal to generate the control signal based on the binary input signal and the error associated with the MSB such that a current diverted by at least one first switching device compensates for the error associated with the MSB; The output voltage is generated based on the currents of the first path and the second path.

2. The DAC circuit according to claim 1, wherein The control device compensates for the error associated with the MSB by controlling at least one first switching device among the plurality of first switching devices, the at least one first switching device providing a current corresponding to the binary input signal and the error associated with the MSB.

3. The DAC circuit according to claim 1 , wherein: The plurality of current providing devices are a plurality of shunts (20), and the plurality of shunts (20) are connected so that the output current from each shunt is the input current of the subsequent shunt.

4. The DAC circuit according to claim 1, wherein The control device is connected to a plurality of current sources (125) and corresponding second switching devices (130), and The control device is further configured to control the second switching device such that currents generated by the plurality of current sources compensate for the error associated with the MSB.

5. The DAC circuit according to claim 4, wherein Each of the plurality of current sources generates a current equivalent to a current provided by a shunt corresponding to the LSB.

6. The DAC circuit according to claim 3, wherein The control device is also used for: receiving an error associated with the next MSB; and generating a control signal further based on said error associated with said next MSB, Such that when the next MSB is set to 1, current is delivered by the plurality of shunts that compensates for the error associated with the next MSB.

7. The DAC circuit according to any one of claims 1 to 5, wherein: The control device is further configured to reduce the current provided by the shunt corresponding to the MSB.

8. The DAC circuit according to claim 6, wherein The control means is further configured to reduce the current provided by the shunt corresponding to the next MSB.

9. The DAC circuit according to claim 1, wherein: The plurality of current providing devices and the switching devices form an R-2R ladder.

10. The DAC circuit according to claim 1, wherein The multiple current providing devices are: a plurality of current sources (125), wherein the current of the current source is twice the current of the continuous current source; as well as A current divider (120) is provided for dividing an input current into a first output current and a second output current, wherein the first output current is twice the second output current, and the second output current is twice the current of a first current source among the plurality of current sources (125).

11. The DAC circuit according to claim 10, wherein: The control device compensates for the error associated with the MSB by controlling at least one first switching device among the plurality of first switching devices, the at least one first switching device providing a current corresponding to the binary input signal and the error associated with the MSB.

12. The DAC circuit according to any one of claims 1 to 5, wherein: The error is a multiple of the current delivered to the switching device corresponding to the LSB.

13. The DAC circuit according to any one of claims 1 to 5, wherein: The error associated with the MSB is stored in non-volatile memory.

14. The DAC circuit according to any one of claims 1 to 5, wherein: The first path and the second path are connected to an operational transconductance amplifier OPAMP (60) for outputting an output current.

15. A method for a digital-to-analog converter (DAC) circuit for outputting a voltage, the DAC circuit comprising: a plurality of current providing devices (11) connected so that the output current of each current providing device is half the output current of the subsequent current providing device; and a plurality of first switching devices (30) respectively connected to each current providing device, wherein each first switching device is used to transfer each current to the first path (40) or the second path (50) based on a control signal, the method comprising: receiving ( S101 ) a binary input signal, the binary input signal comprising a plurality of bits ranging from a most significant bit (MSB) to a least significant bit (LSB), wherein each bit is associated with a switching device of the plurality of first switching devices; receiving ( S102 ) an error associated with the MSB; and When the MSB is set to 1, modifying (S103) the binary input signal to generate a control signal based on the binary input signal and the error associated with the MSB such that a current diverted by at least one first switching device compensates for the error associated with the MSB; and Based on the currents in the first path and the second path, an output voltage is generated ( S104 ).

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