A data synchronization system, method and storage medium

Abstract

The embodiment of the present invention discloses a data synchronization system, method and storage medium, the system comprising: at least one clock source and at least two communication terminals; each clock source is connected to each communication terminal respectively, and each communication terminal is connected to each other; one of the at least one clock source is used as a master clock source, which is used to generate a clock signal according to a preset rule and send it to each communication terminal; each communication terminal is used to determine the signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count, and when it is determined that the pulse count meets the preset data sending condition, terminal data is sent to other communication terminals. Data sending conditions for different communication terminals are set in advance, and each communication terminal determines whether its pulse count meets the preset data sending condition. If so, terminal data is sent to the remaining communication terminals. Bandwidth is saved, timing control is simple, only the master clock source is required to send the clock signal, and communication efficiency is high.

Description

Technical Field

[0001] Embodiments of the present invention relate to data synchronization technology, and more particularly to a data synchronization system, method and storage medium. Background Art

[0002] With the rapid development of intelligent systems, such as drones, unmanned vehicles, robots, etc., data exchange has also become a necessity of the system. The existing whole machine data interaction is usually realized through data buses such as 485, 422, CAN, etc. However, the commonly used 485 bus, 422 bus and other serial, in multi-site connection, usually half-duplex communication, usually with master-slave mode, data exchange is usually a query and response method, which occupies the total bandwidth of the data to a certain extent and has a certain impact on the data communication rate. The existing data exchange method has low communication efficiency and complex timing control. Summary of the invention

[0003] The present invention provides a data synchronization system, method and storage medium to achieve rapid synchronization of data between communication terminals.

[0004] In a first aspect, an embodiment of the present invention provides a data synchronization system, the data synchronization system comprising: at least one clock source and at least two communication terminals;

[0005] Each of the clock sources is connected to each of the communication terminals respectively, and the communication terminals are connected to each other;

[0006] One of the at least one clock source is used as a master clock source, for generating a clock signal according to a preset rule and sending the clock signal to each of the communication terminals;

[0007] Each of the communication terminals is used to determine the signal type of the clock signal, and perform corresponding pulse statistical operations according to the signal type to generate a pulse count, and when it is determined that the pulse count meets a preset data sending condition, send terminal data to other communication terminals.

[0008] Furthermore, the master clock source includes:

[0009] A reset signal generating module, configured to generate a reset signal according to a preset first duty cycle when the signal transmission frequency meets a preset reset condition;

[0010] A counting signal generating module, used for generating a counting signal according to a preset second duty cycle when the signal sending frequency does not meet a preset reset condition;

[0011] A signal sending module is used to send the reset signal or the counting signal as a clock signal to each of the communication terminals.

[0012] Furthermore, the preset reset condition includes: the number of count signals sent is within a preset threshold range.

[0013] Furthermore, the frequency of the clock signal is determined according to the bus communication rate.

[0014] Furthermore, the communication terminal includes:

[0015] A first operation execution module, used for accumulating pulse counts when the signal type is a counting type;

[0016] The second operation execution module is used to clear the pulse count when the signal type is a reset type.

[0017] Furthermore, the clock source is integrated in a communication terminal.

[0018] Further, the data synchronization system includes: at least two clock sources;

[0019] Each of the communication terminals is further configured to send master clock source failure information to the remaining communication terminals when detecting that the master clock source fails, so that each of the communication terminals selects one clock source from the remaining clock sources to be changed into a new master clock source.

[0020] In a second aspect, an embodiment of the present invention further provides a data synchronization method, which is executed by any communication terminal described in the embodiments of the present invention, and includes:

[0021] Receive the clock signal sent by the main clock source;

[0022] Determine a signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count;

[0023] When it is determined that the pulse count satisfies the preset data transmission condition, the terminal data is transmitted to other communication terminals.

[0024] Further, the performing a corresponding pulse statistical operation according to the signal type to generate a pulse count specifically includes:

[0025] When the signal type is a counting type, accumulating the pulse count generated by the pulse statistical operation;

[0026] When the signal type is a reset type, the pulse count generated by the pulse statistics operation is cleared.

[0027] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a data synchronization method as described in any one of the embodiments of the present invention.

[0028] The embodiment of the present invention provides a data synchronization system, method and storage medium, the system comprising: at least one clock source and at least two communication terminals; each of the clock sources is connected to each of the communication terminals respectively, and each of the communication terminals is connected to each other; one of the at least one clock source is used as a master clock source, which is used to generate a clock signal according to a preset rule and send it to each of the communication terminals; each of the communication terminals is used to determine the signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count, and when it is determined that the pulse count meets the preset data sending condition, send terminal data to other communication terminals. The clock source as the master clock source generates a clock signal according to the preset rule and sends it to each communication terminal. After receiving the clock signal, each communication terminal performs a corresponding pulse statistical operation according to the signal type. The data sending conditions of different communication terminals are preset, and each communication terminal determines whether its pulse count meets the preset data sending condition. If it meets the condition, the communication terminal can send terminal data to the other communication terminals connected to it, so as to achieve efficient data synchronization. There is no need to query and respond to information through the master-slave device mode, which saves bandwidth and simplifies timing control. Only the master clock source needs to send a clock signal, and the communication terminal can determine whether the local machine meets the data transmission conditions, and the communication efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a structural diagram of a data synchronization system in Embodiment 1 of the present invention;

[0030] Figure 2 is a structural diagram of a data synchronization system in Embodiment 2 of the present invention;

[0031] Figure 3 It is a flowchart of a data synchronization method in Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0034] In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0035] Embodiment 1

[0036] Figure 1 A structural schematic diagram of a data synchronization system provided in Embodiment 1 of the present application is given, the system comprising: at least one clock source 11 and at least two communication terminals 12;

[0037] Each clock source 11 is connected to each of the communication terminals 12, and each of the communication terminals 12 is connected to each other;

[0038] At least one of the clock sources 11 is used as a master clock source 111, which is used to generate a clock signal according to a preset rule and send it to each communication terminal 12;

[0039] Each communication terminal 12 is used to determine the signal type of the clock signal, and perform corresponding pulse statistical operations according to the signal type to generate a pulse count, and when it is determined that the pulse count meets a preset data sending condition, terminal data is sent to other communication terminals 12.

[0040] In this embodiment, the clock source 11 can be specifically understood as a clock pulse signal that can provide a stable frequency and level matching. The communication terminal 12 can be specifically understood as an intelligent terminal device that can perform functions such as information interaction and data processing. Each communication terminal 12 can be installed on the same device, for example, all installed on the same aircraft; or installed on different devices, for example, each communication terminal 12 is installed on a different walkie-talkie.

[0041] In this embodiment, the master clock source 111 can be specifically understood as a clock source that currently sends a clock signal and instructs each communication terminal 12 to perform data synchronization. Since the function of the master clock source 111 in this application is to send a clock signal to each communication terminal 12 so that each communication terminal 12 performs data synchronization according to the clock signal. Therefore, only one clock source is required to work in the data synchronization system. The preset rule can be specifically understood as a pre-set signal generation rule, and different rules can be used to generate different types of signals.

[0042] It can be known that when there are one or more clock sources 11 in the data synchronization system, one clock source 11 is selected from them to work normally as the main clock source 111. Other clock sources 11 can be used as alternative or redundant clock sources, waiting for the main clock source 111 to fail, and then the new main clock source 111 will take over the original main clock source 111.

[0043] Specifically, each clock source 11 is connected to each communication terminal 12, and each communication terminal 12 is connected to each other to realize data transmission and reception. When generating a clock signal, the clock source as the master clock source 111 determines the type of clock signal that needs to be generated at present, and generates clock signals with different duty cycles according to preset rules for different types of clock signals and sends them to each communication terminal 12 in the system, so that each communication terminal 12 can accurately distinguish different types of clock signals after receiving the clock signal.

[0044] In this embodiment, the signal type can be specifically understood as the type of clock signal, which can be used to indicate the role of the clock signal, for example, the counting type instructs each communication terminal 12 to count; the reset type instructs each communication terminal 12 to initialize the value of the accumulated count, and the reset can be clearing. The pulse statistical operation can be specifically understood as the operation of performing corresponding statistics on the pulse count, and the pulse statistical operation can be the accumulation of the pulse count, or it can be the accumulation, subtraction, clearing, etc. The data sending condition can be specifically understood as the condition for determining whether the communication terminal 12 sends data to the outside, and the data sending condition can be satisfied when the pulse count reaches a preset value, or when the pulse count is an integer multiple of n, or it can be determined by taking the remainder, etc. The terminal data can be specifically understood as the relevant data of the communication terminal 12, which can be the status data of the communication terminal 12, the data collected or processed by the communication terminal 12, and the data generated or acquired during the working process of the communication terminal 12 can be used as the terminal data.

[0045] Specifically, each communication terminal 12 receives the clock signal sent by the main clock source 111, analyzes the characteristics of the received clock signal, for example, analyzes the duty cycle, and determines the signal type according to the different duty cycles. After determining the signal type, the pulse statistical operation corresponding to this signal type is determined according to the mapping relationship between the signal type and the pulse statistical operation, and the corresponding pulse statistical operation is performed to generate a pulse count. Each communication terminal 12 determines the pulse count of the local machine, determines whether the pulse count meets the data transmission conditions of the local machine, and when the pulse count meets the data transmission conditions, the relevant data of the local machine is selected to form terminal data and sent to other communication terminals 12 connected thereto, thereby realizing data synchronization of each communication terminal 12.

[0046] Each communication terminal 12 will not conflict when sending terminal data, and there is no additional timing management data on the communication bus, thereby maximizing bus utilization.

[0047] It can be known that at the same time, only one communication terminal 12 has a pulse count that meets the data transmission condition. Therefore, at the same time, only one communication terminal 12 can send terminal data to the outside. Different communication terminals 12 send terminal data in an interleaved manner to achieve data synchronization between different communication terminals 12. After receiving terminal data sent by other communication terminals 12, the communication terminal 12 can determine the working status of other communication terminals 12 according to the terminal data. When a communication terminal 12 fails, the fault can be discovered and repaired in time, and the work of the failed communication terminal 12 can also be taken over to ensure the normal operation of the system, reduce the system failure rate, and improve the system work efficiency.

[0048] The embodiment of the present invention provides a data synchronization system, which includes: at least one clock source and at least two communication terminals; each clock source is connected to each communication terminal respectively, and each communication terminal is connected to each other; one of the at least one clock source is used as a master clock source, which is used to generate a clock signal according to a preset rule and send it to each communication terminal; each communication terminal is used to determine the signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count, and when it is determined that the pulse count meets the preset data sending condition, send terminal data to other communication terminals. The clock source as the master clock source generates a clock signal according to the preset rule and sends it to each communication terminal. After receiving the clock signal, each communication terminal performs a corresponding pulse statistical operation according to the signal type. The data sending conditions of different communication terminals are pre-set, and each communication terminal determines whether its pulse count meets the preset data sending condition. If it does, this communication terminal can send terminal data to the other communication terminals connected to it, so as to achieve efficient data synchronization. There is no need to perform information inquiry and response through the master-slave device mode, which saves bandwidth and has simple timing control. Only the master clock source needs to send a clock signal, and the communication terminal can determine whether the local device meets the data sending condition, and the communication efficiency is high.

[0049] Embodiment 2

[0050] Figure 2 The structure diagram of a data synchronization system provided by the second embodiment of the present invention is shown in FIG. The embodiment of the present invention is optimized based on the above embodiment. Figure 2As shown, the embodiment of the present invention further refines the main clock source 111, specifically including: a reset signal generating module 1111, used to generate a reset signal according to a preset first duty cycle when the signal sending frequency meets the preset reset condition; a counting signal generating module 1112, used to generate a counting signal according to a preset second duty cycle when the signal sending frequency does not meet the preset reset condition; a signal sending module 1113, used to send the reset signal or the counting signal as a clock signal to each communication terminal 12.

[0051] In this embodiment, the reset signal generating module 1111 can be specifically understood as a data processing module for generating a reset signal. The preset reset condition can be a pre-set condition. For example, if the signal transmission frequency reaches 300 clock signals have been sent, it is determined that the preset reset condition is met. The counting signal generating module 1112 can be specifically understood as a data processing module for generating a counting signal. The signal sending module 1113 can be specifically understood as a module for sending a clock signal to each communication terminal 12.

[0052] Specifically, the reset signal generating module 1111 detects the signal transmission frequency of the clock signal, determines whether the signal transmission frequency satisfies the preset reset condition, and if the signal transmission frequency satisfies the preset reset condition, generates a reset signal according to a first duty cycle of a preset size. The counting signal generating module 1112 also detects the signal transmission frequency of the clock signal, determines whether the signal transmission frequency satisfies the reset condition, and if the signal transmission frequency does not satisfy the reset condition, generates a counting signal according to a second duty cycle of a preset size. The signal transmitting module 1113 sends the generated reset signal or counting signal as a clock signal to each communication terminal 12.

[0053] In this embodiment, the first duty cycle and the second duty cycle are different in size so as to distinguish the reset signal from the counting signal. The first duty cycle and the second duty cycle can be set according to actual engineering application requirements.

[0054] As an optional embodiment of this embodiment, this optional embodiment further optimizes the preset reset condition: the preset reset condition includes: the number of count signals sent is within a preset threshold range.

[0055] In this embodiment, the preset threshold range can be specifically understood as a preset numerical range, which can be a numerical interval, for example, the interval [300-301), or a specific numerical value, for example, 300, that is, the preset reset condition is satisfied only when the number of counting signals is equal to 300. The number of counting signals is equal to the pulse count, that is, the master clock source 111 sends a clock signal, and the clock signal is a counting signal or a reset signal. The communication terminal 12 will accumulate the pulse count after receiving the counting signal, and will clear the pulse count after receiving the reset signal. The master clock source 111 will record the sending frequency of the sent counting signal, and the number of recorded counting signals is the same as the pulse count counted by each communication terminal 12. When the master clock source 111 records the number of counting signals, if the number of counting signals meets the preset threshold range (for example, equal to 300), it is determined that the preset reset condition is satisfied, and a reset signal is generated according to the first duty cycle.

[0056] In the embodiment of the present application, when it is determined that the number of count signals is within the preset threshold range, the number of count signals can be cleared to achieve timing generation and send a reset signal to reset the pulse count. If the number of count signals is not cleared, the preset threshold range can be set to an integer range such as 300, 600, 900, etc. to achieve timing generation of the reset signal.

[0057] Further, the frequency of the clock signal is determined according to the bus communication rate.

[0058] In this embodiment, the bus communication rate can be specifically understood as the communication rate of the data bus for communication connection between the communication terminals 12. The bus communication rate can represent the speed of data exchange between the communication terminals 12. When the amount of communication data is small, the sending speed of the clock signal is set slower, and the frequency of the clock signal is smaller. When the amount of communication data is large, the sending speed of the clock signal is set faster, and the frequency of the clock signal is larger. In this application, the frequency of the clock signal is usually constant, and the clock signal is sent at a certain frequency. However, when the bus communication rate changes, in order to ensure the efficiency and effect of data exchange, the frequency of the clock signal will change with the change of the bus communication rate. It can support high-speed, large-bandwidth data interaction, and the bus bandwidth of each communication terminal 12 can be equal, unequal, and flexibly set.

[0059] Furthermore, the communication terminal 12 includes:

[0060] A first operation execution module 121, configured to accumulate pulse counts when the signal type is a counting type;

[0061] The second operation execution module 122 is used to clear the pulse count when the signal type is a reset type.

[0062] In this embodiment, the first operation execution module 121 can be specifically understood as being used to execute a corresponding pulse statistical operation after receiving a counting type clock signal. The second operation execution module 122 can be specifically understood as being used to execute a corresponding pulse statistical operation after receiving a reset type clock signal.

[0063] After the communication terminal 12 receives the clock signal and determines the type of the clock signal, when the signal type is a counting type, the first operation execution module 121 accumulates the pulse count, and the accumulation method can be to add 1 to the pulse count for each received clock signal of the counting type. When the signal type is a reset type, the second operation execution module 122 clears the pulse count. The pulse count can be cleared regularly through the reset signal to avoid the communication terminal 12 pulse counting error, which cannot be discovered and corrected in time, affecting data synchronization.

[0064] Exemplarily, taking the number of communication terminals as 3, the master clock source generates the first counting signal and sends it to each communication terminal. After receiving the first counting signal, communication terminals 1 to 3 count 1 respectively. When the pulse count is 1, communication terminal 1 determines that the data transmission condition of the local device is met, and sends terminal data to communication terminals 2 and 3 for data synchronization. After the master clock source 111 sends the first counting signal, it sends the second counting signal. After communication terminals 1-3 receive it, the pulse count is accumulated. At this time, the pulse count is 2. Communication terminal 2 determines that the data transmission condition of the local device is met, and sends terminal data to communication terminals 1 and 3 for data synchronization. The master clock source 111 sends the third counting signal. After receiving it, communication terminals 1-3 accumulate the pulse count. At this time, the pulse count is 3. Communication terminal 3 determines that the data transmission condition of the local device is met, and sends terminal data to communication terminals 1 and 2 for data synchronization. The master clock source 111 sends the fourth count signal. After receiving it, communication terminals 1-3 accumulate the pulse count. At this time, the pulse count is 4. Communication terminal 1 determines that the data transmission conditions of the local device are met, and sends terminal data to communication terminals 2 and 3 for data synchronization, thereby achieving data synchronization. When the number of count signals sent by the master clock source reaches 300, a reset signal is generated to clear the count to avoid excessive pulse counts, which may prevent timely detection and correction when errors occur.

[0065] Furthermore, the clock source 11 may be integrated into the communication terminal 12 .

[0066] The number of clock sources 11 of the present application may be one or more, and each clock source 11 may be integrated in a communication terminal 12. Each clock source 11 may be integrated in the same communication terminal 12 or in different communication terminals 12 respectively, that is, the clock source 11 may be generated from one or more communication terminals 12.

[0067] The clock source 11 in the embodiment of the present application may also come from a dedicated clock unit and is not integrated in the communication terminal 12 .

[0068] Further, the system comprises: at least two clock sources 11;

[0069] Each communication terminal 12 is further configured to send master clock source failure information to other communication terminals 12 when detecting that the master clock source 111 fails, so that each communication terminal 12 selects one clock source 11 from the remaining clock sources 11 to be changed into a new master clock source 111 .

[0070] In this embodiment, the master clock source failure information can be specifically understood as information used to inform other communication terminals 12 that the master clock source 111 has failed. The master clock source failure information can be generated in an agreed format, and the master clock failure information can include information such as clock failure and when the clock fails, or it can be just an agreed indication information. After receiving the information in this format, each communication terminal 12 can determine that the master clock source 111 has failed.

[0071] Each communication terminal 12 communicates with the master clock source 111 and receives the clock signal sent by the master clock source 111. If the communication terminal 12 does not receive the clock signal sent by the master clock source 111 within a period of time, it can be determined that the master clock source 111 is invalid. At this time, the communication terminal 12 that detects the failure of the master clock source 111 generates and sends the master clock source failure information to the remaining communication terminals 12. After receiving the master clock source failure information, the remaining communication terminals 12 determine that the current master clock source 111 has failed. Each communication terminal 12 selects a clock source 11 from the remaining clock sources 11 as a new master clock source 111 to ensure the normal data synchronization. The method of selecting a clock source 11 from the remaining clock sources 11 can be: each clock source 11 is marked in advance and sorted according to a certain rule. If the current master clock source 111 fails, a new master clock source 111 is selected from the remaining clock sources 11 in order. For example, the current master clock source 111 is the clock source 11 numbered 1. When it fails, the clock source 11 numbered 2 is selected as the new master clock source 111. Each communication terminal selects the same clock source as the new master clock source. By setting an alternative clock source 11, after a clock source 11 fails, the alternative clock source 11 can take over the work without affecting the normal operation of the system, ensuring that the data synchronization of the communication terminal will not be interrupted, having good redundancy, and having higher reliability than the traditional master-slave transmission logic.

[0072] It can be known that the structures and working principles of the clock sources 11 are the same, and they also include a reset signal generating module, a counting signal generating module and a signal sending module. When a clock source 11 is reselected as a new master clock source 111, the master clock source 111 at this time also realizes the corresponding functions.

[0073] The duration of the communication terminal 12 sending the terminal data can be controlled by the clock signal. For example, after sending the counting signal, the main clock source 111 can send a high-level signal for a period of time. During the duration of this high level, the communication terminal 12 sends the terminal data to the outside. Alternatively, since the frequency of the clock signal is known, the duty cycle of the counting signal in the signal cycle can also be preset. Therefore, the duration of the high and low levels in the counting signal cycle is determined. For example, it is a high level within 0-0.5ms and a low level within 0.5-1ms. After receiving the counting signal, the communication terminal 12 can determine that the clock signal is a counting signal after 0.5ms, and sends data to the outside during the low level period within 0.5-1ms. After receiving the next high-level signal, the pulse count changes, and the communication terminal 12 that sends the data is switched. The high and low level time of the above signal cycle is only for example, and it can be other times in reality.

[0074] The embodiment of the present invention provides a data synchronization system, which includes: at least one clock source and at least two communication terminals; each clock source is connected to each of the communication terminals respectively, and each communication terminal is connected to each other; one of the at least one clock source is used as a master clock source, which is used to generate a clock signal according to a preset rule and send it to each communication terminal; each communication terminal is used to determine the signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count, and when it is determined that the pulse count meets the preset data sending condition, send terminal data to other communication terminals. The clock source as the master clock source generates a clock signal according to the preset rule and sends it to each communication terminal. After receiving the clock signal, each communication terminal performs a corresponding pulse statistical operation according to the signal type to generate a pulse count. The data sending conditions of different communication terminals are preset, and each communication terminal determines whether its pulse count meets the preset data sending condition. If it meets the condition, the communication terminal can send terminal data to the other communication terminals connected to it, so as to achieve efficient data synchronization. Each communication terminal will not conflict when sending terminal data, and there is no additional timing management data on the communication bus, so as to maximize the bus utilization. There is no need to query and respond to information through the master-slave device mode, which saves bandwidth and simplifies timing control. Only the master clock source needs to send a clock signal, and the communication terminal can determine whether the local machine meets the data transmission conditions, and the communication efficiency is high.

[0075] Embodiment 3

[0076] Figure 3A flow chart of a data synchronization method provided in Embodiment 3 of the present invention is provided, and the method is executed by any communication terminal described in the embodiments of the present application.

[0077] S201. Receive a clock signal sent by a main clock source.

[0078] The master clock source generates a clock signal according to a preset rule and sends it to the communication terminal. When the signal transmission frequency meets the reset condition, the master clock source generates a reset signal according to the first duty cycle; when the signal transmission frequency does not meet the reset condition, it generates a count signal according to the second duty cycle. After generating the reset signal or count signal, it is sent to the communication terminal as a clock signal. The communication terminal receives the clock signal sent by the master clock source so as to perform data synchronization according to the clock signal.

[0079] S202: Determine a signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count.

[0080] After receiving the clock signal, the duty cycle of the clock signal is analyzed to determine the signal type of the clock signal, and the corresponding pulse statistical operation is determined according to the signal type. The pulse count is generated according to the pulse statistical operation. The pulse statistical operation can be operations such as accumulation and clearing of the pulse count.

[0081] S203: When it is determined that the pulse count meets a preset data sending condition, terminal data is sent to other communication terminals.

[0082] The communication terminal determines the pulse count counted by the local machine, and judges whether the pulse count meets the data transmission conditions of the local machine. If so, it determines that this is the data transmission time of the local machine, and sends the terminal data to other communication terminals to achieve data synchronization.

[0083] The embodiment of the present invention provides a data synchronization method, which includes: receiving a clock signal sent by a master clock source; determining the signal type of the clock signal, and performing a corresponding pulse statistical operation according to the signal type to generate a pulse count; when it is determined that the pulse count meets the preset data transmission condition, sending terminal data to other communication terminals. After receiving the clock signal sent by the master clock source, the communication terminal determines the signal type, and performs a corresponding pulse statistical operation according to the signal type to generate a pulse count. The data transmission conditions of different communication terminals are pre-set, and the communication terminal determines whether its own pulse count meets the preset data transmission conditions. If it does, the terminal data can be sent to the remaining communication terminals connected to it, so as to achieve efficient data synchronization. There is no need to perform information inquiry and response through the master-slave device mode, which saves bandwidth and has simple timing control. Only the master clock source needs to send a clock signal, and the communication terminal can determine whether the local machine meets the data transmission conditions, and the communication efficiency is high.

[0084] Further, the performing corresponding pulse statistical operations according to the signal type includes:

[0085] When the signal type is a counting type, accumulating the pulse count generated by the pulse statistical operation;

[0086] When the signal type is a reset type, the pulse count generated by the pulse statistics operation is cleared.

[0087] Furthermore, the frequency of the clock signal is determined according to the bus communication rate.

[0088] Embodiment 4

[0089] Embodiment 4 of the present invention further provides a storage medium including computer executable instructions, wherein the computer executable instructions are used to execute a data synchronization method when executed by a computer processor, the method comprising:

[0090] Receive the clock signal sent by the main clock source;

[0091] Determine a signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count;

[0092] When it is determined that the pulse count satisfies the preset data transmission condition, the terminal data is transmitted to other communication terminals.

[0093] Of course, the computer executable instructions of a storage medium containing computer executable instructions provided by an embodiment of the present invention are not limited to the operations of the method described above, and can also execute related operations in the data synchronization method provided by any embodiment of the present invention.

[0094] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0095] It is worth noting that in the embodiment of the above-mentioned data synchronization system, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0096] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A data synchronization system, It is characterized in that include: at least two clock sources and at least two communication terminals; Each of the clock sources is connected to each of the communication terminals respectively, and the communication terminals are connected to each other; One of the at least two clock sources is used as a master clock source, and is used to generate a clock signal according to a preset rule and send the clock signal to each of the communication terminals; Each of the communication terminals is configured to determine a signal type of the clock signal, and to perform a corresponding pulse statistical operation according to the signal type to generate a pulse count, and to send terminal data to other communication terminals when it is determined that the pulse count meets a preset data sending condition; Each of the communication terminals is further configured to send master clock source failure information to the remaining communication terminals when detecting that the master clock source fails, so that each of the communication terminals selects a clock source from the remaining clock sources to be changed to a new master clock source; The step of selecting a clock source from the remaining clock sources and changing it to a new master clock source includes: Each clock source is marked in advance and sorted according to certain rules. If the current master clock source fails, a new master clock source is selected from the remaining clock sources in order. Wherein, the main clock source includes: A reset signal generating module, configured to generate a reset signal according to a preset first duty cycle when the signal transmission frequency meets a preset reset condition; A counting signal generating module is used to generate a counting signal according to a preset second duty cycle when the signal sending frequency does not meet a preset reset condition; wherein the first duty cycle and the second duty cycle are different in size.

2. The data synchronization system according to claim 1, It is characterized in that The main clock source further includes: A signal sending module is used to send the reset signal or the counting signal as a clock signal to each of the communication terminals.

3. The data synchronization system according to claim 1, It is characterized in that The preset reset condition includes: the number of count signals sent is within a preset threshold range.

4. The system according to claim 1, It is characterized in that The frequency of the clock signal is determined according to the bus communication rate.

5. The data synchronization system according to claim 1, It is characterized in that The communication terminal comprises: A first operation execution module, used for accumulating pulse counts when the signal type is a counting type; The second operation execution module is used to clear the pulse count when the signal type is a reset type.

6. The data synchronization system according to claim 1, It is characterized in that The clock source is integrated in the communication terminal.

7. A data synchronization method, It is characterized in that The method is performed by the communication terminal according to any one of claims 1 to 6, comprising: Receive the clock signal sent by the main clock source; Determine a signal type of the clock signal, and perform a corresponding pulse statistical operation according to the signal type to generate a pulse count; When it is determined that the pulse count satisfies the preset data transmission condition, the terminal data is transmitted to other communication terminals.

8. The method according to claim 7, It is characterized in that The performing a corresponding pulse statistical operation according to the signal type to generate a pulse count specifically includes: When the signal type is a counting type, accumulating the pulse count generated by the pulse statistical operation; When the signal type is a reset type, the pulse count generated by the pulse statistics operation is cleared.

9. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the program is executed by a processor, the data synchronization method as described in any one of claims 7 to 8 is implemented.

Images