Josephson magnetic memory with semiconductor-based magnetic spin valve

Abstract

A Josephson magnetic memory cell having a semiconductor-based magnetic spin valve is described. The example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve disposed between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator disposed adjacent to the semiconductor layer, disposed on a first side of the semiconductor layer, and configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve also includes a second ferromagnetic insulator disposed on a second side of the semiconductor layer, opposite the first side, and configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, and to the second superconducting electrode.

Description

Background Art

[0001] Semiconductor-based integrated circuits used in electronic devices, such as random access memory, include digital circuits based on complementary metal oxide semiconductor (CMOS) technology. However, CMOS technology is reaching its limits in terms of device size. In addition, leakage current in CMOS-based memories can lead to high power consumption, even when the memories are not being accessed.

[0002] As an example, servers in data centers are consuming increasing amounts of power. Even when CMOS circuits are inactive, power consumption is partly a result of power losses due to energy dissipation. This is because even when such circuits (such as random access memory) are inactive and not consuming any dynamic power, they still consume power due to the need to maintain the state of the CMOS transistors. In addition, because CMOS circuits are powered by DC voltage, there is a certain amount of current leakage even when the CMOS circuits are inactive. Therefore, even when such circuits are not performing processing operations such as read / write, power is wasted not only due to the need to maintain the state of the CMOS transistors, but also due to current leakage.

[0003] An alternative to memories based on CMOS technology is Josephson magnetic memory. Summary of the Invention

[0004] In one example, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed adjacent to the semiconductor layer, wherein the first ferromagnetic insulator is disposed on a first side of the semiconductor layer, and wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed adjacent to the semiconductor layer, wherein the second ferromagnetic insulator is disposed on a second side of the semiconductor layer opposite the first side, and wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode.

[0005] In another example, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode. The semiconductor-based magnetic spin valve may further include a control gate disposed on top of the semiconductor layer, located between the first ferromagnetic insulator and the second ferromagnetic insulator, and configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator.

[0006] In yet another example, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first control gate configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator. The semiconductor-based magnetic spin valve may further include a second control gate configured to control a carrier density of the semiconductor layer.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0009] Figure 1 shows a cross-sectional view of an example memory cell during fabrication;

[0010] Figure 2 shows a cross-sectional view of an example memory cell during fabrication;

[0011] Figure 3 shows a cross-sectional view of an example memory cell during fabrication;

[0012] Figure 4 shows a cross-sectional view of an example memory cell during fabrication;

[0013] Figure 5 shows a top view of an example memory cell during fabrication;

[0014] Figure 6 shows the density of a supercurrent flowing through a semiconductor layer according to one example;

[0015] Figure 7 shows the density of a supercurrent flowing through a semiconductor layer according to another example;

[0016] Figure 8 shows a cross-sectional view of another example memory cell during fabrication;

[0017] Figure 9 shows a memory cell circuit according to one example; and

[0018] Figure 10 A computing system including a memory coupled to a processor is shown according to one example. DETAILED DESCRIPTION

[0019] Examples described in this disclosure relate to memory systems based on superconducting logic, including memories with semiconductor-based magnetic spin valves. Certain examples also relate to Josephson magnetic random access memory (JMRAM) with semiconductor-based magnetic spin valves. Unlike CMOS transistors, superconducting devices use devices based on Josephson junctions.

[0020] Various superconducting circuits, including transmission lines, can be formed by coupling multiple Josephson junctions via inductors or other components as needed. Single-flux quantum (SFQ) pulses can be propagated through these transmission lines under the control of at least one clock. SFQ pulses can be positive or negative. For example, when a sinusoidal bias current is supplied to the junction, both positive and negative pulses can propagate to the right on the transmission line during opposite clock phases.

[0021] Microwave signals (e.g., SFQ pulses) can be used to control the state of a memory cell. During read / write operations, word lines and bit lines can be selectively activated by SFQ pulses arriving via an address bus. These pulses can in turn control word line and bit line drivers, which can provide word line and bit line currents to the associated memory cells. As an example, the state of such a memory cell can be read out using a superconducting quantum interference device (SQUID). The memory cell circuit can include a SQUID and a semiconductor-based magnetic spin valve device.

[0022] The memory cells can be arranged in rows and columns such that each row can be activated by a common flux bias (e.g., a read word line signal), and each bit line can form a transmission line that can propagate the output of the memory cell in a voltage state to a sense amplifier at one end of the column. The memory cells in a column can be serially biased by a common current source; for example, a flux pump.

[0023] Figure 1 A cross-sectional view of an example memory cell 100 during fabrication is shown. In this example, as part of this step, starting with a substrate 102, a buffer layer 104 may be formed. In this example, the substrate 102 may be an indium phosphide (InP) substrate. The buffer layer 104 may be an indium gallium arsenide (InGaAs) layer. Next, a semiconductor layer 106 may be formed on the top buffer layer 104. The semiconductor layer 106 may include gallium arsenide (GaAs) or indium arsenide (InAs). The semiconductor layer 106 may also include indium antimonide (InSb). Additionally, the semiconductor layer 106 may also be a ternary alloy including any combination of these materials (e.g., GaAsSb and InAsSb). Each of these layers may be formed using molecular beam epitaxy (MBE). As an example, MBE-related processes may be performed in an MBE system that allows for the deposition of appropriate materials in a vacuum. Although Figure 1 A certain number of layers of memory cell 100 are shown arranged in a certain manner, but there may be a greater or lesser number of layers arranged in a different manner.

[0024] Figure 2A cross-sectional view of an example memory cell 100 during fabrication is shown. In this example, as part of this step, a dielectric layer 108 may be formed on top of the semiconductor layer 106. The dielectric layer 108 may include any suitable dielectric, including oxide-based dielectrics. Although Figure 2 A certain number of layers of the memory cell 100 are shown arranged in a certain manner, but there may be a greater or lesser number of layers arranged in a different manner.

[0025] Figure 3 A cross-sectional view of an example memory cell during fabrication is shown. In this example, as part of this step, which may include multiple sub-steps, a superconducting electrode 112 and another superconducting electrode 114 may be formed. Figure 3 As shown, superconducting electrode 112 and superconducting electrode 114 can be formed so that during operation of memory cell 100, current can flow from superconducting electrode 112 to superconducting electrode 114 through semiconductor layer 106. Current can also flow in the opposite direction. In this example, superconducting electrode 112 and superconducting electrode 114 can be formed by using a mask and a photolithography-based manufacturing technique. Therefore, as needed, semiconductor layer 106 and dielectric layer 108 can be etched to define areas where electrodes can be formed. In this example, superconducting electrode 112 and superconducting electrode 114 can include a superconducting metal, such as niobium. Other niobium alloys can also be used, such as niobium-titanium-nitride (NbTiN).

[0026] Continue to refer to Figure 3 , dielectric layer 108 may be further processed to form ferromagnetic insulator 120 and another ferromagnetic insulator 122. In one example, each of ferromagnetic insulator 120 and ferromagnetic insulator 122 may include europium sulfide (EuS). In another example, each of ferromagnetic insulator 120 and ferromagnetic insulator 122 may include europium oxide (EuO). Ferromagnetic insulator 120 may be spaced apart from ferromagnetic insulator 122 by a selected distance (e.g., Figure 3 The amount of the selected distance (A) can be selected to control the coupling between the ferromagnetic insulator 120 and the ferromagnetic insulator 122. Although the ferromagnetic insulator 120 and the ferromagnetic insulator 122 are shown as being formed on top of the semiconductor layer 106, they can be formed elsewhere as long as they are close to the semiconductor layer 106. As used in this disclosure, the term "close to" includes the arrangement of the ferromagnetic insulator on top of the semiconductor layer 106, such as Figure 3 However, the term is not limited to this example. Ferromagnetic insulators are arranged “close to” semiconductor layer 106 as long as they are arranged in a manner that can influence the phase of the supercurrent flowing through semiconductor layer 106 .

[0027] Still refer to Figure 3 As part of the memory cell 100, a control gate 124 may be formed. The control gate 124 may comprise a suitable metal or a suitable stack of layers. Example metals include aluminum, copper, titanium, or other metals. In this example, the control gate 124 may be configured to control the coupling of electrons through the semiconductor layer 106 between the ferromagnetic insulator 120 and the ferromagnetic insulator 122. The coupling may be controlled by applying a specific voltage via the control gate 124. In one example, while minimizing energy consumption may be important, the coupling between the ferromagnetic insulator 120 and the ferromagnetic insulator 122 needs to be sufficiently weak so that uncontrolled state changes do not occur. Therefore, if there is some magnetic moment discontinuity between the two ferromagnets, the control gate 124 may minimize this to stabilize the memory cell (e.g., the memory cell state does not flip on its own, but at the same time, the difference in supercurrent flowing through the semiconductor layer 106 may be sufficient to distinguish the magnetization difference). The voltage applied via the control gate 124 may be selected to achieve these goals. This is because applying a voltage via the gate 124 may affect the charge carriers in the semiconductor layer 106. Additionally, as mentioned above, the distance between the ferromagnetic insulators can be selected to further control the coupling between the ferromagnetic insulators. Figure 3 A certain number of layers of memory cell 100 are shown arranged in a certain manner, but a greater or lesser number of layers may be arranged in a different manner. Additionally, the layers and other features of memory cell 100 may be formed in a different order. As an example, dielectric layer 108 may be deposited after forming ferromagnetic insulator 120 and ferromagnetic insulator 122, and then control gate 124 may be formed.

[0028] Figure 4 A cross-sectional view of an example memory cell 100 during fabrication is shown. In this example, as part of this step, a back gate 130 may be formed. In this example, the back gate 130 may be formed using a portion of the substrate 102. Thus, as an example, a portion of the substrate 102 with appropriate doping may serve as the back gate 130. In another example, the back gate 130 may include a metal alloy or metal, such as aluminum, niobium, or copper. The back gate 130 may also include a stack, including multiple layers. In yet another example, the back gate 130 may be a doped portion of the semiconductor layer 106. In one example, the back gate 130 may serve as another control gate for the memory device 100. Thus, applying a voltage to the back gate 130 may control the density of carriers in the semiconductor layer 106. Although Figure 4A certain number of layers of memory cell 100 are shown arranged in a certain manner, but a greater or lesser number of layers may be arranged in a different manner. As an example, memory cell 100 may not include control gate 124. This is because the coupling between ferromagnetic insulators can be controlled by spacing them apart as described earlier. As another example, memory cell 100 may not include back gate 130. This is because the density of carriers in semiconductor layer 106 can be controlled by controlling the doping in the stack of layers used to form memory cell 100.

[0029] Figure 5 A top view of an example memory cell 100 during fabrication is shown. In this example, the top view shows an example arrangement including superconducting electrode 112, superconducting electrode 114, dielectric layer 108, ferromagnetic insulator 120, ferromagnetic insulator 122, and control gate 124. Although Figure 5 A certain number of layers of the memory cell 100 are shown arranged in a certain manner, but there may be a greater or lesser number of layers arranged in a different manner. As an example, the layers and components need not be formed in a planar arrangement.

[0030] In terms of the operation of memory cell 100, electrons in semiconductor layer 106 can carry a supercurrent, which can undergo magnetization, and when the magnetizations of each of the two ferromagnetic insulators (e.g., ferromagnetic insulator 120 and ferromagnetic insulator 122) are in the same direction (e.g., parallel to each other), the phase accumulated during the transmission can be added. Alternatively, when the magnetizations of each of the two ferromagnetic insulators (e.g., ferromagnetic insulator 120 and ferromagnetic insulator 122) are in opposite directions (e.g., antiparallel to each other), the phases can be canceled. In memory cell 100, no supercurrent flows through the ferromagnetic insulators (e.g., ferromagnetic insulator 120 and ferromagnetic insulator 122).

[0031] Figure 6 The graph 610 shows the relationship between the density of the supercurrent flowing through the semiconductor layer 106 and the phase of the supercurrent, depending on whether the magnetization of the ferromagnetic insulator is parallel or antiparallel. 2 ) and the superconducting phase (φ). Graph 650 shows the relationship between the supercurrent density (mA / μm) when the magnetizations of the ferromagnetic insulator are antiparallel. 2 ) and the superconducting phase (φ). As shown by graphs 610 and 650, the magnitude of the supercurrent is lower for certain values ​​of the superconducting phase (φ) when the magnetization of the ferromagnetic insulator is parallel rather than antiparallel. Similarly, the sign associated with the current is different for the same phase value. Each of these parameters can be controlled to affect a change in the state of the memory cell 100.

[0032] Figure 7 The relationship between the density of the supercurrent flowing through the semiconductor layer 106 and the phase of the supercurrent is shown, depending on whether the magnetization of the ferromagnetic insulator is parallel or antiparallel. Figure 7 Corresponding to the junction behavior. Graph 710 shows that when the magnetizations of the ferromagnetic insulators are parallel, the supercurrent density (mA / μm 2 ) and the superconducting phase (φ). Graph 750 shows the supercurrent density (mA / μm) when the magnetizations of the ferromagnetic insulator are antiparallel. 2 ) and the superconducting phase (φ). As shown via graphs 710 and 750, the magnitude of the supercurrent is lower for certain values ​​of the superconducting phase (φ) when the magnetizations of the ferromagnetic insulator are parallel rather than antiparallel. Similarly, the sign associated with the current is different for certain values ​​of the phase. Each of these parameters can be controlled to affect a change in the state of the memory cell 100. With respect to Figure 7 The coupling strength of the ferromagnetic insulator in the graph shown is Figure 6 Therefore, in a parallel configuration, relative to Figure 6 As shown in the graph, the magnitude of the supercurrent exceeds Figure 7 The graph shown.

[0033] Advantageously, the example memory cell 100 includes only two materials to form a Josephson junction, resulting in fewer interfaces that may adversely affect the operation of the memory cell 100. However, a conventional JMRAM memory cell may include multiple interfaces—for example, an interface between niobium and copper and another interface between copper and iron or nickel. Each of these interfaces can change the characteristics of the signal propagating at these interfaces. In addition, in a conventional JMRAM memory cell, the Josephson junction may use copper as a spacer, which in some instances may lead to strong spin-orbit coupling, thereby causing spin-orbit physics-related issues. However, the memory cell 100 does not include such copper-induced spin-orbit physics-related issues. Moreover, the ferromagnetic domains in ferromagnetic insulators (such as EuS) are very large, so any harmful effects of multi-domain physics are eliminated. This is because in a typical ferromagnetic material, there are multiple magnetic domains that interfere with each other, resulting in a multi-domain effect.

[0034] Additionally, the electrons corresponding to the supercurrent can be influenced in a way that suppresses the supercurrent based on electrons diffusing through the ferromagnet. However, in memory cell 100, the movement of electrons through semiconductor layer 106 is ballistic, rather than diffusive, so the transport of the supercurrent is easier to manage. The trajectories in ballistic transport are simple—essentially straight lines from one lead to the other—making it easier to understand and optimize stacks with ballistic transport. However, in the case of diffusive transport, the trajectories are complex. The electrons diffuse throughout the structure carrying the electrons, and their different trajectories cancel out the signal; therefore, the supercurrent in such a structure decays very quickly. Therefore, one can control the amount of disorder in the semiconductor, thereby producing a clean stack with ballistic transport. In contrast, in a metal junction, disorder is inherent and cannot be controlled (e.g., even with a control gate).

[0035] In addition, as described, during the fabrication of the memory cell, a high-quality material stack can be grown using molecular beam epitaxy (MBE), which is less susceptible to even slight disorder. Stacks grown using MBE allow for a high degree of control over the deposition of each layer. In addition, compared to devices formed using sputtering techniques, the stack has a small number of interfaces (e.g., only two interfaces), where each deposition of new material changes the properties of the stack. Moreover, the semiconductor portion of the system (with the deposited ferromagnetic insulator) can be characterized separately using manufacturing techniques. In addition, the memory cell 100 has a highly tunable coupling between the ferromagnetic insulator and the supercurrent, which allows for optimization of the operating regime of the memory cell 100. As explained earlier with respect to the memory cell 100, using the correct spacing and control gates, the coupling between the magnetic valves can be optimized.

[0036] Figure 8 A cross-sectional view of another example memory cell 800 during fabrication is shown. The layers and other portions of the memory cell 800 may be fabricated using the same techniques as described earlier with respect to FIG. Figures 1 to 5 The memory cell 800 may include a back gate 802, a dielectric layer 804, a semiconductor layer 806, a ferromagnetic insulator 810, another ferromagnetic insulator 812, a gate dielectric 816, a control gate 818, a left gate 820, and a right gate 822. Thus, the memory cell 800 may include additional gates, a left gate 820 and a right gate 822. Each of these gates may be configured as an electrostatic gate. Applying a voltage to these gates may be configured to allow a single transmission channel through the semiconductor layer 806. In one example, the semiconductor layer 806 may be a gallium arsenide (GaAs) wire having a thickness of 10 nm. In this example, the semiconductor layer 806 may have a border with each of the ferromagnetic insulators that is approximately 50 nm to 100 nm long. The spin valve junction may be 20 nm to 50 nm long. Although Figure 8A certain number of layers of memory cell 800 are shown arranged in a certain manner, but there may be a greater or lesser number of layers arranged in a different manner.

[0037] With respect to the operation of memory cell 800, it may operate in a similar manner to memory cell 100, as described earlier with respect to Figure 6 and Figure 7 Explained. Electrons in the semiconductor layer 806 can carry supercurrents, which can undergo magnetization, and when the magnetizations of each of the two ferromagnetic insulators (e.g., ferromagnetic insulator 810 and ferromagnetic insulator 812) are in the same direction (e.g., parallel to each other), the phases accumulated during the transmission can be added. Alternatively, when the magnetizations of each of the two ferromagnetic insulators (e.g., ferromagnetic insulator 810 and ferromagnetic insulator 812) are in opposite directions (e.g., antiparallel to each other), the phases can be canceled. The changes in the amplitude and phase of the supercurrent can be similar to those described earlier with respect to Figure 6 and Figure 7 explained. In summary, the proximity effect on the magnetic insulator controls the amplitude and phase of the supercurrent, which depends on the strength of the magnetic splitting (e.g., Zeeman-induced splitting) and the geometry of the memory cell. In the example memory cell, the proximity effect is an effect that occurs at the interface of two materials—a superconducting electrode and a semiconductor layer. The semiconductor layer close to the superconducting electrode will inherit some of the properties of the superconductor because electrons can tunnel into the superconductor in a short time and sense the correlations present in the material. Therefore, proximity-induced superconductivity exists in the semiconductor layer associated with the memory cell. Electrons from the semiconductor layer tunnel into the ferromagnetic insulator in a short time and experience magnetic correlations.

[0038] Figure 9 FIG2 shows a diagram of a memory cell circuit 900 according to an example. In one example, the memory cell circuit 900 may include a memory storage element 902 including at least one memory cell device 910 (e.g., memory cell 100 or memory cell 700) and at least two Josephson junctions 912 and 914, such as Figure 9 Memory storage element 902 may further include a transformer 916. Transformer 916 may include two inductors 918 and 920. Memory storage element 902 may further include another transformer 922. Transformer 922 may include inductors 924 and 926. In one example, Josephson junctions 912 and 914 may form a readout superconducting quantum interference device (SQUID).

[0039] Continue to refer to Figure 9Memory cell circuit 900 can be coupled to word lines and bit lines to perform various memory operations, including, for example, read and write operations. As an example, a read word line (RWL) for performing a read operation can be coupled to memory cell circuit 900. In this example, the read word line (RWL) can be coupled via transformer 922. A write word line (WWL) for performing a write operation can be coupled to memory cell circuit 900. The write word line can be magnetically coupled to memory cell device 910. Additionally, a read bit line (RBL) for performing a read operation can be coupled to memory cell circuit 900. A write bit line (WBL) for performing a write operation can also be coupled to memory cell circuit 900. In this example, the write bit line (WBL) can be coupled via transformer 916. Memory cell device 910 can be used as a control mechanism to change the state of memory cell circuit 900. In one example, coupling with memory cell device 910 can allow the magnetization of a ferromagnetic insulator to be changed by applying a local write word line current and by applying a write bit line current.

[0040] In one example, the memory cell device 910 can be in a first state (e.g., corresponding to when the magnetization provided by the ferromagnetic insulator is parallel) and a second state (e.g., corresponding to when the magnetization provided by the ferromagnetic insulator is antiparallel). In at least one of these states, the memory cell device 910 can apply flux to JJ 912 and JJ 914, such that, under application of a word read current, due to the flux generated by the memory cell device 910 and the coupling of the word read current via the transformer 922, an induced current in the memory storage element 902 can combine with the applied bit read current to trigger the Josephson junctions 912 and 914, thereby sending the read SQUID to a voltage state. This voltage can generate a current along the read bit line, which can act as a transmission line with a certain impedance. This current can be sensed using a sense amplifier. In one example, once amplified by the sense amplifier, the presence or absence of the current pulse can determine the state of the memory cell circuit 900 as a logic low or a logic high.

[0041] In one example, during a write operation, the write word line (WWL) and the write bit line (WBL) can receive current from respective drivers. Figure 9 By applying flux to the loop (e.g., a transformer 916 in FIG. 1 ), the magnitude or sign of the supercurrent through the memory cell device 910 can be controlled and can be used to implement magnetic switching. Figure 9 A certain number of components are shown arranged in a certain manner, but the memory cell circuit 900 may include additional or fewer components arranged differently.

[0042] Figure 10 A computing system 100 is shown, according to one example, including a memory 1020 coupled to a processor 1010. Processor 1010 can perform read or write operations on memory 1020 in the manner explained earlier. Memory 1020 can be used as part of a storage device in a data center for delivering cloud-based services such as software as a service, platform as a service, or other services. Memory system 1020 can include an array 1002 of JMRAM memory cells arranged in rows and columns. In one example, array 1002 can be an array of memory cell circuits, such as memory cell circuit 900. Memory system 1020 can also include a row decoder 1018 that can be configured to decode row control / address signals. Row decoder 1018 can also be coupled to wordline drivers 1022. Wordline drivers 1022 can include circuitry for providing wordline read / write currents to a subset or all of the memory cells associated with a selected wordline for any read or write operation. Word line driver 1022 may provide this current via word line 1024 .

[0043] The memory system 1020 may also include a bus interface 1030 that may be configured to receive control signals or other signals from the processor 1010. The bus interface 1030 may also be coupled to a bit line driver 1032. The bit line driver 1032 may include circuitry for providing a bit line read current to a subset or all of the memory cells associated with a selected bit line for any read or write operation. The bit line driver 1032 may provide such current via a bit line 1034. The bit line 1034 may include a read bit line and a write bit line. In other words, different bit lines may be used to provide current to a selected memory cell for a read or write operation. Using a row address and a column address, any memory cell may be accessed using an address. Each of the bit lines (e.g., bit line 1034) may also be coupled to a sense amplifier 1004 for sensing the bit line to determine the logical state of each array in the memory cell array 1002. Although Figure 10 A certain number of components of computing system 1000 are shown arranged in a certain manner, but there may be a greater or lesser number of components arranged in a different manner.

[0044] In summary, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed adjacent to the semiconductor layer, wherein the first ferromagnetic insulator is disposed on a first side of the semiconductor layer, and wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed adjacent to the semiconductor layer, wherein the second ferromagnetic insulator is disposed on a second side of the semiconductor layer opposite the first side, and wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode.

[0045] Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the direction of the current flow or the magnitude of the current flow. Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the magnitude of the current flow.

[0046] Each of the first ferromagnetic insulator and the second ferromagnetic insulator may include europium sulfide or europium oxide. Each of the first ferromagnetic insulator and the second ferromagnetic insulator may include niobium.

[0047] The semiconductor layer may include gallium arsenide, indium arsenide, or indium antimonide. The memory cell may be configured to be in a logic high state or a logic low state, and the semiconductor-based magnetic spin valve may be configured to be in a 0 state or a π state among the two logic states of the memory cell.

[0048] In another example, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode. The semiconductor-based magnetic spin valve may further include a control gate disposed on top of the semiconductor layer, located between the first ferromagnetic insulator and the second ferromagnetic insulator, and configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator.

[0049] Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the direction of the current flow or the magnitude of the current flow. Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the magnitude of the current flow.

[0050] Each of the first ferromagnetic insulator and the second ferromagnetic insulator may include europium sulfide or europium oxide. Each of the first ferromagnetic insulator and the second ferromagnetic insulator may include niobium.

[0051] The semiconductor layer may include gallium arsenide, indium arsenide, or indium antimonide. The memory cell may be configured to be in a logic high state or a logic low state, and the semiconductor-based magnetic spin valve may be configured to be in a 0 state or a π state among the two logic states of the memory cell.

[0052] In yet another example, the present disclosure relates to a memory cell comprising a first superconducting electrode. The memory cell may further comprise a second superconducting electrode. The memory cell may further comprise a semiconductor-based magnetic spin valve coupled to the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may comprise a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction. The semiconductor-based magnetic spin valve may further comprise a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or in a second direction opposite the first direction, so as to control a parameter associated with the flow of current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode. The semiconductor-based magnetic spin valve may further comprise a first control gate configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator. The semiconductor-based magnetic spin valve may further include a second control gate configured to control a carrier density of the semiconductor layer.

[0053] Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the direction of the current flow or the magnitude of the current flow. Parameters associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode may include the magnitude of the current flow, and the second control gate may be further configured to control the magnitude of the current flow.

[0054] The first ferromagnetic insulator may be spaced apart from the second ferromagnetic insulator by a selected distance, and the selected distance may be selected to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator. The memory cell may further include a third control gate coupled to the first ferromagnetic insulator and a fourth control gate coupled to the second ferromagnetic insulator, wherein each of the third control gate and the fourth control gate may be configured to control carrier density near the semiconductor layer. The memory cell may be configured to be in a logic high state or a logic low state, and the semiconductor-based magnetic spin valve may be configured to be in a 0 state or a π state between the two logic states of the memory cell.

[0055] It is to be understood that the methods, modules and components described herein are merely exemplary. Alternatively or in addition, the functionality described herein can be performed at least in part by one or more hardware logic components. For example, and not limitation, the hardware logic components of the illustrative types that can be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs) and the like. In an abstract but still clear sense, any component arrangement that implements the same functionality is effectively "associated" so that the desired functionality is achieved. Therefore, any two components that are combined to implement specific functionality herein can be considered to be "associated" to each other so that the desired functionality is achieved, regardless of architecture or intermediate components. Similarly, any two components so associated can also be considered to be "operably connected" or "coupled" to each other to achieve the desired functionality.

[0056] The functionality associated with the examples described in this disclosure may also include instructions stored in non-transient media. As used herein, the term "non-transient media" refers to any medium that stores data and / or instructions that cause a machine to operate in a specific manner. Exemplary non-transient media may include non-volatile media and / or volatile media. Non-volatile media may include, for example, a hard disk, a solid-state drive, a magnetic disk or tape, an optical disk or optical tape, flash memory, EPROM, NVRAM, PRAM, or other such media or networked versions of such media. Volatile media may include, for example, dynamic memory such as DRAM, SRAM, cache, or other such media. Non-transient media is distinct from, but may be used in conjunction with, transmission media. Transmission media are used to transfer data and / or instructions to or from a machine. Exemplary transmission media may include coaxial cables, optical fibers, copper wire, and wireless media such as radio waves.

[0057] Furthermore, those skilled in the art will recognize that the boundaries between the functionality of the above-described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed among additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be altered in various other embodiments.

[0058] Although this disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as a key, required, or essential feature or element of any or all the claims.

[0059] In addition, the terms "a" or "an" as used herein are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as meaning that any particular claim containing such introduced claim element by the indefinite article "a" or "an" is limited to inventions containing only one such element, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an". The same applies to the use of definite articles.

[0060] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate spatial, temporal, or other prioritization of such elements.

Claims

1. A memory cell comprising: a first superconducting electrode; a second superconducting electrode; as well as A semiconductor-based magnetic spin valve is coupled to the first superconducting electrode and the second superconducting electrode, wherein the semiconductor-based magnetic spin valve comprises: a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode, a first ferromagnetic insulator disposed proximate the semiconductor layer, wherein the first ferromagnetic insulator is disposed on a first side of the semiconductor layer, and wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction, and a second ferromagnetic insulator disposed proximate the semiconductor layer, wherein the second ferromagnetic insulator is disposed on a second side of the semiconductor layer opposite the first side, and wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction, or a second direction opposite the first direction, so as to control a parameter associated with the flow of electric current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode; wherein phases accumulated during transmission are added when the magnetizations of the first ferromagnetic insulator and the second ferromagnetic insulator are in the same direction, and are canceled when the magnetizations of the first ferromagnetic insulator and the second ferromagnetic insulator are in opposite directions.

2. The memory cell of claim 1 , wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: the direction of the flow of the current or the magnitude of the flow of the current.

3. The memory cell of claim 1 , wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: the magnitude of said flow of said current. 4 . The memory cell of claim 1 , wherein each of the first ferromagnetic insulator and the second ferromagnetic insulator comprises europium sulfide or europium oxide. 5 . The memory cell of claim 1 , wherein each of the first and second superconducting electrodes comprises niobium.

6. The memory cell of claim 1, wherein the semiconductor layer comprises gallium arsenide, indium arsenide, or indium antimonide.

7. The memory cell of claim 1 , wherein the memory cell is configured to be in a logic high state or a logic low state, and wherein the semiconductor-based magnetic spin valve is configured to be in either a 0 state or a π state among the two logic states of the memory cell.

8. A memory cell comprising: a first superconducting electrode; a second superconducting electrode; as well as A semiconductor-based magnetic spin valve is coupled to the first superconducting electrode and the second superconducting electrode, wherein the semiconductor-based magnetic spin valve comprises: a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode, a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction, a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or a second direction opposite the first direction so as to control a parameter associated with the flow of electric current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode, and A control gate is disposed on top of the semiconductor layer, between the first ferromagnetic insulator and the second ferromagnetic insulator, and is configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator.

9. The memory cell of claim 8, wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: the direction of the flow of the current or the magnitude of the flow of the current.

10. The memory cell of claim 8, wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: the magnitude of said flow of said current.

11. The memory cell of claim 8, wherein each of the first ferromagnetic insulator and the second ferromagnetic insulator comprises europium sulfide or europium oxide.

12. The memory cell of claim 8, wherein each of the first and second superconducting electrodes comprises niobium.

13. The memory cell of claim 8, wherein the semiconductor layer comprises gallium arsenide, indium arsenide, or indium antimonide.

14. The memory cell of claim 8, wherein the memory cell is configured to be in a logic high state or a logic low state, and wherein the semiconductor-based magnetic spin valve is configured to be in a 0 state or a π state among the two logic states of the memory cell.

15. A memory cell comprising: a first superconducting electrode; a second superconducting electrode; as well as A semiconductor-based magnetic spin valve is coupled to the first superconducting electrode and the second superconducting electrode, wherein the semiconductor-based magnetic spin valve comprises: a semiconductor layer disposed between the first superconducting electrode and the second superconducting electrode, a first ferromagnetic insulator disposed on at least a first side of the semiconductor layer, wherein the first ferromagnetic insulator is configured to provide a fixed magnetization oriented in a first direction, a second ferromagnetic insulator disposed on at least a second side of the semiconductor layer opposite the first side, wherein the second ferromagnetic insulator is configured to provide a free magnetization oriented in the first direction or a second direction opposite to the first direction so as to control a parameter associated with the flow of current from the first superconducting electrode through the semiconductor layer to the second superconducting electrode, a first control gate configured to control coupling between the first ferromagnetic insulator and the second ferromagnetic insulator, and The second control gate is configured to control the carrier density of the semiconductor layer.

16. The memory cell of claim 15, wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: the direction of the flow of the current or the magnitude of the flow of the current.

17. The memory cell of claim 15, wherein the parameters associated with the flow of the current from the first superconducting electrode, through the semiconductor layer, to the second superconducting electrode include: an amplitude of the flow of the current, and wherein the second control gate is further configured to control the amplitude of the flow of the current.

18. The memory cell of claim 15, wherein the first ferromagnetic insulator is separated from the second ferromagnetic insulator by a selected distance, and wherein the selected distance is selected to control the coupling between the first ferromagnetic insulator and the second ferromagnetic insulator.

19. The memory cell of claim 15 , further comprising a third control gate coupled to the first ferromagnetic insulator and a fourth control gate coupled to the second ferromagnetic insulator, wherein each of the third control gate and the fourth control gate is configured to control carrier density near the semiconductor layer.

20. The memory cell of claim 15, wherein the memory cell is configured to be in a logic high state or a logic low state, and wherein the semiconductor-based magnetic spin valve is configured to be in a 0 state or a π state among the two logic states of the memory cell.

Images