Magnetic random access memory and electronic device

Abstract

A magnetic random access memory and an electronic device are provided to improve the storage density of the magnetic random access memory. The magnetic random access memory includes a plurality of structure units and a plurality of voltage control lines; the plurality of voltage control lines are parallel; planes on which the plurality of structure units are located are parallel, and a plane on which each structure unit of the plurality of structure units is located is perpendicular to the plurality of voltage control lines. Each structure unit includes a plurality of layers of storage structures stacked in sequence, each layer of storage structure of the plurality of layers of storage structures includes an electrode line and a plurality of storage units arranged on the electrode line, each storage unit of the plurality of storage units includes a magnetic tunnel junction, one end of each storage unit is connected to the electrode line, and the other end of each storage unit is connected to one voltage control line of the plurality of voltage control lines.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a magnetic random access memory and electronic device. Background Technology

[0002] The development of information technology has placed higher demands on storage media. Compared with traditional semiconductor storage technology, magnetic random access memory (MRAM), which uses magnetic tunnel junctions (MTJs) as storage units, is considered a high-density memory with broad application prospects due to its many excellent characteristics, such as non-volatility of stored data, fast read and write speeds, unlimited erase and write cycles, and low read and write power consumption.

[0003] The core storage unit of MRAM is the MTJ, and each MTJ consists of a free layer, a barrier layer, and a reference layer. When writing data into an MTJ, different data can be written by changing the direction of the magnetic moments of the free layer (i.e., controlling whether the magnetic moments of the free layer and the reference layer of the MTJ are parallel or antiparallel).

[0004] To increase the storage density of MRAM, one possible approach is to evolve the storage format of MRAM from two dimensions (2D) to three dimensions (3D). Figure 1 An MRAM consisting of a 3D stacked memory array is shown.

[0005] exist Figure 1In the 3D memory array shown, each memory cell consists of a series MTJ selector. When the selector is turned on, data can be written to the MTJ connected to it. One end of the memory cell is connected to the word line (WL), and the other end is connected to the bit line (BL). Writing to the MTJ utilizes the spin transfer torque (STT) effect. That is, electrons are spin-polarized when passing through the reference layer of the MTJ. These polarized electrons change the magnetic moment state of the free layer when passing through it, thereby changing the relative orientation (parallel or antiparallel) of the magnetic moments between the free layer and the reference layer, thus enabling data writing. Specifically, the selector's turn-on voltage can be between V and V / 2. The data writing method is as follows: a voltage V is applied between the WL and BL of the memory cell to be written. The selector of that memory cell is turned on, generating a current that flows through the MTJ. Under the STT effect, the magnetic moment of the free layer of the MTJ flips, completing the writing of data 0. Changing the voltage polarity (i.e., applying a voltage of -V between WL and BL) changes the current direction, corresponding to writing data 1. During the writing process, a small voltage, such as V / 2 or V / 3, is applied between WL and BL corresponding to non-written memory cells. This voltage is less than the selector's turn-on voltage, so the selector is in the off state and no current flows through MTJ.

[0006] use Figure 1 The 3D stacked memory array shown has a memory cell consisting of a series-connected selector and a metal-gate junction box (MTJ). Since the electrical characteristics of the selector need to be matched with the MTJ, finding a selector that matches the MTJ is difficult. Furthermore, in terms of the writing method, when writing data using the STT effect, the current needs to pass through the junction region (i.e., the barrier layer) of the MTJ, which can easily cause MTJ breakdown, reducing the stability of the memory cell.

[0007] In summary, there is an urgent need for a 3D stacked storage array solution to improve the storage density of MRAM and enhance the stability of storage cells. Summary of the Invention

[0008] This application provides a magnetic random access memory and an electronic device to improve the storage density of the magnetic random access memory.

[0009] In a first aspect, embodiments of this application provide a magnetic random access memory (MRM), which includes multiple structural units and multiple voltage control lines. In this MRM, each structural unit includes a multi-layered storage structure stacked sequentially. Each storage layer includes an electrode line and multiple storage cells disposed on the electrode line. Each storage cell includes a magnetic tunnel junction (MTJ), with one end connected to the electrode line and the other end connected to one of the multiple voltage control lines.

[0010] The magnetic random access memory (RAM) provided in the first aspect, where each structural unit includes a multi-layered storage structure, allows for 3D stacking of the storage structures, thereby increasing the storage density of the RAM. Figure 1 Compared to the 3D stacked memory array shown, no selector is needed in the memory cell, thus simplifying the cell structure. Furthermore, using the magnetic random access memory provided in the first aspect, writing to the memory cell can utilize the spin-orbit torque (SOT) effect and the voltage-controlled magnetic anisotropy (VCMA) effect. Specifically, a bias voltage is applied to the voltage control line connected to the magnetic tunnel junction, and the critical switching current density of the magnetic tunnel junction is changed using the VCMA effect. Simultaneously, current is passed through the electrode line connected to the magnetic tunnel junction, and the SOT effect causes the magnetic moment in the free layer to flip, achieving data writing. Compared to... Figure 1 Compared to the scheme shown, no current flows through the junction region (i.e., barrier layer) of the magnetic tunnel junction during data writing, thus resulting in higher stability of the magnetic tunnel junction. Furthermore, the magnetic random access memory provided in the first aspect includes only one magnetic tunnel junction per memory cell, thereby significantly reducing the fabrication difficulty of the memory cells and increasing the storage density of the magnetic random access memory.

[0011] In one possible design, multiple voltage control lines are arranged in parallel, multiple structural units are located in parallel planes, and each structural unit's plane is perpendicular to multiple voltage control lines.

[0012] Furthermore, in the magnetic random access memory provided in the first aspect, the resistance of each magnetic tunnel junction can be greater than or equal to 100 kΩ. When the resistance of the memory cell is much greater than the resistance of the electrode line, this can effectively prevent write current from flowing through the MTJ and reduce the influence of the creep path.

[0013] In one possible design, the way to write data to the magnetic random access memory provided by the first aspect can be: when writing data to the magnetic random access memory, the electrode lines are used to provide write current to a plurality of memory cells connected to the electrode lines, and each of the plurality of voltage control lines is used to provide a bias voltage to the plurality of memory cells connected to the electrode lines respectively.

[0014] In one possible design, the way to read data from the magnetic random access memory provided in the first aspect is as follows: when reading data from the magnetic random access memory, the electrode line is used to provide a grounding loop for a plurality of memory cells connected to the electrode line, and each of the plurality of voltage control lines is used to provide a read voltage or a read current to the plurality of memory cells connected to the electrode line respectively.

[0015] In the magnetic random access memory provided in the first aspect, the process of applying voltage or passing current through electrode lines can be achieved in different ways.

[0016] Method 1

[0017] In one possible design, the magnetic random access memory provided by the first aspect further includes a first bit line and a second bit line; wherein the first bit line, the second bit line, and a plurality of voltage control lines are parallel to each other; furthermore, each structural unit also includes a word line, a first transistor, and a second transistor; wherein the gates of the first transistor and the second transistor are respectively connected to the word line, the source of the first transistor is connected to the first bit line, the drain of the second transistor is connected to the second bit line, the drain of the first transistor is connected to a first end of an electrode line via a metal wire, and the source of the second transistor is connected to a second end of an electrode line via a metal wire.

[0018] Using the above scheme, the first and second transistors can be turned on by applying a gate bias voltage to the word line, and then a voltage or current can be applied to the electrode line by applying different voltages to the first and second bit lines.

[0019] In Method 1, when writing data to the magnetic random access memory, the word lines can apply gate bias voltages to the first transistor and the second transistor respectively; the first bit line is applied with a write voltage and the second bit line is grounded; among the multiple voltage control lines, the voltage control line connected to the memory cell that needs to be written with data is applied with a first bias voltage, and the voltage control line connected to the memory cell that does not need to be written with data is applied with a second bias voltage, wherein the first bias voltage and the second bias voltage are not equal.

[0020] The first bias voltage and the second bias voltage are different. In one example, the difference between the first bias voltage and the voltage of the electrode line is negative, and the difference between the second bias voltage and the voltage of the electrode line is positive or zero; in another example, the difference between the first bias voltage and the voltage of the electrode line is positive, and the difference between the second bias voltage and the voltage of the electrode line is negative or zero.

[0021] Using the above scheme, the first and second transistors can be turned on by applying a gate bias voltage to the word line. Then, by applying different voltages to the first and second bit lines, voltage or current can be applied to the electrode lines. Simultaneously, different voltages are applied to the voltage control lines connected to the memory cells that need to be written to and those connected to the memory cells that do not need to be written to, thus achieving data writing.

[0022] Specifically, when reading data from the magnetic random access memory, the word line can apply a gate bias voltage to the first transistor and the second transistor respectively, so that the first transistor and the second transistor are turned on; each of the multiple voltage control lines is used to apply a read voltage or read current to the corresponding connected memory cell, and to receive feedback information from the corresponding connected memory cell, which is used to indicate the data stored in the corresponding connected memory cell.

[0023] When each voltage control line applies a read voltage to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the current and capacitance of the memory cell. When the read voltage applied to each voltage control line is the same, the feedback current or capacitance will be different when the memory cell is in different resistance states. When each voltage control line applies a read current to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the voltage and capacitance of the memory cell. When the read current applied to each voltage control line is the same, the feedback voltage or capacitance will be different when the memory cell is in different resistance states.

[0024] In addition, the magnetic random access memory may also include multiple amplifiers that are connected one-to-one with multiple voltage control lines, each of which is used to read the feedback information received by the corresponding connected voltage control line.

[0025] Each amplifier and its surrounding resistors together form a readout circuit, used to read data from the storage cell corresponding to the voltage control line connected to the amplifier, based on feedback information. Specifically, each amplifier can determine whether the storage cell is in a high-resistance or low-resistance state by comparing the feedback information (e.g., voltage, current, capacitance, charge / discharge time) with a reference value, thereby determining the data stored in that storage cell.

[0026] Method 2

[0027] In another possible design, each structural unit may also include: a first bit line and a second bit line, the first bit line, the second bit line and the electrode line being parallel to each other, the first bit line being perpendicular to a plurality of voltage control lines, the second bit line being perpendicular to a plurality of voltage control lines, the first bit line being connected to the first end of the electrode line through a metal wire, and the second bit line being connected to the second end of the electrode line through a metal wire.

[0028] Using the above scheme, voltage or current can be applied to the electrode lines by applying different voltages to the first and second electrode lines.

[0029] In Method 2, when writing data to the magnetic random access memory, a write voltage is applied to the first bit line and the second bit line is grounded, or the first bit line is grounded and a write voltage is applied to the second bit line; a first bias voltage is applied to the voltage control line connected to the memory cell that needs to be written data among the multiple voltage control lines, and a second bias voltage is applied to the voltage control line connected to the memory cell that does not need to be written data among the multiple voltage control lines, wherein the first bias voltage and the second bias voltage are not equal.

[0030] The first bias voltage and the second bias voltage are different. In one example, the difference between the first bias voltage and the voltage of the electrode line is negative, and the difference between the second bias voltage and the voltage of the electrode line is positive or zero; in another example, the difference between the first bias voltage and the voltage of the electrode line is positive, and the difference between the second bias voltage and the voltage of the electrode line is negative or zero.

[0031] Using the above scheme, different voltages can be applied to the first and second bit lines to apply voltage or flow current to the electrode lines. Simultaneously, different voltages can be applied to the voltage control lines connected to the memory cells that need data writing and those connected to the memory cells that do not need data writing, thus enabling data writing.

[0032] Specifically, when reading data from the magnetic random access memory, each of the multiple voltage control lines is used to apply a read voltage or read current to the corresponding connected memory cell and to receive feedback information from the corresponding connected memory cell, which is used to indicate the data stored in the corresponding connected memory cell.

[0033] When each voltage control line applies a read voltage to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the current and capacitance of the memory cell. When the read voltage applied to each voltage control line is the same, the feedback current or capacitance will be different when the memory cell is in different resistance states. When each voltage control line applies a read current to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the voltage and capacitance of the memory cell. When the read current applied to each voltage control line is the same, the feedback voltage or capacitance will be different when the memory cell is in different resistance states.

[0034] In addition, the magnetic random access memory may also include multiple amplifiers that are connected one-to-one with multiple voltage control lines, each of which is used to read the feedback information received by the corresponding connected voltage control line.

[0035] Each amplifier and its surrounding resistors together form a readout circuit, used to read data from the storage cell corresponding to the voltage control line connected to the amplifier, based on feedback information. Specifically, each amplifier can determine whether the storage cell is in a high-resistance or low-resistance state by comparing the feedback information (e.g., voltage, current, capacitance, charge / discharge time) with a reference value, thereby determining the data stored in that storage cell.

[0036] In one possible design, in the magnetic random access memory provided in the first aspect, each magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer stacked sequentially, wherein the free layer is connected to an electrode line and the reference layer is connected to a voltage control line.

[0037] In a second aspect, embodiments of this application provide an electronic device including a processor and a magnetic random access memory coupled to the processor, provided in the first aspect and any possible design thereof.

[0038] Specifically, the processor can call software programs stored in the magnetic random access memory to execute corresponding methods and realize the corresponding functions of the electronic device. Attached Figure Description

[0039] Figure 1 A schematic diagram of a 3D stacked memory array for a magnetic random access memory provided by the prior art;

[0040] Figure 2 This is a schematic diagram of the structure of the first type of magnetic random access memory provided in the embodiments of this application;

[0041] Figure 3 This is a schematic diagram of the structure of a second type of magnetic random access memory provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of the structure of a third type of magnetic random access memory provided in an embodiment of this application;

[0043] Figure 5 This application provides a schematic diagram of the structure of an MTJ.

[0044] Figure 6 This is a schematic diagram of the structure of the fourth type of magnetic random access memory provided in the embodiments of this application;

[0045] Figure 7 A schematic diagram of reading and writing data in a magnetic random access memory provided in this application embodiment;

[0046] Figure 8 This is a schematic diagram of the structure of the fifth type of magnetic random access memory provided in the embodiments of this application;

[0047] Figure 9 A schematic diagram of another magnetic random access memory for reading and writing data provided in an embodiment of this application;

[0048] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0049] This application provides a magnetic random access memory and an electronic device to improve the storage density of the magnetic random access memory and enhance the stability of the storage cells.

[0050] The application scenarios of the embodiments of this application will be briefly introduced below.

[0051] The embodiments of this application can be applied to Figure 2 The magnetic random access memory shown includes control circuitry and at least one storage circuit.

[0052] Specifically, each storage circuit is used for writing and reading data. The control circuit is used to control the process of writing and reading data in the storage circuit. For example, when writing data, the control circuit selects the storage cell to be written to and applies a corresponding voltage and current to realize the writing of data in the selected storage cell. Similarly, when reading data, the control circuit selects the storage cell to be read from and applies a corresponding voltage and current to realize the reading of data from the selected storage cell.

[0053] Each storage circuit includes multiple storage units. A storage unit is the smallest unit in a magnetic random access memory that has data storage and read / write functions. It can be used to store a minimum unit of information, namely 1 bit of data (e.g., 0 or 1), which is a binary bit.

[0054] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0055] It should be noted that "multiple" in this application refers to two or more. Furthermore, it should be understood that the terms "first," "second," etc., used in the description of this application are used only for descriptive purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0056] See Figure 3 This is a schematic diagram of the structure of a magnetic random access memory (RAM) provided in an embodiment of this application. The RAM includes multiple structural units 301 and multiple voltage control lines 302. The multiple structural units 301 and multiple voltage control lines 302 can be considered as... Figure 2 The storage circuit in it.

[0057] Each structural unit 301 includes a multi-layer memory structure stacked sequentially. Each layer of the multi-layer memory structure includes an electrode line and multiple memory cells disposed on the electrode line. Each memory cell includes a magnetic tunnel junction (MTJ). One end of each memory cell is connected to the electrode line, and the other end is connected to one of the multiple voltage control lines.

[0058] Optionally, the multiple voltage control lines 302 are parallel; the planes in which the multiple structural units 301 are located are parallel, and the plane in which each structural unit 301 is located is perpendicular to the multiple voltage control lines 302.

[0059] It should be noted that, in the embodiments of this application, the concept of multiple voltage control lines 302 being parallel is not strictly parallel. During the fabrication process of magnetic random access memory, due to the influence of fabrication technology and equipment, it is possible that the multiple voltage control lines 302 are not strictly parallel. This situation is caused by the specific fabrication process and does not mean that the situation of multiple voltage control lines 302 not being strictly parallel exceeds the protection scope of this application. In addition, there is a similar understanding for the two positional relationships of planar parallelism and perpendicularity, which will not be elaborated here.

[0060] It should be noted that, Figure 3 This illustration uses three memory cells per electrode line as an example; in actual applications, the number of memory cells per electrode line is not specifically limited. Since the voltage control line 302 corresponds one-to-one with the memory cell, therefore... Figure 3 In the example, the number of voltage control lines 302 connected to the memory cells in each layer of the memory structure is also three. In actual applications, the number of voltage control lines 302 connected to the memory cells changes with the number of memory cells.

[0061] For ease of description, Figure 3 The magnetic random access memory shown illustrates an xyz coordinate system. Voltage control lines 302 are arranged parallel to the x-axis, electrode lines are arranged parallel to the y-axis, and the multi-layer storage structure is stacked sequentially along the z-axis. The plane containing each structural unit 301 is perpendicular to the x-axis.

[0062] In addition, Figure 3 The example only shows a scheme where multiple structural units 301 are repeatedly arranged along the x-axis. In practical applications, multiple structural units can also be repeatedly arranged along the y-axis, and correspondingly, each structural unit also has multiple connected voltage control lines. Because the structure and read / write principle of structural units repeatedly arranged along the y-axis are different from... Figure 3 The structural unit 301 shown is consistent with the one described above. In this embodiment, the structural unit that is repeatedly arranged along the y-axis will not be described in detail.

[0063] It should be understood that a storage cell is the smallest unit in a magnetic random access memory (MRM) that has data storage and read / write functions. It can be used to store a single unit of information, namely 1 bit of data (e.g., 0 or 1), which is a binary digit. Multiple storage cells can be used to store multiple binary digits of data. Specifically, in the embodiments of this application, a storage cell includes an MTJ for storing one binary digit. Each MTJ may include a free layer, a barrier layer, and a reference layer stacked sequentially along the positive z-axis. The magnetic moment direction of the reference layer is fixed, while the magnetic moment direction of the free layer can change during data writing. Different data is corresponding to the parallel or antiparallel arrangement of the magnetic moments of the free layer and the reference layer. The barrier layer is used to generate the tunneling magnetoresistance effect. Specifically, in this application, the free layer is connected to the electrode line, and the reference layer is connected to the voltage control line, such as... Figure 3 As shown. That is, the free layer is close to the electrode line connected to the MTJ, the reference layer is farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.

[0064] It should be understood that Figure 3 The structure of the magnetic random access memory shown is merely an example. In practical applications, there is no specific limitation on whether the MTJ is on the electrode line or below the electrode line. For example, in another example, the structure of the magnetic random access memory provided in this application embodiment can be as follows: Figure 4 As shown. In Figure 4 In the magnetic random access memory shown, the MTJs are arranged in the opposite direction to the z-axis, and correspondingly, the position of the voltage control line 302 connected to the MTJs also changes. It should be noted that in... Figure 4 In the example, the free layer in the MTJ is close to the electrode line, the reference layer is farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.

[0065] For ease of description, in the following examples, we will use... Figure 3 The structure shown is used as an example for explanation. Figure 4 The specific implementation method and read / write principle of the structure shown are the same as those of the structure shown. Figure 3 Similar examples will not be repeated in this application.

[0066] The magnetic random access memory provided in this application utilizes the SOT effect and VCMA effect when writing data, and the tunnel magneto resistance (TMR) effect when reading data.

[0067] The SOT effect works as follows: when current is passed through the electrode wires, an upward (i.e., towards the positive z-axis) spin-polarized current is generated and diffuses into the free layer of the MTJ. When the current reaches a certain value (critical flip current density), the magnetic moment of the free layer flips under the influence of the spin-orbit interaction torque, enabling data writing. Changing the direction of the current in the electrode wires changes the polarization direction of the spin current, and the flip direction of the magnetic moment of the free layer also changes accordingly, enabling the writing of different data. The VCMA effect works as follows: applying a bias voltage across the MTJ can change the interface charge density between the free layer and the barrier layer, thereby changing the vertical anisotropy and coercivity of the free layer, and thus reducing the critical flip current density of the MTJ. By utilizing the VCMA effect to reduce the critical flip current density of the MTJ, and simultaneously passing current through the electrode wires, the magnetic moment in the free layer flips under the combined action of the SOT and VCMA effects, enabling data writing. This writing method can significantly reduce the power consumption of data writing.

[0068] In practical applications, electrode wires can be made of heavy metal materials or other materials that can generate spin flow. Electrode wires can also be called SOT electrode wires.

[0069] For example, Figure 3 The structure of the MTJ in the magnetic random access memory shown can be as follows: Figure 5 As shown. From Figure 5 As can be seen, the free layer of the MTJ is connected to the electrode line, and the reference layer of the MTJ is connected to the voltage control line 302. By applying voltage or current to the voltage control line 302 through a voltage source or current source, and by passing current into the electrode line, a voltage difference can be created between the voltage on the voltage control line 302 and the voltage on the electrode line. This voltage difference is the bias voltage applied across the MTJ.

[0070] Specifically, in this embodiment, when writing data to the magnetic random access memory (MRJ), the voltage control line 302 independently performs selective operation on the MTJ connected to it. For example, a first bias voltage can be applied to the voltage control line connected to the memory cell to be written, reducing the critical switching current density of the memory cell to be written. A second bias voltage can be applied to the voltage control line connected to the non-writing memory cell, increasing (or not changing) the critical switching current density of the non-writing memory cell. At the same time, a write current is passed through the electrode line connected to the memory cell to be written (different directions of current can write different data), generating an upward (i.e., towards the positive z-axis) diffusing spin current into the free layer of the MTJ, thereby realizing the writing of data to the memory cell to be written.

[0071] The principle of the TMR effect is as follows: when the magnetic moments of the free layer and the reference layer of the MTJ are aligned in parallel, the MTJ is in a low-resistance state; when the magnetic moments of the free layer and the reference layer are antiparallel (i.e., parallel and opposite in direction), the MTJ is in a high-resistance state. High and low resistance represent two different data states, such as 0 or 1; different data can be read from the high-resistance or low-resistance state of the MTJ.

[0072] Specifically, in the embodiments of this application, when reading data from a magnetic random access memory, the electrode line connected to the memory cell to be read is used to provide a grounding loop for the memory cell, a read voltage or read current is applied to the voltage control line 302 connected to the memory cell to be read, and the data information carried by the memory cell to be read is obtained through the readout loop (e.g., including an amplifier) ​​connected to the voltage control line 302.

[0073] For example, by reading the output voltage of the amplifier in the circuit, it can be determined whether the MTJ corresponding to the voltage control line 302 connected to the amplifier is in a high-impedance state or a low-impedance state, and then it can be determined whether the data stored in the MTJ is 0 or 1.

[0074] To prevent current from flowing through the MTJ during data writing and forming a sneak path that could affect the accuracy of the written data, in this embodiment, the MTJ can have high resistance characteristics, for example, the resistance value of the MTJ is not less than 100KΩ, making the resistance value of the MTJ much greater than the resistance value of the electrode line. This can effectively prevent the writing current from flowing through the MTJ and reduce the impact of the sneak path.

[0075] In addition, Figure 3 In the magnetic random access memory shown, the magnetic moments of the free layer and the reference layer are arranged in parallel or antiparallel directions. Specifically, the magnetic moments of the free layer and the reference layer can lie in the xy plane, be perpendicular to the xy plane, or be at a certain angle to the xy plane. In this embodiment, the magnetic moments of the free layer and the reference layer are not specifically limited, as long as they are arranged in parallel or antiparallel directions.

[0076] As mentioned earlier, data can be written to or read from the magnetic random access memory by applying voltage or current to the voltage control line 302 and the electrode line. In practical applications, there are various ways to apply voltage and apply current. The following describes two specific embodiments.

[0077] Example 1

[0078] In Embodiment 1, the process of applying voltage or flowing current onto the electrode lines can be achieved by two transistors connected to two bit lines respectively. One bit line is connected to one end of the electrode line through a transistor, and the other bit line is connected to the other end of the electrode line through another transistor. The on and off states of the two transistors are controlled by word lines. Applying gate bias voltages to the two transistors on the word lines turns them on, and applying different voltages to the two bit lines allows for the application of voltage or the flow of current onto the electrode lines.

[0079] Specifically, in one possible implementation, Figure 3 The magnetic random access memory shown may further include: a first bit line and a second bit line; each structural unit 301 further includes a word line, a first transistor, and a second transistor. The gates of the first transistor and the second transistor are respectively connected to the word line, the source of the first transistor is connected to the first bit line, the drain of the second transistor is connected to the second bit line, the drain of the first transistor is connected to the first end of the electrode line via a metal wire, and the source of the second transistor is connected to the second end of the electrode line via a metal wire.

[0080] The metal wire can be made of the same material as the electrode wire or a different material. The first transistor and the second transistor can be N-type metal-oxide-semiconductor (NMOS) transistors. Of course, the first transistor and the second transistor can also be other types of transistors, such as P-type metal-oxide-semiconductor (NMOS) transistors. This application does not specifically limit the types of transistors used.

[0081] It is easy to see that in Embodiment 1, the gates of the first transistor and the second transistor are respectively connected to the word line. The word line can be used to provide gate bias voltages for the first transistor and the second transistor, so that the first transistor and the second transistor are turned on. By applying different voltages to the first bit line and the second bit line respectively, current can flow through the electrode lines, that is, to provide write current for the memory cells on the electrode lines.

[0082] Since the first transistor can be connected to the first end of all electrode lines in a structural unit through a metal wire, and the second transistor can be connected to the second end of all electrode lines in a structural unit through another metal wire, the scheme of Embodiment 1 can provide write current in parallel for all electrode lines in a structural unit.

[0083] Specifically, in Embodiment 1, when writing data to the magnetic random access memory, the voltage or current applied to the first bit line, the second bit line, the word line, and the voltage control line can be applied in the following manner: the word line applies a gate bias voltage to the first transistor and the second transistor respectively, so that the first transistor and the second transistor are turned on; the first bit line is applied with a write voltage, and the second bit line is grounded; the voltage control line 302 connected to the memory cell that needs to be written with data among the plurality of voltage control lines 302 is applied with a first bias voltage, and the voltage control line 302 connected to the memory cell that does not need to be written with data among the plurality of voltage control lines 302 is applied with a second bias voltage, wherein the first bias voltage and the second bias voltage are not equal.

[0084] The first bias voltage is used to reduce the critical switching current density of the memory cell to be written to, while the second bias voltage is used to increase (or not change) the critical switching current density of the memory cell not to be written to. The values ​​of the first and second bias voltages are different, and their specific values ​​can be determined based on the specific structure and material parameters of the memory cell. That is, when the first bias voltage is applied to the voltage control line 302, data can be written to the memory cell connected to the voltage control line 302; when the second bias voltage is applied to the voltage control line 302, data cannot be written to the memory cell connected to the voltage control line 302.

[0085] In a specific example, the difference between the first bias voltage and the voltage of the electrode line is negative, and the difference between the second bias voltage and the voltage of the electrode line is positive or zero; or, the difference between the first bias voltage and the voltage of the electrode line is positive, and the difference between the second bias voltage and the voltage of the electrode line is negative or zero.

[0086] When writing data to a memory cell, the required current direction in the electrode line can be determined according to the data to be written (0 or 1). The required current is then supplied to the electrode line by applying the corresponding voltage to the first bit line, the second bit line, and the word line. At the same time, a first bias voltage is applied to the voltage control line 302 connected to the memory cell to which data needs to be written, and a second bias voltage is applied to the voltage control line 302 connected to the memory cell to which data does not need to be written, thereby realizing the process of writing data to a memory cell.

[0087] Furthermore, when reading data from the magnetic random access memory, all data stored in all storage units of a certain structural unit 301 can be read at once.

[0088] Reading data from the memory cell utilizes the TMR effect. When reading data from the magnetic random access memory, a gate bias voltage is applied to the first transistor and the second transistor respectively on the word line, causing the first transistor and the second transistor to conduct; each of the plurality of voltage control lines 302 is used to apply a read voltage or read current to the corresponding connected memory cell, and to receive feedback information from the corresponding connected memory cell, which is used to indicate the data stored in the corresponding connected memory cell.

[0089] When each voltage control line applies a read voltage to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the current and capacitance of the memory cell. When the read voltage applied to each voltage control line is the same, the feedback current or capacitance will be different when the memory cell is in different resistance states. When each voltage control line applies a read current to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the voltage and capacitance of the memory cell. When the read current applied to each voltage control line is the same, the feedback voltage or capacitance will be different when the memory cell is in different resistance states.

[0090] In addition, the magnetic random access memory may also include multiple amplifiers that are connected one-to-one with multiple voltage control lines, each of which is used to read the feedback information received by the corresponding connected voltage control line.

[0091] Each amplifier and its peripheral resistors together form a readout circuit, which is used to provide feedback information to the storage cell corresponding to the voltage control line connected to the amplifier, thereby reading the data in the storage cell.

[0092] Specifically, each amplifier can determine whether the memory cell is in a high-resistance state or a low-resistance state by comparing the feedback information of the memory cell (such as voltage, current, capacitance, and charge / discharge time) with reference values, thereby determining the data stored in the memory cell.

[0093] In practical applications, when writing data to the magnetic random access memory (MRMemory), the process of applying voltage or applying current to the first bit line, second bit line, word line, and voltage control line 302 can be controlled by a level control circuit configured in the MRMemory. This level control circuit provides the required voltage or current to the first bit line, second bit line, word line, and voltage control line 302. Similarly, when reading data from the MRMemory, the process of applying voltage or applying current to the voltage control line 302 can also be controlled by the same level control circuit, which provides the required voltage or current to the voltage control line 302.

[0094] In addition, the magnetic random access memory may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell through word lines and bit lines when writing or reading data. The aforementioned level control circuit can determine the voltage or current to be applied to the first bit line, the second bit line, and the word line according to the selection of the row address decoding circuit and the column address decoding circuit, so as to realize the read and write operation of one or more memory cells selected by the row address decoding circuit and the column address decoding circuit.

[0095] Among them, the level control circuit, the row address decoding circuit, and the column address decoding circuit can be collectively referred to as the control circuit.

[0096] For example, Figure 6 A schematic diagram of a possible structure of the magnetic random access memory provided in Embodiment 1 is shown. Figure 6 The magnetic random access memory shown is illustrated by arranging three structural units (also called cells) periodically along the x-axis. Each structural unit includes three layers of storage structure, and each layer of storage structure includes three storage cells. In practical applications, there are no specific limitations on the number of structural units, the number of layers of storage structure, or the number of storage cells in each layer of storage structure.

[0097] exist Figure 6 In the magnetic random access memory (MTJ) shown, two NMOS transistors (NMOS1 and NMOS2) in a cell share a single wire (WL). WL connects to the gate of the NMOS transistor and controls its on / off state. One end of NMOS1 (NMOS2) is connected to BL (SL), and the other end is connected to an electrode line via a metal wire. The voltage control line on each MTJ is parallel to BL (SL) and perpendicular to WL and the electrode line. Different cells arranged along the x-axis share BL, SL, and the voltage control line, with each cell containing one WL. Each voltage control line is connected to a sense amplifier (SA) for reading data stored in the MTJ. Figure 6 Only one SA is shown in the text, actually Figure 6 The magnetic random access memory shown may include nine SAs, each connected to one of nine voltage control lines. BL(SL) is selected via a row address decoding circuit, and WL is selected via a column address decoding circuit; alternatively, BL(SL) is selected via a column address decoding circuit, and WL is selected via a row address decoding circuit.

[0098] As mentioned earlier, when current flows through the electrode lines in different directions, different data (e.g., 0 or 1) can be written to the storage cells on the electrode lines. Therefore, in... Figure 6In the example, to flow current along the y-axis in the electrode line, BL can be considered the first bit line, NMOS1 the first transistor, SL the second bit line, and NMOS2 the second transistor. The voltage applied to BL is greater than the voltage applied to SL, resulting in a current path of BL→NMOS1→metal wire (parallel to the z-axis)→electrode line→metal wire (parallel to the z-axis)→NMOS2→SL, i.e., a current flowing along the y-axis in the electrode line (for example, data 0 or 1 can be written at this time). To flow current along the -y-axis in the electrode line, SL can be considered the first bit line, NMOS2 the first transistor, BL the second bit line, and NMOS1 the second transistor. The voltage applied to SL is greater than the voltage applied to BL, resulting in a current path of SL→NMOS2→metal wire (parallel to the z-axis)→electrode line→metal wire (parallel to the z-axis)→NMOS1→BL, i.e., a current flowing along the -y-axis in the electrode line (for example, data 1 or 0 can be written at this time).

[0099] Figure 7 It shows Figure 6 The diagram shows the principle of reading and writing data in a single cell of a magnetic random access memory.

[0100] When writing data to a Media Transfer Jet (MTJ), the row address decoding circuit (or column address decoding circuit) first locates the gate level (WL) of the cell containing the MTJ. The level control circuit applies a gate bias voltage to the WL based on the selection of the row address decoding circuit (or column address decoding circuit), turning on the two NMOS transistors (NMOS1 and NMOS2) in that cell. The level control circuit then applies a write voltage between the BL and SL lines based on the selection of the column address decoding circuit (or row address decoding circuit) (positive and negative voltages can write different data), applying a first bias voltage to the voltage control line above the MTJ to be written to and a second bias voltage to the voltage control line of the non-MTJs being written to. Under the combined effect of the VCMA and SOT effects, the free-layer magnetic moment of the MTJ to be written to flips, while the magnetic moment orientation of the non-MTJs remains unchanged, thus completing the data writing process in the MTJ to be written to.

[0101] When reading data from the magnetic random access memory (MRMemory), all data stored in all MTJs within the cell can be read at once: the level control circuit applies a gate bias voltage to the WL within the cell according to the selection of the row address decoding circuit (or column address decoding circuit), and NMOS1 and NMOS2 are turned on. Simultaneously, a read voltage or current is applied to each voltage control line 302, ensuring that each MTJ within the cell is contained in an independent readout loop. The SA in each readout loop reads the data stored in the MTJ by identifying the resistance value of the MTJ.

[0102] Example 2

[0103] In Embodiment 2, the process of applying voltage or flowing current onto the electrode line can be achieved using two bit lines, one connected to one end of the electrode line and the other connected to the other end. Applying different voltages to the two bit lines allows for the application of voltage or the flow of current onto the electrode line. Unlike Embodiment 1, in Embodiment 2, it is not necessary to control the transistor to be turned on via a word line before applying voltage or current onto the electrode line; instead, voltage or current is directly applied to the electrode line by applying different voltages to the two bit lines.

[0104] Specifically, in one possible implementation, in Figure 3 In the magnetic random access memory shown, the structural unit 301 may further include a first bit line and a second bit line. The first bit line, the second bit line and the electrode line are parallel to each other. The first bit line is perpendicular to the plurality of voltage control lines 302, and the second bit line is perpendicular to the plurality of voltage control lines 302. The first bit line is connected to the first end of the electrode line through a metal wire, and the second bit line is connected to the second end of the electrode line through a metal wire.

[0105] The metal wire can be made of the same material as the electrode wire, or it can be made of a different material.

[0106] It is easy to see that in Embodiment 2, the first bit line is connected to the first end of the electrode line via a metal wire, and the second bit line is connected to the second end of the electrode line via a metal wire. Therefore, applying different voltages to the first bit line and the second bit line respectively allows current to flow through the electrode line, thus providing write current for the memory cell on the electrode line. When the voltage difference between the first bit line and the second bit line is positive or negative, currents in different directions can be passed through the electrode line, thereby writing different data into the memory cell.

[0107] Since the first bit line can be connected to the first end of all electrode lines in a structural unit through a metal wire, and the second bit line can be connected to the second end of all electrode lines in a structural unit through another metal wire, the scheme of Embodiment 2 can provide write current in parallel for all electrode lines in a structural unit 301.

[0108] Specifically, in Embodiment 2, when writing data to the magnetic random access memory, the voltage or current applied to the first bit line, the second bit line, and the voltage control line can be applied in the following manner: the first bit line is applied with a write voltage and the second bit line is grounded, or the first bit line is grounded and the second bit line is applied with a write voltage; the voltage control line 302 connected to the memory cell that needs to be written with data is applied with a first bias voltage, and the voltage control line 302 connected to the memory cell that does not need to be written with data is applied with a second bias voltage, wherein the first bias voltage and the second bias voltage are not equal.

[0109] The first bias voltage is used to reduce the critical switching current density of the memory cell to be written to, while the second bias voltage is used to increase (or not change) the critical switching current density of the memory cell not to be written to. The values ​​of the first and second bias voltages are different, and their specific values ​​can be determined based on the specific structure and material parameters of the memory cell. That is, when the first bias voltage is applied to the voltage control line 302, data can be written to the memory cell connected to the voltage control line 302; when the second bias voltage is applied to the voltage control line 302, data cannot be written to the memory cell connected to the voltage control line 302.

[0110] In a specific example, the difference between the first bias voltage and the voltage of the electrode line is negative, and the difference between the second bias voltage and the voltage of the electrode line is positive or zero; or, the difference between the first bias voltage and the voltage of the electrode line is positive, and the difference between the second bias voltage and the voltage of the electrode line is negative or zero.

[0111] When writing data to a memory cell, the direction of the current required in the electrode line can be determined based on the data to be written (0 or 1), thereby determining whether to apply the write voltage on the first bit line or the second bit line; at the same time, a first bias voltage is applied to the voltage control line 302 connected to the memory cell to which data needs to be written, and a second bias voltage is applied to the voltage control line 302 connected to the memory cell to which data does not need to be written, thereby realizing the process of writing data to a memory cell.

[0112] Furthermore, when reading data from the magnetic random access memory, data stored in all storage cells of a certain structural unit 301 can be read at once.

[0113] Reading data from the memory cell utilizes the TMR effect. When reading data from the magnetic random access memory (MRMemory), each of the plurality of voltage control lines 302 applies a read voltage or read current to the corresponding connected memory cell and receives feedback information from the corresponding connected memory cell, indicating the data stored in the corresponding connected memory cell. The first and second bit lines can be grounded, thereby providing a ground loop.

[0114] When each voltage control line applies a read voltage to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the current and capacitance of the memory cell. When the read voltage applied to each voltage control line is the same, the feedback current or capacitance will be different when the memory cell is in different resistance states. When each voltage control line applies a read current to the corresponding connected memory cell, the feedback information from the memory cell can be information such as the voltage and capacitance of the memory cell. When the read current applied to each voltage control line is the same, the feedback voltage or capacitance will be different when the memory cell is in different resistance states.

[0115] In addition, the magnetic random access memory may also include multiple amplifiers that are connected one-to-one with multiple voltage control lines, each of which is used to read the feedback information received by the corresponding connected voltage control line.

[0116] Each amplifier and its peripheral resistors together form a readout circuit, which is used to provide feedback information to the storage cell corresponding to the voltage control line connected to the amplifier, thereby reading the data in the storage cell.

[0117] Specifically, each amplifier can determine whether the memory cell is in a high-resistance state or a low-resistance state by comparing the feedback information of the memory cell (such as voltage, current, capacitance, and charge / discharge time) with reference values, thereby determining the data stored in the memory cell.

[0118] In practical applications, when writing data to the magnetic random access memory (RAM), the process of applying voltage or current to the first bit line, the second bit line, and the voltage control line 302 can be controlled by a level control circuit configured in the RAM. This level control circuit provides the required voltage or current to the first bit line, the second bit line, and the voltage control line 302. Similarly, when reading data from the RAM, the process of applying voltage or current to the voltage control line 302 can also be controlled by the same level control circuit, which provides the required voltage or current to the voltage control line 302.

[0119] Furthermore, in Embodiment 2, the voltage control line 302 can also serve as a word line in the magnetic random access memory (MRM). The MLM may also include row address decoding circuits and column address decoding circuits, used to select the corresponding memory cell via word lines and bit lines when writing or reading data. The aforementioned level control circuit can determine the voltage or current to be applied to the first bit line, the second bit line, and the voltage control line 302 based on the selection of the row address decoding circuit and the column address decoding circuit, thereby enabling read / write operations on one or more memory cells selected by the row address decoding circuit and the column address decoding circuit.

[0120] Among them, the level control circuit, the row address decoding circuit, and the column address decoding circuit can be collectively referred to as the control circuit.

[0121] For example, Figure 8 A schematic diagram of a possible structure of the magnetic random access memory provided in Embodiment 2 is shown. Figure 8 The example provided illustrates a magnetic random access memory (RAM) comprising three structural units (also called cells), each structural unit consisting of three layers of storage structures, and each storage structure containing three storage cells. In practical applications, there are no specific limitations on the number of structural units, the number of storage structure layers, or the number of storage cells in each storage structure layer.

[0122] exist Figure 8 In the magnetic random access memory shown, each cell is connected to BL and BL' at both ends. Switching between write voltage and ground via BL and BL' provides write current in different directions in parallel to all electrode lines within that cell. Each voltage control line 302 is connected to SA for reading data stored in the MTJ. Figure 8 Only one SA is shown in the text, actually Figure 8 The magnetic random access memory shown may include nine SAs, each connected to one of nine voltage control lines 302. BL(BL') is selected by a row address decoding circuit, and the voltage control lines are selected by a column address decoding circuit; or, BL(BL') is selected by a column address decoding circuit, and the voltage control lines are selected by a row address decoding circuit.

[0123] Wherein, BL can be regarded as the first bit line in Embodiment 2, and BL' can be regarded as the second bit line in Embodiment 2.

[0124] Figure 9 It shows Figure 8 The diagram shows the principle of reading and writing data in a single cell of a magnetic random access memory.

[0125] When writing data to an MTJ, the row address decoding circuit (or column address decoding circuit) first locates the BL and BL' of the cell containing the MTJ. The level control circuit, based on the selection of the row address decoding circuit (or column address decoding circuit), connects BL and BL' to Vop and Gnd respectively, thus generating a write current in all electrode lines within the cell. Simultaneously, the level control circuit, based on the selection of the column address decoding circuit (or row address decoding circuit), applies a first bias voltage to the voltage control line 302 above the MTJ to be written, while applying a second bias voltage to the voltage control line of the non-written MTJ. Under the combined effect of the VCMA and SOT effects, the free layer magnetic moment of the MTJ to be written flips, while the magnetic moment orientation of the non-written MTJ remains unchanged, thereby completing the data writing in the MTJ to be written.

[0126] When reading data from the magnetic random access memory, all the data stored in all MTJs in the cell can be read at once: the level control circuit applies the read voltage or read current to each voltage control line 302 according to the selection of the column address decoding circuit (or row address decoding circuit), and connects BL and BL' in the cell to Gnd (providing a ground loop), so that each MTJ in the cell is contained in an independent read loop. The SA in each read loop reads the data stored in the MTJ by identifying the resistance value of the MTJ.

[0127] The magnetic random access memory (RAM) provided in this application, where each structural unit includes a multi-layered storage structure, allows for 3D stacking of storage structures, thereby increasing the storage density of the RAM. Figure 1 Compared to the 3D stacked memory array shown, no selector is needed in the memory cell, thus simplifying the cell structure. Furthermore, using the magnetic random access memory provided in this embodiment, writing to the memory cell can utilize the SOT and VCMA effects. Specifically, a bias voltage is applied to the voltage control line connected to the magnetic tunnel junction, and the VCMA effect is used to change the critical switching current density of the magnetic tunnel junction. Simultaneously, current is passed through the electrode line connected to the magnetic tunnel junction, and the SOT effect is used to cause the magnetic moment in the free layer to flip, thereby achieving data writing. Compared to... Figure 1 Compared to the scheme shown, no current flows through the junction region (i.e., barrier layer) of the magnetic tunnel junction when writing data, thus resulting in higher stability of the magnetic tunnel junction. Furthermore, using the magnetic random access memory provided in this application embodiment, each memory cell includes only one magnetic tunnel junction, thereby significantly reducing the fabrication difficulty of the memory cell and increasing the storage density of the magnetic random access memory.

[0128] Based on the same inventive concept, embodiments of this application also provide an electronic device. See also Figure 10 The electronic device includes a processor 1001 and a magnetic random access memory 1002 coupled to the processor. The magnetic random access memory 1002 may be... Figure 3 The magnetic random access memory shown.

[0129] Specifically, the processor 1001 can call the software program stored in the magnetic random access memory 1002 to execute the corresponding method and realize the corresponding function of the electronic device.

[0130] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A magnetic random access memory, characterized in that, It includes multiple structural units and multiple voltage control lines; Each of the structural units includes a multi-layer storage structure stacked sequentially. Each layer of the multi-layer storage structure includes an electrode line and a plurality of storage cells disposed on the electrode line. Each of the plurality of storage cells includes a magnetic tunnel junction. One end of each storage cell is connected to the electrode line, and the other end is connected to one of the plurality of voltage control lines. The magnetic random access memory further includes: The first bit line and the second bit line; the first bit line, the second bit line, and the plurality of voltage control lines are parallel to each other; Each structural unit further includes a word line, a first transistor, and a second transistor. The gates of the first transistor and the second transistor are respectively connected to the word line. The source of the first transistor is connected to the first bit line, and the drain of the second transistor is connected to the second bit line. The drain of the first transistor is connected to the first end of the electrode line through a metal wire, and the source of the second transistor is connected to the second end of the electrode line through a metal wire.

2. The magnetic random access memory as described in claim 1, characterized in that, The plurality of voltage control lines are parallel; the planes in which the plurality of structural units are located are parallel, and the plane in which each of the plurality of structural units is located is perpendicular to the plurality of voltage control lines.

3. The magnetic random access memory as described in claim 1, characterized in that, When writing data to the magnetic random access memory, the word lines apply gate bias voltages to the first transistor and the second transistor respectively; the first bit line is applied with a write voltage and the second bit line is grounded; among the plurality of voltage control lines, the voltage control line connected to the memory cell to which data needs to be written is applied with a first bias voltage, and the voltage control line connected to the memory cell to which data does not need to be written is applied with a second bias voltage, wherein the first bias voltage and the second bias voltage are not equal.

4. The magnetic random access memory as described in claim 1, characterized in that, When reading data from the magnetic random access memory, the word lines apply gate bias voltages to the first transistor and the second transistor, respectively; each of the plurality of voltage control lines is used to apply a read voltage or read current to the corresponding connected memory cell, and to receive feedback information from the corresponding connected memory cell, the feedback information being used to indicate the data stored in the corresponding connected memory cell.

5. The magnetic random access memory as described in claim 4, characterized in that, Also includes: Multiple amplifiers are connected one-to-one with the multiple voltage control lines, and each of the multiple amplifiers is used to read the feedback information received by the corresponding connected voltage control line.

6. The magnetic random access memory as claimed in claim 1, characterized in that, Each structural unit also includes: The first bit line and the second bit line are parallel to each other, the first bit line is perpendicular to the plurality of voltage control lines, the second bit line is perpendicular to the plurality of voltage control lines, the first bit line is connected to the first end of the electrode line through a metal wire, and the second bit line is connected to the second end of the electrode line through a metal wire.

7. The magnetic random access memory as described in claim 6, characterized in that, When writing data to the magnetic random access memory, a write voltage is applied to the first bit line and the second bit line is grounded, or the first bit line is grounded and the write voltage is applied to the second bit line; a first bias voltage is applied to the voltage control line connected to the memory cell that needs to be written data among the plurality of voltage control lines, and a second bias voltage is applied to the voltage control line connected to the memory cell that does not need to be written data among the plurality of voltage control lines, wherein the first bias voltage and the second bias voltage are not equal.

8. The magnetic random access memory as described in claim 6 or 7, characterized in that, When reading data from the magnetic random access memory, each of the plurality of voltage control lines is used to apply a read voltage or read current to the corresponding connected memory cell and to receive feedback information from the corresponding connected memory cell, the feedback information being used to indicate the data stored in the corresponding connected memory cell.

9. The magnetic random access memory as described in claim 8, characterized in that, Also includes: Multiple amplifiers are connected one-to-one with the multiple voltage control lines, and each of the multiple amplifiers is used to read the feedback information received by the corresponding connected voltage control line.

10. The magnetic random access memory according to any one of claims 1 to 7, characterized in that, Each magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer stacked sequentially. The free layer is connected to the electrode line, and the reference layer is connected to the voltage control line.

11. The magnetic random access memory according to any one of claims 1 to 7, characterized in that, When writing data to the magnetic random access memory, the electrode lines are used to provide write current to the plurality of memory cells connected to the electrode lines, and each of the plurality of voltage control lines is used to provide bias voltage to the plurality of memory cells connected to the electrode lines respectively.

12. The magnetic random access memory according to any one of claims 1 to 7, characterized in that, When reading data from the magnetic random access memory, the electrode line is used to provide a grounding loop for the plurality of memory cells connected to the electrode line, and each of the plurality of voltage control lines is used to provide a read voltage or a read current to the plurality of memory cells connected to the electrode line, respectively.

13. The magnetic random access memory according to any one of claims 1 to 7, characterized in that, The resistance of each magnetic tunnel junction is greater than or equal to 100KΩ.

14. An electronic device, characterized in that, It includes a processor and a magnetic random access memory coupled to the processor as described in any one of claims 1 to 13.

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