Inductive capacitance measuring device and terminal equipment

Abstract

The application provides an inductive capacitance measuring device and a terminal device. The inductive capacitance measuring device comprises an amplifier having a first input end, a second input end and an output end; a feedback capacitor connected between the first input end and the output end of the amplifier; a first pulse signal connected with the second input end of the amplifier; and a compensation circuit connected with the first input end of the amplifier, which provides charges for the inductive capacitance multiple times in a control period of the first pulse signal, compensates for the parasitic capacitance multiple times, reduces the capacitance value of the required compensation capacitor, reduces the area of the touch display chip and reduces the chip cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitive sensing recognition, and particularly relates to an inductive capacitance measuring device and a terminal device. BACKGROUND

[0002] At present, a capacitive sensing recognition system is widely applied to a projective capacitive touch screen, a touch pad and a fingerprint recognition and the like human-computer interaction application. Its principle is to convert a capacitance value into an electric signal amount (voltage, current and the like) through an inductive capacitance measuring device. For a touch screen application, a finger pressing will cause a change of a size of an inductive capacitance at a corresponding position, and an electric signal size output by the inductive capacitance measuring device is also different from that when there is no touch, so that whether a touch occurs and position information thereof are judged.

[0003] In an existing capacitive touch screen control chip, many adopt a technology that a touch panel is installed on a display device such as a liquid crystal display (LCD). A common electrode in the liquid crystal display (LCD) is divided into many small blocks as inductive electrodes for touch screen control.

[0004] When a touch point is detected, the common electrode as the inductive electrode will have a large parasitic capacitance, including a parasitic of a wire and a parasitic of a source line (source line) and a gate line (gate line) of a display panel in the liquid crystal display. Due to the parasitic capacitance, the inductive capacitance measuring device cannot directly amplify a change amount of the detection capacitance. If only the gain of the inductive capacitance measuring device is increased, the inductive capacitance measuring device will be saturated. When an absolute value of the change amount of the detection capacitance relative to a total capacitance is very small, this will usually make an effective dynamic range of the inductive capacitance small, affecting touch control collection effect. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide an inductive capacitance measuring device and a terminal device, to reduce the influence of the parasitic capacitance on touch control detection, to reduce the area of a compensation capacitance in a compensation path, to also reduce the area of a touch control display chip, and to reduce chip cost.

[0006] According to an aspect of the present application, an inductive capacitance measuring device is provided, comprising: an amplifier having a first input end, a second input end and an output end; a feedback capacitance connected between the first input end and the output end of the amplifier; a first pulse signal connected with the second input end of the amplifier; and a compensation circuit connected with the first input end of the amplifier, which provides electric charges for the inductive capacitance multiple times in a control period of the first pulse signal.

[0007] Preferably, the control period of the first pulse signal comprises a first time period and a second time period.

[0008] a first time period and a second time period, respectively, comprising an overall reset phase and an overall integration phase, and an N number of compensation circuit reset phases, an N number of compensation circuit integration phases, wherein N is an even number not less than 4, the compensation circuit providing charges to the sensing capacitor in the compensation circuit reset phases and the compensation circuit integration phases.

[0009] Preferably, further comprising: a first switch connected between the first input terminal and the output terminal of the amplifier; a second switch connected between a common point between the sensing capacitor and the compensation circuit and the first input terminal of the amplifier, wherein the first switch S1 is in a conducting state and the second switch S2 is in a non-conducting state; the first switch S1 is in a non-conducting state and the second switch S2 is in a conducting state.

[0010] Preferably, in the overall integration phase, the first pulse signal level flips, and the first switch transitions from a conducting state to a non-conducting state; in the overall signal reset phase, the first switch transitions from a non-conducting state to a conducting state.

[0011] Preferably, the compensation circuit comprises a third switch, a fourth switch, a fifth switch, a compensation capacitor, and a second pulse signal; the second pulse signal is provided to the first input terminal of the amplifier via the fifth switch and the compensation capacitor connected in series; a first voltage is provided to a common point of the fifth switch and the compensation capacitor via the third switch; the fourth switch is connected between the common point between the fifth switch and the compensation capacitor and a ground terminal.

[0012] Preferably, in the compensation circuit reset phase, the fifth switch transitions from a conducting state to a non-conducting state; in the compensation circuit integration phase, the fifth switch transitions from a non-conducting state to a conducting state.

[0013] Preferably, in the compensation circuit phase in the first time period, when the fifth switch is in a conducting state, the third switch is in a non-conducting state; when the fifth switch is in a non-conducting state, the third switch is in a conducting state, and the conducting and non-conducting states of the fifth switch are synchronized with the second pulse signal; in the compensation circuit phase in the second time period, when the fifth switch is in a conducting state, the fourth switch is in a non-conducting state; when the fifth switch is in a non-conducting state, the fourth switch is in a conducting state, and the conducting and non-conducting states of the fifth switch are synchronized with the second pulse signal in an inverted manner.

[0014] Preferably, the second pulse signal is a square wave signal, which jumps between a ground voltage and the first voltage.

[0015] Preferably, the first input terminal is a negative input terminal, and the second input terminal is a positive input terminal.

[0016] Preferably, the first input terminal is a positive input terminal, and the second input terminal is a negative input terminal.

[0017] According to another application of the present application, a terminal device is provided, wherein the terminal device comprises the inductive capacitance measuring device as described above.

[0018] The inductive capacitance measuring device provided by the present application comprises: an amplifier having a first input terminal, a second input terminal and an output terminal; a feedback capacitance connected between the first input terminal and the output terminal of the amplifier; a first pulse signal connected to the second input terminal of the amplifier; and a compensation circuit connected to the first input terminal of the amplifier, which provides charges to the inductive capacitance multiple times in a control period of the first pulse signal, thereby reducing the capacitance value of the required compensation capacitance by compensating the parasitic capacitance multiple times, so as to reduce the area of the touch display chip and lower the chip cost. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A structure schematic diagram of the inductive capacitance measuring device provided by an embodiment of the present application is shown.

[0021] Figure 2 A signal timing diagram of the inductive capacitance measuring device according to the prior art is shown.

[0022] Figure 3 A signal timing diagram of the inductive capacitance measuring device provided by an embodiment of the present application is shown.

[0023] Figure 4 A signal timing diagram of the inductive capacitance measuring device provided by another embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Various embodiments of the present application will be described in detail with reference to the drawings, wherein the same or like components or modules are denoted by the same or similar reference numerals. For the sake of clarity, each part in the drawings is not drawn in proportion.

[0025] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements storing instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements between the two.

[0026] Also, certain terms have been used herein for the purpose of reference only and thus are not intended to be limiting. For example, terms such as "upper", "lower", "bottom" and "top", are used only to facilitate discussion of the principles of the application and are not a requirement that the device be constructed or operated in any particular orientation. Terms such as "first", "second", "third", etc., are used only to facilitate discussion of the principles of the application and are not a requirement that the device be constructed or operated in any particular order or sequence.

[0027] Furthermore, equivalence to terms such as "first" and "second" are intended to distinguish one entity or operation from another, but not necessarily imply any actual relationship or order between such entities or operations. Moreover, the terms "include", "have", or any other similar term are intended to encompass non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not required to comprise only those elements in the list, but can include other elements not expressly listed, or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the stated element.

[0028] Figure 1 A structure diagram of an induced capacitance measuring device according to an embodiment of the present application is shown.

[0029] As shown in Figure 1 , the induced capacitance measuring device according to the embodiment of the present application comprises an amplifier 21, a feedback capacitance C fb , a first switch S1, a second switch S2, a first pulse signal V STIM , and a compensation circuit 22. An induced capacitance Cs of a capacitance induction identification system is connected to a first input end of the amplifier 21; the first pulse signal V STIM is connected to a second input end of the amplifier 21. The front-end feedback capacitance C fb and the first switch S1 are connected in parallel between the first input end and an output end of the amplifier 21.

[0030] In addition, the amplifier 21 comprises a first input, a second input and an output. For example, the amplifier 21 can be a common differential amplifier, the first input of which can be a negative input and the second input can be a positive input, or vice versa. The first switch S1 is connected between the first input of the amplifier and the output, and the second switch S2 is connected between the common point between the sensing capacitor and the compensation circuit and the first input of the amplifier.

[0031] The sensing capacitor Cs is the sensing capacitor between the touch panel and the common electrode, and the touch will cause the sensing capacitor Cs to change, and the change is The first pulse signal V STIM The full range of the system voltage can be repeatedly used in the whole control period. The compensation circuit 22 is connected to the first input of the amplifier 21, and when the first switch S1 is in the off state and S2 is in the on state, it provides the sensing capacitor Cs with electric charge.

[0032] The sensing capacitor measurement device further comprises a parasitic capacitor C base1 and C base2 , C base1 represents the parasitic capacitor of the sensing electrode and the source line and the gate line of the display panel, and C base2 represents the parasitic capacitor of the sensing electrode to the ground.

[0033] Figure 2 The signal timing diagram of the sensing capacitor measurement device according to the prior art is shown.

[0034] The touch detection principle of the sensing capacitor measurement device is that the touch panel is first pre-charged, and then connected to the charge amplifier 21, so that the charge of the sensing electrode RX is transferred to the output of the charge amplifier. Since the pre-charged voltage is constant, when the sensing electrode RX changes, the output voltage Vout of the charge amplifier is different. When a finger touches the touch panel, the equivalent capacitance of the sensing electrode RX becomes larger, so that the output voltage Vout of the charge amplifier 22 also becomes larger,

[0035] That is, the output voltage change of the charge amplifier 22 is: ……………………………(1)

[0036] In this way, whether there is a touch can be detected according to the change of the output voltage Vout of the charge amplifier.

[0037] Since the parasitic capacitances C base1 and C base2Very large (up to several hundred pF), so that the output of the charge amplifier 22 is saturated, in order to make the charge amplifier 22 work in the linear region, the need to induce the electrode RX parasitic capacitance C base1 And C base2 Compensation, so that the charge amplifier 22 receives the equivalent input capacitance is relatively small.

[0038] In the prior art, in the structure diagram of the induced capacitance measuring device as Figure 1 Shown, mainly through the parasitic capacitance C base1 Between the sensing electrode and the source line and the gate line of the display panel and the second input end of the charge amplifier 22 using a same phase excitation signal V STIM To eliminate the parasitic capacitance C base1 .

[0039] For the elimination of the parasitic capacitance C base2 , a capacitance compensation circuit 21 (as shown in the dashed box) is used. This capacitance compensation circuit 21 pre-charges the internal compensation capacitor C nge At Ts1 stage, and then at Ts2, the pre-charged charge is introduced into the sensing electrode RX, for details see the timing of each signal in the accompanying Figure 2 The fifth switch C nge And the second switch S2 of the capacitance compensation circuit 21 are the same in timing, which is represented by the timing of S2 in the figure, and the timing of each signal described above meets the purpose of eliminating the parasitic capacitance. This technical feature is a conventional technical means in the field, and will not be described in detail here.

[0040] In the prior art, since the compensation capacitor C nge Can be several pF or even 10 pF, the larger the capacitance value of the compensation capacitor, the larger the volume of the capacitor, and dozens of such capacitor compensation circuits 21 are integrated in the chip at the same time, occupying a considerable chip area and increasing the chip cost.

[0041] Figure 3 The signal timing diagram of the induced capacitance measuring device according to an embodiment of the present application is shown.

[0042] As shown in Figure 3 In this embodiment, the control period Tctrl of the first pulse signal V STIM Includes a first time period Ts1 and a second time period Ts2. The first time period Ts1 and the second time period Ts2 each include N time periods. The first pulse signal V STIM When the level is flipped within the control period Tctrl, the first switch S1 transitions from the on state to the off state. The first pulse signal V STIMThe level is flipped in the first time period Ts1 and the second time period Ts2, and the first switch S1 is switched from off to on at the end of the first time period Ts1 and the second time period Ts2.

[0043] In the embodiment, the compensation circuit 22 comprises a third switch C nge _S1A, a fourth switch C nge _S1B, a fifth switch C nge _S2, and a compensation capacitor C nge The second pulse signal is provided to a common point m between the fifth switch C nge _S2 and the compensation capacitor C nge The second pulse signal is, for example, a square wave signal, which jumps between 0 and the first voltage VDDA, and applies a ground voltage or the first voltage VDDA on the lower plate of the compensation capacitor C nge .

[0044] The first voltage VDDA is provided to the common point m between the fifth switch C nge _S2 and the compensation capacitor C nge The fourth switch C nge _S1B is connected between the common point m between the fifth switch C nge _S2 and the compensation capacitor C nge and the ground terminal GND. The second pulse signal has the same or different amplitude as the first pulse signal V STIM .

[0045] In the embodiment, the second switch S2 is off when the first switch S1 is on, and the second switch S2 is on when the first switch S1 is off.

[0046] The first time period Ts1 in which the first pulse signal V STIM jumps from low to high comprises multiple stages.

[0047] Specifically, the T1 stage (corresponding to the numeral mark in the drawing) in the first time period Ts1, i.e. the overall reset stage, in which the positive terminal of the amplifier 21 is connected to the low of the first pulse signal V STIM , the first switch S1 connected in parallel with the feedback capacitor C fb is on, and the amplifier 21 is connected in the form of a buffer; the lower plate of the parasitic capacitor C base1 is connected to the low of the first pulse signal V STIM ; and the compensation capacitor C nge is connected to the high of the first pulse signal V nge .the upper plate of the compensation capacitor C nge The lower plate of the compensation capacitor C

[0048] In the T2 stage (corresponding to the numeral mark in the drawing) in the first time period Ts1, i.e. the overall integration phase, the upper plate of the compensation capacitor C fb The first switch S1 in parallel is turned off, and the voltage at the second input terminal of the amplifier 21 is changed from low level to high level by the first pulse signal V STIM The lower plate of the compensation capacitor C base1 The excitation signal V STIM The lower plate of the compensation capacitor C nge The upper plate of the compensation capacitor C

[0049] In the overall integration phase, the first pulse signal level is flipped, and the first switch is switched from the on state to the off state; in the overall signal reset phase, the first switch is switched from the off state to the on state, which is the overall phase.

[0050] In the T3 stage (corresponding to the numeral mark in the drawing) in the first time period Ts1, i.e. the compensation circuit reset phase, in the compensation circuit reset phase, the upper plate of the compensation capacitor C nge The first input terminal of the amplifier 21 is connected through the fifth switch C nge The S2 switch is turned off, and the first input terminal of the amplifier 21 is connected through the third switch C nge The S1A switch is connected to the first voltage VDDA, and the lower plate voltage of the compensation capacitor C nge The lower plate voltage of the compensation capacitor C

[0051] In the T4 stage (corresponding to the numeral mark in the drawing) in the first time period Ts1, i.e. the compensation circuit integration phase, in the compensation circuit integration phase, the third switch C nge The S1A switch is turned off, and the upper plate of the compensation capacitor C nge The first input terminal of the amplifier 21 is connected through the fifth switch C nge The S2 switch is connected to the amplifier 22, and the lower plate voltage is changed from ground to the first voltage VDDA.

[0052] As shown in the drawing, the first time period Ts1 can also include T5, T6, …, T(N-1), TN, where N is an even number, for example, the odd stages T5, T7, …, T(N-1) in the subsequent multiple stages are connected to the first voltage VDDA, and the even stages T6, T8, …, TN-2 are connected to the ground. The compensation circuit integrates the phase stage and the T3 stage in the first time period Ts1, and the even stages T6, T8,..., TN in the subsequent stages are consistent with the T4 stage in the first time period Ts1. The compensation circuit 21 provides charges for the sensing capacitor in the compensation circuit reset stage and the compensation circuit integration phase stage.

[0053] In the pulse signal V STIM The second time period Ts2 from the high level to the low level includes multiple stages.

[0054] Specifically, in the T1 stage (corresponding to the number mark in the figure) in the first time period Ts2, that is, the overall reset stage, the positive terminal of the amplifier 21 is connected to the low level of the first pulse signal V STIM The first switch S1 connected in parallel with the feedback capacitor C fb is turned on, and the amplifier 21 is connected in the form of a buffer; the lower plate of the parasitic capacitor C base1 is connected to the high level of the first pulse signal V STIM The upper plate of the compensation capacitor C nge is connected to the ground through the fourth switch C nge _S1B, and the lower plate is connected to the first voltage VDDA.

[0055] In the T2 stage (corresponding to the number mark in the figure) in the first time period Ts2, that is, the overall integration phase stage, the first switch S1 connected in parallel with the feedback capacitor C fb is turned off, and the second input voltage of the amplifier 21 is jumped from the high level of the first pulse signal V STIM to the low level; at the same time, the excitation signal V base1 applied to the parasitic capacitor C STIM is also jumped from the high level to the low level; the upper plate of the compensation capacitor C nge is connected to the first input of the amplifier 21, and the lower plate voltage is jumped from the first voltage VDDA to the ground.

[0056] In the T3 stage (corresponding to the number mark in the figure) in the first time period Ts2, that is, the compensation circuit reset stage, the upper plate of the compensation capacitor C nge is disconnected from the first input of the amplifier 21 through the fifth switch C nge _S2 switch, and is connected to the ground through the third switch C nge _S1B, and the lower plate voltage of the compensation capacitor C nge is jumped from the ground to the first voltage VDDA.

[0057] In the T4 stage (corresponding to the numeral mark in the drawing) in the first time period Ts2, i.e. the compensation circuit integration phase stage, the fourth switch C nge _S1B is turned off, and the compensation capacitor C nge The upper plate is connected to the fifth switch C nge _S2 is connected to the amplifier 22, and the lower plate voltage jumps from the first voltage VDDA to ground.

[0058] As shown in the drawing, the first time period Ts2 can further include T5, T6, …, T(N-1), TN, where N is an even number, for example, the odd stages T5, T7, …, T(N-1) in the subsequent multiple stages are connected to the fifth switch C The compensation circuit 21 provides the induced capacitor with charges in the compensation circuit reset stage and the compensation circuit integration phase stage multiple times. The odd stages T5, T7, …, T(N-1) in the subsequent multiple stages are consistent with the T3 stage in the first time period Ts2, and the even stages T6, T8, …, TN in the subsequent multiple stages are consistent with the T4 stage in the first time period Ts2.

[0059] In the compensation circuit stage in the first time period, the fifth switch C nge _S2 is in the on state, the third switch C nge _S1A is in the off state; the fifth switch C nge _S2 is in the off state, the third switch C nge _S1A is in the on state, and the fifth switch C nge _S2 is in the on state and the off state synchronously with the second pulse signal;

[0060] In the compensation circuit stage in the second time period, the fifth switch C nge _S2 is in the on state, the fourth switch C nge _S1B is in the off state; the fifth switch C nge _S2 is in the off state, the fourth switch C nge _S1B is in the on state, and the fifth switch C nge _S2 is in the on state and the off state synchronously with the second pulse signal.

[0061] The 2N stages in the above first time period Ts1 and the second time period Ts2 complete a complete sampling quantization of the excitation signal V STIM period, and N is in the range of: and is an even number.

[0062] In the integration phase of the above one detection period, the compensation capacitor C nge is connected to the fifth switch Cnge S2 is off, and the third switch C nge S1A / fourth switch C nge S1B is on, and the second pulse signal jumps to make the compensation capacitor C nge The lower plate changes back to low / high level, thereby recharging the compensation capacitor C nge ; each time after recharging, the third switch C nge S1A / fourth switch C nge S1B, the fifth switch C nge S2, and the compensation capacitor C nge The lower plate becomes high / low level. In this way, the compensation capacitor C nge is switched between the two states of recharging and reconnection to the amplifier 21 several times to achieve a smaller compensation C nge for the parasitic capacitance Cbase2.

[0063] Referring to Figure 1 and Figure 3 explain the working principle of the embodiment of the application.

[0064] Specifically, V STIM is taken as an example of jumping from low to high level, where and represent the low and high voltage levels of V respectively;

[0065] In the T1 stage in the first time period Ts1, that is, the overall reset stage, the first switch S1 is on, V STIM is at low potential, and the charge at the first input end of the amplifier 21 is:

[0066] ……………………………(2)

[0067] In the T2 stage in the first time period Ts1, that is, the overall integration phase, the first switch S1 is off, the low level of the first pulse signal V STIM jumps to high level, and the upper plate of the compensation capacitor Cnge is connected to the first input end of the amplifier 21. In this stage, the charge at the first input end of the amplifier 21 is:

[0068] (3)

[0069] In the T3 stage in the first time period Ts1, that is, the compensation circuit reset stage, the upper plate of the compensation capacitor C nge is connected to the first voltage VDDA, and the lower plate voltage jumps from the first voltage VDDA to ground. In this stage, the charge at the upper plate of C nge is:

[0070] ……………………………(4)

[0071] T4 stage in the first time period Ts1, i.e. the phase of compensating circuit integrating phase, the compensating capacitor C nge The upper plate is connected to the fifth switch C nge The lower plate voltage jumps from ground to the first voltage VDDA, and the compensating capacitor C nge The charge of the upper plate is:

[0072] ……………………………(5)

[0073] After experiencing a reset and integration cycle of the compensating circuit, the compensating capacitor C nge The total charge additionally obtained by the upper plate is formula (5) minus formula (4):

[0074] ……………………………(6)

[0075] According to the above formula (6), after experiencing (N-2) / 2 reset and integration cycles of the compensating circuit, the compensating capacitor C nge The total charge additionally obtained by the upper plate is:

[0076] ……………………………(7)

[0077] Suppose the compensation target value is This value can be adjusted according to actual conditions, and this value is selected here for ease of calculation. When the compensation target value is the above value, according to the law of conservation of charge, let formula (3) plus formula (7) equal formula (2), we get:

[0078] ……………………………(8)

[0079] Let Simplify formula (8) to get:

[0080] ……………………………(9)

[0081] As can be seen from formula (9), the more the compensation times N, the smaller the compensating capacitor C nge required. At the same time, according to the law of conservation of charge, let formula (2) equal formula (3), according to the law of conservation of charge, the size of the compensating capacitor C nge required in the prior art method is:

[0082] ……………………………(10)

[0083] Comparing formula (9) and formula (10), it can be seen that the embodiment passed by the application reduces the compensation capacitor to

[0084] times of the original, thereby reducing the area of the chip. The touch circuit part in the current touch display single-chip ITD (Integrated-touch-driver) occupies about 30% of the area of the compensation capacitor, and if this method is used, more than 15% of the area will be reduced.

[0085] The touch circuit part in the current touch display single-chip ITD (Integrated-touch-driver) occupies about 30% of the area of the compensation capacitor, and if this method is used, more than 15% of the area will be reduced.

[0086] The inductive capacitance measuring device provided by the application is used for detecting the inductive capacitance of a capacitive inductive recognition system. By setting a compensation circuit at the input end of an amplifier, the change amount of the inductive capacitance is quantified / amplified by the amplifier, the dynamic range and signal-to-noise ratio of the system are greatly improved, and by compensating the parasitic capacitance multiple times, the capacitance value of the required compensation capacitor is reduced, so that the area of the touch display chip is reduced and the cost of the chip is reduced.

[0087] In a preferred embodiment, the inductive capacitance measuring device further comprises a compensation calibration module 23, which is used for adjusting the second pulse signal or the compensation capacitor C nge of the compensation circuit according to the signal Vout at the output end of the amplifier 21 to adjust the compensation amount of the compensation circuit.

[0088] In this embodiment, the compensation calibration module 23 comprises an analog-to-digital converter (ADC) 231 and a digital control unit 232. The analog-to-digital converter 231 is connected to the output end of the amplifier 21, and the digital control unit 232 is connected between the analog-to-digital converter 231 and the compensation circuit 22, and is used for receiving the output voltage Vout from the output end of the amplifier 21 via the analog-to-digital converter 231, adjusting the second pulse signal or the compensation capacitor C nge to adjust the compensation amount of the compensation circuit 22 and the reset and integration cycle times of the compensation circuit.

[0089] For the adjustment of the second pulse signal, for example, it is realized by a digital-to-analog converter DAC, which will not be described here again; for the adjustment of the compensation capacitor C nge , for example, it is realized by a capacitor array and switch selection; and for the reset and integration cycle times of the compensation circuit, it can be realized by timing control, which will not be described here again.

[0090] ​In the embodiments of the present application, a terminal device is also provided, which comprises a display device and a sensing capacitance measurement device for obtaining touch information. The display device is, for example, selected from any one of a liquid crystal display, an LED display, an AMOLED display, a quantum dot display, electronic paper, and a MicroLED display. The sensing capacitance measurement device is installed on the terminal device. Specifically, the terminal device can be any one of a smartphone, a smartwatch, a tablet computer, a notebook computer, an all-in-one computer, and an access control display device, and the present application does not limit this.

[0091] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details and do not limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made based on the above description. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The scope of protection of the present application should be defined by the scope of the claims of the present application and their equivalents.

Claims

1. An inductive capacitance measuring device, comprising: an amplifier having a first input, a second input and an output; a feedback capacitor connected between the first input and the output of the amplifier; a first pulse signal connected to the second input of the amplifier; a compensation circuit connected to the first input of the amplifier, which provides charge to the inductive capacitor multiple times in a control period of the first pulse signal, wherein the compensation circuit comprises a third switch, a fourth switch, a fifth switch, a compensation capacitor and a second pulse signal; the second pulse signal is provided to the first input of the amplifier via the fifth switch and the compensation capacitor connected in series; a first voltage is provided to a common point of the fifth switch and the compensation capacitor via the third switch; the fourth switch is connected between the common point between the fifth switch and the compensation capacitor and a ground terminal, the control period of the first pulse signal comprises a first time period and a second time period, the first time period and the second time period respectively comprise an overall reset phase and an overall integration phase, and one compensation circuit reset phase, one compensation circuit integration phase, wherein N is an even number not less than 4, the compensation circuit provides the induction capacitor with charges multiple times in the compensation circuit reset phase and the compensation circuit integration phase.

2. The inductive capacitance measuring device according to claim 1, further comprising: a first switch connected between the first input and the output of the amplifier; a second switch connected between a common point between the inductive capacitor and the compensation circuit and the first input of the amplifier, wherein the first switch S1 is in an on state and the second switch S2 is in an off state when the first switch S1 is in an off state and the second switch S2 is in an on state.

3. The inductive capacitance measuring device according to claim 2, wherein in the whole integration phase, the first pulse signal level flips and the first switch transitions from an on state to an off state; in the whole signal reset phase, the first switch transitions from an off state to an on state.

4. The inductive capacitance measuring device according to claim 3, wherein in the compensation circuit reset phase, the fifth switch transitions from an on state to an off state; in the compensation circuit integration phase, the fifth switch transitions from an off state to an on state.

5. The inductive capacitance measuring device according to claim 4, wherein in the compensation circuit phase in the first time period, the third switch is in an off state when the fifth switch is in an on state and the third switch is in an on state when the fifth switch is in an off state, and the on and off states of the fifth switch are synchronized with the second pulse signal; in the compensation circuit phase in the second time period, the fourth switch is in an off state when the fifth switch is in an on state and the fourth switch is in an on state when the fifth switch is in an off state, and the on and off states of the fifth switch are synchronized with the second pulse signal in an inverted manner.

6. The inductive capacitance measuring device of claim 1, wherein, the second pulse signal is a square wave signal jumping between a ground voltage and the first voltage.

7. The device according to any of claims 1-6, wherein the device is a device for measuring the capacitance of an inductor. the first input is a negative input and the second input is a positive input.

8. The device according to any of claims 1-6, wherein the device is a device for measuring the capacitance of an inductor. the first input is a positive input and the second input is a negative input.

9. A terminal device, wherein, the terminal device comprises the inductive capacitance measuring device according to any one of claims 1-8.

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