A parameter extraction modeling method suitable for discrete devices after dicing

Abstract

The present invention relates to a parameter extraction modeling method suitable for discrete devices after dicing, comprising: connecting a left pad, a device to be tested after dicing and a right pad into a GSG on-chip test structure by gold wire bonding; measuring and obtaining the capacitive compensation parameters of the left and right compensation networks caused by the left and right pads; determining the inductive compensation parameters of the left and right compensation networks caused by the gold wire wires of the gold wire bonding based on the through distances between the left and right pads and the device to be tested respectively; determining the S parameters of the left and right compensation networks according to the inductive compensation parameters and capacitive compensation parameters of the left and right compensation networks; adding the S parameters of the left and right compensation networks to the input and output ends of the test calibration compensation data of the vector network analyzer respectively, so as to remove the wiring influence of the GSG on-chip test structure. The present invention can quickly and effectively obtain an accurate large signal model, avoiding the model changes caused by the unevenness between the chips of the device process.

Description

Technical Field

[0001] The present invention relates to the field of on-wafer testing technology, and in particular to a parameter extraction and modeling method suitable for discrete devices after dicing. Background Art

[0002] With the development and application of radio frequency devices, especially the widespread application of wide bandgap compound semiconductor devices, the operating frequency of the circuit has increased, the output power has increased, and the efficiency requirement is accurate to 1%. Therefore, the design of power amplifier circuits, especially hybrid power amplifier circuits, has higher and higher requirements for models.

[0003] Device models are the basis of circuit design. Power amplifier circuit design relies on accurate device models, especially nonlinear large signal models. Accurate device models can significantly shorten the circuit design cycle, improve the design success rate, and reduce costs.

[0004] In addition to the traditional silicon-based LDMOS and GaAs-based pHEMT, the RF power devices currently used are increasingly widely used with gallium nitride (GaN) devices with higher power density. However, the large signal models of these new materials are not mature, and the failure analysis and defect structure of the new materials are not clear. There is still room for improvement in the process. This results in the accuracy of the model not meeting the design requirements, especially due to the uniformity between chips and the diversity of sizes. When we choose the tube core size in circuit design, we need to make real-time adjustments. Commercial tube cores do not have a connection form that can be tested on-chip, and can only be tested one-to-one through external circuits and bonding wires. The pad structure and bonding wires added to the auxiliary test during the test will add parasitic parameters to the on-chip test structure. The additional parasitic parameters affect the accurate modeling of the device. In order to improve the accuracy of circuit design, the influence of parasitic parameters must be removed during the parameter modeling process. Summary of the invention

[0005] In view of the above analysis, the present invention aims to provide a parameter extraction modeling method suitable for discrete devices after dicing, solve the influence of parasitic parameters on modeling accuracy, and realize accurate modeling of devices.

[0006] The technical solution provided by the present invention is:

[0007] A parameter extraction modeling method applicable to discrete devices after dicing, comprising the following steps:

[0008] Connect the left pad, the device under test after dicing and the right pad into a GSG on-wafer test structure by gold wire bonding;

[0009] The capacitive compensation parameters of the left and right compensation networks caused by the left and right pads are measured;

[0010] Determine the inductive compensation parameters of the left and right compensation networks caused by the gold wires of the gold wire bonding based on the through distances Lm and Ln between the left and right pads and the device under test respectively;

[0011] Determine the S parameters of the left and right compensation networks according to the inductive compensation parameters and capacitive compensation parameters of the left and right compensation networks;

[0012] The S parameters of the left and right compensation networks are added to the input and output of the test calibration compensation data of the vector network analyzer respectively to remove the influence of the GSG on-wafer test structure wiring and be used for parameter modeling of discrete devices.

[0013] Furthermore, the structures of the left and right pads are the same; when measuring the capacitive compensation parameters, any pad on the left or right side is connected to a vector network analyzer to measure the S parameter S of the pad. c , the S parameter S of the pad c Convert to Y parameter Y C ;

[0014] ABCD parameter matrix for calculating pad capacitance compensation parameters

[0015] Furthermore, the ABCD parameter matrix parameters of the inductive compensation parameters of the left compensation network caused by the gold wire bonded by the gold wire are determined based on the through distance Lm between the left pad and the device under test:

[0016]

[0017] Based on the through distance Ln between the right pad and the device under test, the ABCD parameter matrix parameters of the inductive compensation parameters of the right compensation network caused by the gold wire bonded by the gold wire are determined:

[0018]

[0019] In the formula, is the impedance calibration compensation parameter, Calibrate compensation parameters for the transfer constant.

[0020] Furthermore, the impedance calibration compensation parameters and the transmission constant calibration compensation parameters are obtained by processing radio frequency test results of multiple groups of different test spacing patterns.

[0021] Furthermore, the impedance calibration compensation parameter and transfer constant calibration compensation parameters The method for determining includes the following steps:

[0022] Step S501: Select M through distances d1, ..., d between the left and right pads. i ,…,dM ; Connect the left pad, the device under test after dicing and the right pad in sequence through gold wire;

[0023] Step S502: Connect a vector network analyzer at each through distance to test the gold wire d i The straight-through graph is used to obtain the S parameter S ti , convert the S parameter to the Y parameter and get S ti →Y ti ; i=1,…,M;

[0024] Step S503: Calculate the Y parameter of the gold wire to remove the influence of the pad

[0025] Step S504: Convert the gold wire Y parameter into an ABCD parameter matrix

[0026] Step S505: At each through distance, the impedance Zc of the gold wire transmission line and the transmission constant γ of the transmission line are calculated using the ABCD parameter matrix:

[0027]

[0028] Step S506: Calculate impedance calibration compensation parameters and transfer constant calibration compensation parameters

[0029] Furthermore, the S parameters of the compensation network on the left; T L =T C T Lm →S L ;

[0030] S parameters of the compensation network on the right; T R =T Ln T C →S R .

[0031] Further, the gold wire d i When drawing a through graph, the test frequency is set to 2-3 times the frequency required for parameter modeling.

[0032] Further, the gold wire d i The number, spacing, and curvature requirements of the gold wires when drawing a straight-through graphic are the same as the number, spacing, and curvature requirements of the gold wires used for gold bonding during parameter modeling.

[0033] Furthermore, the through distances d1, ..., d i ,…,d MThe length range covers the through distances Lm and Ln between the left and right pads and the device under test during parameter modeling.

[0034] Further, the assembly sequence of the GSG on-wafer test structure includes:

[0035] Solder the left and right pads for GSG on-wafer testing and the device under test onto the metal heat sink through solder;

[0036] According to the preset spacing, the left pad and the device under test, and the right pad and the device under test are connected together by gold wires respectively;

[0037] The substrate material of the left and right solder pads is a high-resistance material, and the solder is consistent with the solder required for soldering the chip of the device under test.

[0038] The present invention can achieve at least one of the following beneficial effects:

[0039] The nonlinear model in the present invention has no special on-wafer test pattern requirements for the discrete devices after dicing, and no special requirements for the materials of the discrete devices. This method can be used to quickly and effectively obtain an accurate large signal model, avoiding model changes caused by uneven device process between chips. In circuit design, especially in hybrid packaging circuit design, circuit correction can be performed according to the real-time model, improving circuit design efficiency and saving R&D costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0041] Figure 1 This is a flow chart of the parameter extraction modeling method of this embodiment;

[0042] Figure 2 This is a schematic diagram of the device under test and the GSG on-wafer test connection graphic chip after welding and gold wire bonding in this embodiment;

[0043] Figure 3 This is a physical picture of the device under test and the GSG on-wafer test connection graphic chip after welding and gold wire bonding in this embodiment;

[0044] Figure 4 It is a side view after the package bonding of this embodiment;

[0045] Figure 5 is a flow chart of a method for determining impedance calibration compensation parameters and transmission constant calibration compensation parameters of this embodiment;

[0046] Figure 6 is a schematic diagram of a straight-through pattern with a straight-through distance of d1 in this embodiment;

[0047] Figure 7 Schematic diagram of a straight-through diagram with a straight-through distance of d2 in this embodiment;

[0048] Figure 8 This is a comparison diagram of the parasitic inductance measured and simulated in this embodiment;

[0049] Fig. 9 This is a measured diagram of the parasitic capacitance of this embodiment;

[0050] Fig.10 is a DC comparison diagram of the actual measurement results and the model simulation results of this embodiment;

[0051] Fig.11 4 is a large signal comparison diagram of the actual measurement results and the model simulation results of this embodiment. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0053] This embodiment discloses a parameter extraction modeling method suitable for discrete devices after dicing, such as Figure 1 As shown, the following steps are included:

[0054] Step S1, connecting the left pad, the device to be tested after dicing and the right pad into a GSG on-wafer test structure by gold wire bonding;

[0055] The device under test after dicing is a discrete device;

[0056] Specifically, the assembly sequence of the GSG (ground-signal-ground) on-wafer test structure includes:

[0057] Solder the left and right pads for GSG on-wafer testing and the device under test onto the metal heat sink through solder;

[0058] According to the preset spacing, connect the left and right pads and the device under test together through gold wires;

[0059] The left pad is connected to the input terminal of the device under test through a gold wire connection; the right pad is connected to the output terminal of the device under test through a gold wire connection;

[0060] The substrate material of the left and right solder pads is a high-resistance material, and the solder is consistent with the solder required for soldering the chip of the device under test.

[0061] Figure 2 The schematic diagram of the device under test, GSG on-wafer test pad (connecting the graphics chip) welding and gold wire bonding completed according to step S1 is as follows: Figure 3 for Figure 2Physical picture. Figure 4 It is a side view after package bonding, in which 10 is a test pad, 20 is a device to be tested, 30 is a gold wire, 40 is a metal heat sink, and 50 is solder.

[0062] Step S2, measuring the capacitive compensation parameters of the left and right compensation networks caused by the left and right pads;

[0063] Specifically, the left and right pads have the same structural shape; when measuring the capacitive compensation parameters caused by the pads, any of the left and right pads is connected to a vector network analyzer, and the S parameter S of the pad is measured by the vector network analyzer. c , the S parameter S of the pad c Convert to Y parameter Y C ; When measuring, the test frequency is set to 2-3 times the frequency required for parameter modeling.

[0064] Since the GSG on-wafer test is a four-port network, the ABCD parameter matrix of the pad capacitance compensation parameters is calculated.

[0065] Step S3, determining the inductive compensation parameters of the left and right compensation networks caused by the gold wires of the gold wire bonding based on the through distances Lm and Ln between the left and right pads and the device under test;

[0066] Specifically, the ABCD parameter matrix parameters of the inductive compensation parameters of the left compensation network caused by the gold wire bonded by the gold wire are determined based on the through distance Lm between the left pad and the device under test:

[0067]

[0068] Specifically, the ABCD parameter matrix parameters of the inductive compensation parameters of the right compensation network caused by the gold wire bonded by the gold wire are determined based on the through distance Ln between the right pad and the device under test:

[0069]

[0070] In the formula, is the impedance calibration compensation parameter, Calibrate compensation parameters for the transfer constant.

[0071] More specifically, in order to further remove the influence of parasitic parameters attached to pads and gold wires on accurate modeling of devices, impedance calibration compensation parameters and transmission constant calibration compensation parameters are obtained by data processing of RF test results of multiple groups of different test spacing patterns.

[0072] Specifically, Figure 5 Impedance calibration compensation parameters and transfer constant calibration compensation parameters The method for determining includes the following steps:

[0073] Step S501: Select M through distances d1, ..., d between the left and right pads. i ,…,d M ; Connect the left pad, the device under test after dicing and the right pad in sequence through gold wire;

[0074] Specifically, test the gold wire d i The number, spacing, and curvature requirements of the gold wires when drawing a straight-through graphic are the same as the number, spacing, and curvature requirements of the gold wires used for gold bonding during parameter modeling.

[0075] The through distances d1, ..., d i ,…,d M The length range covers the through distances Lm and Ln between the left and right pads and the device under test during parameter modeling.

[0076] In the connected through-graph, the connection point of the gold wire connecting the left pad and the device under test and the gold wire connecting the right pad and the device under test on the device under test are the same connection point. In terms of connection, it can be considered that the gold wire starts from the left pad, bridges on the metal pad of the device under test, and then connects to the right pad from the device under test.

[0077] Figure 6 , Figure 7 They are schematic diagrams of straight-through graphics with straight-through distances of d1 and d2 respectively.

[0078] Step S502: Connect a vector network analyzer at each through distance to test the gold wire d i The straight-through graph is used to obtain the S parameter S ti , convert the S parameter to the Y parameter and get S ti →Y ti ; i=1,…,M;

[0079] The S parameter S of the connection structure in step S501 ti The S parameters are obtained by measuring the left and right pads respectively; the test frequency is set to 2-3 times the frequency required for parameter modeling.

[0080] Step S503, calculating the Y parameter of the gold wire after removing the influence of the pad;

[0081] Since the left and right pads both bring parasitic parameters during the measurement of step S502, the pad influence is removed when calculating the gold wire Y parameter; therefore, the gold wire Y parameter

[0082] Step S504, converting the gold wire Y parameter into an ABCD parameter matrix;

[0083] Converting the Y parameters of the gold wire into an ABCD parameter matrix based on a four-port network

[0084] Step S505: At each through distance, the impedance Zc of the gold wire transmission line and the transmission constant γ of the transmission line are calculated using the ABCD parameter matrix:

[0085] Among them, the impedance of the gold wire transmission line at each through distance is Transmission line transmission constant

[0086] Step S506: Calculate impedance calibration compensation parameters and transfer constant calibration compensation parameters

[0087] Impedance calibration compensation parameters

[0088] Transfer constant calibration compensation parameters

[0089] Step S4, determining the S parameters of the left and right compensation networks according to the inductive compensation parameters and the capacitive compensation parameters;

[0090] S parameters of the compensation network on the left; T L =T C T Lm →S L ;

[0091] S parameters of the compensation network on the right; T R =T Ln T C →S R ;

[0092] ABCD parameter matrix of pad

[0093] The through distance Lm between the left pad and the device under test determines the ABCD parameter matrix parameters of the inductive compensation parameters of the left compensation network caused by the gold wire bonded by the gold wire:

[0094]

[0095] The through distance Ln between the right pad and the device under test determines the ABCD parameter matrix parameters of the inductive compensation parameters of the right compensation network caused by the gold wire bonded by the gold wire:

[0096]

[0097] Step S5, adding the S parameters of the left and right compensation networks to the input and output terminals of the test calibration compensation data of the vector network analyzer respectively, to form a test pattern that removes the influence of the GSG on-wafer test structure wiring, which is used for parameter extraction modeling of discrete devices.

[0098] S L and S R Added to the test calibration compensation data input and output terminals S[in] and S[out] of the vector network analyzer respectively;

[0099] The S parameters of the pad and gold wire are based on the above formula, and the parasitic capacitance and inductance parameters are calculated. The obtained S2P file is substituted into ADS for verification. Figure 8 , 9 As shown in the figure, the comparison between the simulation results and the measured results shows that the accuracy of restoring the S parameters of the test graph using the solved gold wire S parameters is very high. S11 has basically no deviation in the whole frequency band, S21 has a slight offset at higher frequencies, and the deviation is very small in the actual frequency range below 18GHz. Therefore, the extracted gold wire S parameters meet the actual test requirements.

[0100] Through the parameter extraction modeling method of this embodiment, after completing the calibration, the modeling software is used to perform modeling, obtain the corresponding modeling data, and perform device testing. Test conditions: frequency: 3GHz, gate voltage Vgs=-2V, drain voltage Vds=30V. Fig.10 This is a DC comparison chart of the measured results and the model simulation results. The solid line is the test simulation result, and the dots are the measured results. Fig.11 : is a comparison chart of large signal nonlinear test actual measurement and simulation, the solid line is the test simulation result, and the dots are the actual measurement result. By comparison, it can be seen that the parameter extraction modeling method of this embodiment can obtain an accurate model.

[0101] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A parameter extraction modeling method suitable for discrete devices after dicing, characterized in that: The following steps are involved: Connect the left pad, the device under test after dicing and the right pad into a GSG on-wafer test structure by gold wire bonding; The capacitive compensation parameters of the left and right compensation networks caused by the left and right pads are measured; Determine the inductive compensation parameters of the left and right compensation networks caused by the gold wires of the gold wire bonding based on the through distances Lm and Ln between the left and right pads and the device under test respectively; Determine the S parameters of the left and right compensation networks according to the inductive compensation parameters and capacitive compensation parameters of the left and right compensation networks; The S parameters of the left and right compensation networks are added to the input and output of the test calibration compensation data of the vector network analyzer respectively to remove the influence of the GSG on-wafer test structure wiring and be used for parameter modeling of discrete devices.

2. The parameter extraction modeling method according to claim 1, characterized in that: The structures of the left and right pads are the same; when measuring the capacitive compensation parameters, any pad on the left or right side is connected to a vector network analyzer to measure the S parameter S of the pad. c , the S parameter S of the pad c Convert to Y parameter Y C ; ABCD parameter matrix for calculating pad capacitance compensation parameters 3. The parameter extraction modeling method according to claim 1, characterized in that: Based on the through distance Lm between the left pad and the device under test, the ABCD parameter matrix parameters of the inductive compensation parameters of the left compensation network caused by the gold wire bonded by the gold wire are determined: Based on the through distance Ln between the right pad and the device under test, the ABCD parameter matrix parameters of the inductive compensation parameters of the right compensation network caused by the gold wire bonded by the gold wire are determined: In the formula, is the impedance calibration compensation parameter, Calibrate compensation parameters for the transfer constant.

4. The parameter extraction modeling method according to claim 3 is characterized in that: The impedance calibration compensation parameters and the transmission constant calibration compensation parameters are obtained by processing the radio frequency test results of multiple groups of different test spacing patterns.

5. The parameter extraction modeling method according to claim 3 or 4, characterized in that: Impedance calibration compensation parameters and transfer constant calibration compensation parameters The method for determining includes the following steps: Step S501: Select M through distances d1, ..., d between the left and right pads. i ,…,d M ; Connect the left pad, the device under test after dicing and the right pad in sequence through gold wire; Step S502: Connect a vector network analyzer at each through distance to test the gold wire d i The straight-through graph is used to obtain the S parameter S ti , convert the S parameter to the Y parameter and get S ti →Y ti ; i=1,…,M; Step S503: Calculate the Y parameter of the gold wire to remove the influence of the pad Step S504: Convert the gold wire Y parameter into an ABCD parameter matrix Step S505: At each through distance, the impedance Zc of the gold wire transmission line and the transmission constant γ of the transmission line are calculated using the ABCD parameter matrix: Step S506: Calculate impedance calibration compensation parameters and transfer constant calibration compensation parameters 6. The parameter extraction modeling method according to claim 5 is characterized in that: S parameters of the compensation network on the left; T L =T C T Lm →S L ; S parameters of the compensation network on the right; T R =T Ln T C →S R .

7. The parameter extraction modeling method according to claim 5, characterized in that: Test gold wire d i When drawing a through graph, the test frequency is set to 2-3 times the frequency required for parameter modeling.

8. The parameter extraction modeling method according to claim 5, characterized in that: Test gold wire d i The number, spacing, and curvature requirements of the gold wires when drawing a straight-through graphic are the same as the number, spacing, and curvature requirements of the gold wires used for gold bonding during parameter modeling.

9. The parameter extraction modeling method according to claim 5, characterized in that: The through distances d1, ..., d i ,…,d M The length range covers the through distances Lm and Ln between the left and right pads and the device under test during parameter modeling.

10. The parameter extraction and modeling method according to any one of claims 1 to 9, characterized in that: The sequence of assembling the GSG on-wafer test structure includes: Solder the left and right pads for GSG on-wafer testing and the device under test onto the metal heat sink through solder; According to the preset spacing, the left pad and the device under test, and the right pad and the device under test are connected together by gold wires respectively; The substrate material of the left and right solder pads is a high-resistance material, and the solder is consistent with the solder required for soldering the chip of the device under test.

Images