Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched, the layer to be etched including a first region and a second region; forming a first core layer on the first region; forming a sidewall material layer on the sidewalls of the first core layer; forming a second core layer on the layer to be etched; forming a barrier layer on the second region, a portion of the barrier layer having an isolation trench; modifying the second core layer to form a modified region within the second core layer; and removing the first core layer and the second core layer covered by the barrier layer to form a first opening and a second opening. In this technical solution, by forming an isolation trench within the barrier layer, after removing the second core layer covered by the barrier layer, the modified region exposed by the isolation trench forms an integral structure with the other modified regions, thus having strong stability. Therefore, the modified region exposed by the isolation trench is not easily tilted or collapsed, thereby reducing the risk of short circuiting in the subsequently formed second conductive layer, thereby effectively improving the performance of the ultimately formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As circuit integration increases and scale grows, the size of unit devices in the circuit continues to shrink, and the requirements for integrated circuit manufacturing processes continue to increase. For example, critical dimensions continue to decrease, and chip manufacturing requires increasingly higher lithography resolution.

[0003] In the semiconductor device manufacturing process, photolithography is typically used to transfer the pattern on the mask to the substrate. The photolithography process includes: providing a substrate; forming a photoresist on the semiconductor substrate; exposing and developing the photoresist to form a patterned photoresist, so that the pattern on the mask is transferred to the photoresist; etching the substrate using the patterned photoresist as a mask, so that the pattern on the photoresist is transferred to the substrate; and removing the photoresist.

[0004] However, there are still problems with the pattern transfer process in the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched comprises a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are arranged along a first direction, and the first regions are located between adjacent second regions; forming a first core layer on the first regions, wherein the first core layer extends along a second direction, wherein the first direction and the second direction are perpendicular to each other; forming a sidewall material layer on the sidewall surface of the first core layer; forming a second core layer on the layer to be etched, wherein the second core layer covers the sidewall of the sidewall material layer; and forming the second core layer. Afterwards, a barrier layer is formed on the second region, wherein the barrier layer covers a portion of the top surface of the second core layer, the barrier layer extends along the second direction, and a portion of the barrier layer has a partition groove, and the partition groove penetrates the barrier layer along the first direction; using the barrier layer as a mask, the second core layer is modified to form a modified region in the second core layer, wherein the modified region has modified ions; after forming the modified region, the barrier layer, the first core layer and the second core layer covered by the barrier layer are removed to form a first opening and a second opening in the second core layer.

[0007] Optionally, the method for forming the first core layer includes: forming a first core material layer on the layer to be etched; forming a first patterned layer on the first core material layer, the first patterned layer exposing a portion of the top surface of the first core material layer; etching the first core material layer using the first patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first core layer.

[0008] Optionally, the material of the first core layer includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterned film materials, spin-on carbon and silicon carbide.

[0009] Optionally, the method for modifying the region includes: performing a modification ion implantation process on the second core layer using the barrier layer as a mask to form the modified region.

[0010] Optionally, the modifying ions include one or more of boron ions, carbon ions, phosphorus ions and arsenic ions.

[0011] Optionally, the implantation parameters of the modified ions include: an implantation energy of 1.5KeV to 13KeV; an implantation dose of 1.0E14atoms / cm 2 ~1.0E16 atoms / cm 2 .

[0012] Optionally, the spacer material layer is also located on the top surface of the first core layer and the top surface of the layer to be etched; after forming the modified area, the spacer material layer located on the top of the first core layer is removed.

[0013] Optionally, the process for forming the sidewall material layer includes an atomic layer deposition process.

[0014] Optionally, the material of the spacer material layer includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.

[0015] Optionally, part of the barrier layer covers the sidewall material layer located on the sidewall of the first core layer.

[0016] Optionally, the method for forming the second core layer includes: forming a core material film on the layer to be etched, the core material film covering the side wall material layer; and flattening the core material film until the side wall material layer located on the top surface of the first core layer is exposed to form the second core layer.

[0017] Optionally, the process of planarizing the core material film includes one or more combinations of a chemical mechanical polishing process, a wet etching process, and a dry etching process.

[0018] Optionally, the material of the second core layer includes: one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterned film materials, spin-on carbon and silicon carbide.

[0019] Optionally, the method for forming the barrier layer includes: forming an initial barrier layer on the layer to be etched; forming a second patterned layer on the initial barrier layer, wherein the second patterned layer exposes a portion of the top surface of the initial barrier layer; etching the initial barrier layer using the second patterned layer as a mask until the top surface of the second core layer is exposed, thereby forming the barrier layer.

[0020] Optionally, the material of the barrier layer is different from the material of the second core layer.

[0021] Optionally, the material of the barrier layer includes: nitride, oxide or oxynitride.

[0022] Optionally, the layer to be etched includes: a substrate and a first mask layer located on the substrate, and the spacer material layer and the first core layer are located on the first mask layer.

[0023] Optionally, the material of the first mask layer includes: one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0024] Optionally, after forming the first opening and the second opening, the first mask layer is etched using the second core layer and the sidewall material layer as masks to form a first groove and a second groove in the first mask layer, the first opening exposing the first groove, and the second opening exposing the second groove.

[0025] Optionally, after forming the first groove and the second groove, the method further includes: etching the substrate using the first mask layer as a mask to form a first target groove and a second target groove in the substrate, wherein the first groove exposes the first target groove and the second groove exposes the second target groove.

[0026] Optionally, after forming the first target groove and the second target groove, the method further includes: forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.

[0027] Optionally, the material of the first conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

[0028] Optionally, the material of the second conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the technical solution of the present invention, a blocking trench is formed within a portion of the barrier layer, the blocking trench penetrating the barrier layer along the first direction. Using the barrier layer as a mask, the second core layer is modified to form a modified region within the second core layer, containing modified ions. Because the modified region and the second core layer have different etching rates after the modification, the modified region exposed by the blocking trench is minimally damaged during the subsequent removal of the second core layer covered by the barrier layer. This allows for isolation between the subsequently formed portions of the second target trenches and between the subsequently formed portions of the second conductive layer, thereby meeting electrical design requirements. In the present technical solution, a partition groove is formed in part of the barrier layer, thereby retaining the barrier layer with a larger characteristic size, so that the overall structure is relatively stable. After removing the second core layer covered by the barrier layer, the modified area exposed by the partition groove and the modified area formed by other uncovered areas are an integral structure with strong stability. Therefore, the modified area exposed by the partition groove is not easy to tilt and collapse, thereby reducing the risk of short circuit in the subsequently formed second conductive layer, thereby effectively improving the performance of the semiconductor structure finally formed.

[0031] Furthermore, a portion of the barrier layer covers the spacer material layer located on the sidewall of the first core layer. By partially covering the spacer material layer located on the sidewall of the first core layer with the barrier layer, the spacing between the subsequently formed first conductive layer and the second conductive layer is equal to the thickness of the spacer material layer. This can effectively reduce the spacing between the first conductive layer and the second conductive layer, thereby improving the integration density of the semiconductor device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 7 It is a structural diagram of a semiconductor structure;

[0033] Figures 8 to 21 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the pattern transfer process in the prior art still has problems, which will be described in detail below with reference to the accompanying drawings.

[0035] Figures 1 to 7It is a structural schematic diagram of the formation process of a semiconductor structure.

[0036] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 In the schematic cross-sectional view along line AA, a layer to be etched 100 is provided, and a plurality of core layers 101 arranged in parallel are formed on the layer to be etched 100 ; and sidewall spacers 102 are formed on the sidewalls of the core layers 101 .

[0037] Please refer to Figure 3 , Figure 3 and Figure 2 In the same viewing direction, the core layer 101 is removed, and a first opening 103 is formed in the side wall 102 ; and a partition structure 104 is formed in part of the first opening 103 .

[0038] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 In the cross-sectional diagram along line BB, a sacrificial layer 105 is formed on the layer to be etched 100, and the sacrificial layer 105 covers a portion of the first opening 103 and a portion of the side wall 102, and the sacrificial layer 105 exposes the partition structure 104; the layer to be etched 100 is etched using the sacrificial layer 105, the partition structure 104 and a portion of the side wall 102 as a mask to form a groove 106 in the layer to be etched 100.

[0039] Please refer to Figure 6 and Figure 7 , Figure 7 yes Figure 6 In the cross-sectional view along line CC, after the trench 106 is formed, the sacrificial layer 105 , the sidewall spacer 102 and the partition structure 104 are removed; and a conductive layer 107 is formed in the trench 105 .

[0040] In this embodiment, the purpose of forming the partition structure 104 in part of the first opening 103 is to provide a mask through the partition structure 104 so that part of the groove 106 formed subsequently is isolated, thereby ensuring that part of the conductive layer 107 formed in the end is isolated, so as to meet the requirements of electrical design. However, as the size of unit devices in the circuit continues to shrink, the characteristic size of the position where the conductive layer 107 is isolated is very small, so the characteristic size of the partition structure 104 needs to be very small. When the characteristic size of the partition structure 104 is very small, it is easy for the partition structure 104 to tilt and collapse or be partially etched and removed in the subsequent etching process, which will make the conductive layer 107 that needs to be isolated prone to short circuit problems (such as Figure 6As shown in Part A in FIG, the semiconductor structure is not in compliance with the electrical design requirements, thereby affecting the performance of the final semiconductor structure.

[0041] On this basis, the present invention provides a method for forming a semiconductor structure, by forming a partition groove in part of the barrier layer, thereby retaining the barrier layer with a larger characteristic size, so that the overall structure is relatively stable, and after removing the second core layer covered by the barrier layer, the modified area exposed by the partition groove and the modified area formed by other uncovered areas are an integral structure with strong stability. Therefore, the modified area exposed by the partition groove is not easy to tilt and collapse, thereby reducing the risk of short circuit in the subsequently formed second conductive layer, so that the performance of the semiconductor structure finally formed is effectively improved.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 8 to 21 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 A cross-sectional schematic diagram along line DD is provided, providing a layer to be etched, wherein the layer to be etched includes a plurality of first regions I and a plurality of second regions II, wherein the first regions I and the second regions II are arranged along a first direction X, and the first regions I are located between adjacent second regions II.

[0045] In this embodiment, the layer to be etched includes a substrate 200 and a first mask layer 201 located on the substrate 200 .

[0046] In this embodiment, the material of the substrate 200 is a low-K dielectric layer (K is less than or equal to 3.9); in other embodiments, the material of the substrate includes silicon oxide.

[0047] The material of the first mask layer 201 includes one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide, and aluminum nitride. In this embodiment, the material of the first mask layer 201 is silicon oxide.

[0048] Please refer to Figure 10 , Figure 10 and Figure 9 A first core layer 202 is formed on the first region I in the same viewing direction. The first core layer 202 extends along a second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0049] In this embodiment, the first core layer 202 is used to provide a size and a position for a first conductive layer formed subsequently.

[0050] In this embodiment, the method for forming the first core layer 202 includes: forming a first core material layer (not shown) on the layer to be etched; forming a first patterned layer (not shown) on the first core material layer, the first patterned layer exposing a portion of the top surface of the first core material layer; etching the first core material layer using the first patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first core layer 202.

[0051] The material of the first core layer 202 includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterning film (APF), spin-on carbon, and silicon carbide. In this embodiment, the material of the first core layer 202 is amorphous silicon.

[0052] Please refer to Figure 11 , forming a sidewall material layer 203 on the sidewall surface of the first core layer 202 .

[0053] In this embodiment, a spacer material layer 203 is formed on the sidewall of the first core layer 202 to provide a spacer mask for the subsequently formed first conductive layer and second conductive layer.

[0054] In this embodiment, the spacer material layer 203 is also located on the top surface of the first core layer 202 and the top surface of the layer to be etched.

[0055] In this embodiment, the formation process of the spacer material layer 203 includes an atomic layer deposition process.

[0056] The material of the spacer material layer 203 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. In this embodiment, the material of the spacer material layer 203 is silicon nitride.

[0057] Please refer to Figure 12 , forming a second core layer 204 on the layer to be etched, wherein the second core layer 204 covers the sidewalls of the spacer material layer 203 .

[0058] In this embodiment, the method for forming the second core layer 204 includes: forming a core material film (not shown) on the layer to be etched, the core material film covering the sidewall material layer 203; and flattening the core material film until the sidewall material layer 203 located on the top surface of the first core layer 202 is exposed, thereby forming the second core layer 204.

[0059] The process for planarizing the core material film includes one or more combinations of a chemical mechanical polishing process, a wet etching process, and a dry etching process. In this embodiment, the process for planarizing the core material film adopts a chemical mechanical polishing process.

[0060] The material of the second core layer 204 includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterned film materials, spin-on carbon, and silicon carbide. In this embodiment, the material of the second core layer 204 is amorphous silicon.

[0061] Please refer to Figure 13 and Figure 14 , Figure 14 yes Figure 13 In the cross-sectional schematic diagram along line EE, after the second core layer 204 is formed, a barrier layer 205 is formed on the second region II, and the barrier layer 205 covers a portion of the top surface of the second core layer 204. The barrier layer 205 extends along the second direction Y, and a portion of the barrier layer 205 has a partition groove 206, and the partition groove 206 penetrates the barrier layer 205 along the first direction X.

[0062] In this embodiment, the barrier layer 205 is used to provide a size and a position for a second conductive layer formed subsequently.

[0063] In this embodiment, a portion of the barrier layer 205 has a partitioning groove 206 , the purpose of which is to partition a portion of the second conductive layer formed subsequently, thereby meeting the requirements of electrical design.

[0064] In this embodiment, the method for forming the barrier layer 205 includes: forming an initial barrier layer (not shown) on the layer to be etched; forming a second patterned layer (not shown) on the initial barrier layer, wherein the second patterned layer exposes a portion of the top surface of the initial barrier layer; etching the initial barrier layer using the second patterned layer as a mask until the top surface of the second core layer is exposed, thereby forming the barrier layer 205.

[0065] In this embodiment, the material of the barrier layer is different from the material of the second core layer.

[0066] The material of the barrier layer 205 includes nitride, oxide or oxynitride. In this embodiment, the material of the barrier layer 205 is silicon oxide.

[0067] In this embodiment, a portion of the barrier layer 205 covers the spacer material layer 203 located on the sidewalls of the first core layer 202. By partially covering the spacer material layer 203 located on the sidewalls of the first core layer 202 with the barrier layer 205, the distance between the subsequently formed first conductive layer and the second conductive layer is equal to the thickness of the spacer material layer 203. This effectively reduces the distance between the first conductive layer and the second conductive layer, thereby improving the integration density of the semiconductor device structure.

[0068] Please refer to Figure 15 and Figure 16 , Figure 16 yes Figure 15 In the cross-sectional diagram along line FF, the second core layer 204 is modified by using the barrier layer 205 as a mask to form a modified region 207 in the second core layer 204 , wherein the modified region 207 contains modified ions.

[0069] In this embodiment, the purpose of forming a modified zone 207 in the second core layer 204 is to make the etching rate between the modified zone 207 and the second core layer 204 different, so that in the subsequent process of removing the second core layer 204 covered by the barrier layer 205, the modified zone 207 exposed by the isolation groove 206 can be less damaged, thereby forming isolation between the parts of the second target grooves formed subsequently, and ensuring isolation between the parts of the second conductive layers formed subsequently, thereby meeting the requirements of electrical design.

[0070] In this embodiment, the method for forming the modified region 207 includes: performing a modification ion implantation process on the second core layer 204 using the barrier layer 205 as a mask to form the modified region 207 .

[0071] The modified ions include one or more of boron ions, carbon ions, phosphorus ions, and arsenic ions. In this embodiment, the modified ions are carbon ions.

[0072] In this embodiment, the implantation parameters of the modified ions include: implantation energy of 1.5KeV~13KeV; implantation dose of 1.0E14atoms / cm 2 ~1.0E16 atoms / cm 2 .

[0073] Please refer to Figure 17 , Figure 17 and Figure 16In the same viewing direction, after forming the modified area 207, the barrier layer 205, the first core layer 202 and the second core layer 204 covered by the barrier layer 205 are removed, and a first opening 208 and a second opening 209 are formed in the second core layer 204.

[0074] In the present technical solution, a partition groove 206 is formed in part of the barrier layer 205, thereby retaining the barrier layer 205 with a larger characteristic size, so that the overall structure is relatively stable. After removing the second core layer 204 covered by the barrier layer 205, the modified area 207 exposed by the partition groove 206 and the modified area 207 formed by other uncovered areas are an integral structure with strong stability. Therefore, the modified area 207 exposed by the partition groove 206 is not easy to tilt and collapse, thereby reducing the risk of short circuit in the subsequently formed second conductive layer, thereby effectively improving the performance of the semiconductor structure finally formed.

[0075] In this embodiment, the process of removing the barrier layer 205 , the first core layer 202 and the second core layer 204 covered by the barrier layer 205 further includes: removing the spacer material layer 203 located on top of the first core layer 202 .

[0076] In this embodiment, the process of removing the barrier layer 205, the first core layer 202 and the second core layer 204 covered by the barrier layer 205 adopts a dry etching process; in other embodiments, a wet etching process or a combination of a dry etching process and a wet etching process can also be used to etch and remove the barrier layer, the first core layer and the second core layer covered by the barrier layer.

[0077] Please refer to Figure 18 After forming the first opening 208 and the second opening 209, the first mask layer 201 is etched using the second core layer 204 and the sidewall material layer 203 as masks to form a first groove 210 and a second groove 211 in the first mask layer 201. The first opening 208 exposes the first groove 210, and the second opening 209 exposes the second groove 211.

[0078] In this embodiment, the modified region 207 and the spacer material layer 203 are removed after forming the first trench 210 and the second trench 211. In other embodiments, the modified region and the spacer material layer may not be removed after forming the first trench and the second trench, and the substrate may be etched in subsequent processes using the second core layer, the spacer material layer, and the first mask layer as masks.

[0079] In this embodiment, the first mask layer 201 is etched using a dry etching process; in other embodiments, the first mask layer may be removed using a wet etching process or a combination of dry etching and wet etching.

[0080] Please refer to Figure 19 After forming the first groove 210 and the second groove 211, the substrate 200 is etched using the first mask layer 201 as a mask to form a first target groove 212 and a second target groove 213 in the substrate 200, wherein the first groove 210 exposes the first target groove 212, and the second groove 211 exposes the second target groove 213.

[0081] The process of etching the substrate using the first mask layer 201 as a mask includes one or a combination of dry etching and wet etching. In this embodiment, the process of etching the substrate using the first mask layer 201 as a mask adopts a dry etching process.

[0082] In this embodiment, after the first target groove 212 and the second target groove 213 are formed, the first mask layer 201 is removed.

[0083] Please refer to Figure 20 and Figure 21 , Figure 21 yes Figure 20 In the cross-sectional diagram along line GG, after the first target groove 212 and the second target groove 213 are formed, a first conductive layer 214 is formed in the first target groove 212 ; and a second conductive layer 215 is formed in the second target groove 213 .

[0084] In this embodiment, the method for forming the first conductive layer 214 and the second conductive layer 215 includes: forming a conductive film (not shown) in the first target groove 212 and the second target groove 213, the conductive film covering the substrate; flattening the conductive film until the substrate 200 is exposed, forming the first conductive layer 214 in the first target groove 212, and forming the second conductive layer 215 in the second target groove 213.

[0085] The material of the first conductive layer 214 includes one or more of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene. In this embodiment, the material of the first conductive layer 214 is copper.

[0086] The material of the second conductive layer 215 includes one or more of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene. In this embodiment, the material of the second conductive layer 215 is copper.

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, the layer to be etched comprising a plurality of first regions and a plurality of second regions, the first regions and the second regions being arranged along a first direction, and the first regions being located between adjacent second regions; forming a first core layer on the first region, wherein the first core layer extends along a second direction, and the first direction is perpendicular to the second direction; forming a sidewall material layer on the sidewall surface of the first core layer; forming a second core layer on the layer to be etched, wherein the second core layer covers the sidewalls of the spacer material layer; After forming the second core layer, forming a barrier layer on the second region, wherein the barrier layer covers a portion of the top surface of the second core layer, the barrier layer extends along the second direction, and a portion of the barrier layer has a partitioning trench therein, the partitioning trench penetrating the barrier layer along the first direction; Using the barrier layer as a mask, modifying the second core layer to form a modified region in the second core layer, wherein the modified region contains modified ions; After forming the modified area, the barrier layer, the first core layer, and the second core layer covered by the barrier layer are removed, and a first opening and a second opening are formed in the second core layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first core layer includes: forming a first core material layer on the layer to be etched; forming a first patterned layer on the first core material layer, the first patterned layer exposing a portion of the top surface of the first core material layer; etching the first core material layer using the first patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first core layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first core layer includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterned film materials, spin-on carbon and silicon carbide.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the modified region includes: performing a modification ion implantation process on the second core layer using the barrier layer as a mask to form the modified region.

5. The method for forming a semiconductor structure according to claim 1, wherein: The modified ions include one or more of boron ions, carbon ions, phosphorus ions and arsenic ions.

6. The method for forming a semiconductor structure according to claim 4, wherein: The parameters of the modified ion implantation process include: implantation energy of 1.5KeV~13KeV; implantation dose of 1.0E14atoms / cm 2 ~1.0E16 atoms / cm 2 .

7. The method for forming a semiconductor structure according to claim 1, wherein: The spacer material layer is also located on the top surface of the first core layer and the top surface of the layer to be etched; after the modified area is formed, the spacer material layer located on the top of the first core layer is removed.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process for forming the spacer material layer includes an atomic layer deposition process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the spacer material layer includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide.

10. The method for forming a semiconductor structure according to claim 1, wherein: Part of the barrier layer covers the spacer material layer located on the sidewall of the first core layer.

11. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second core layer includes: forming a core material film on the layer to be etched, the core material film covering the sidewall material layer; flattening the core material film until the sidewall material layer located on the top surface of the first core layer is exposed to form the second core layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of planarizing the core material film includes one or more combinations of a chemical mechanical polishing process, a wet etching process, and a dry etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second core layer includes one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, silicon oxide, advanced patterned film materials, spin-on carbon and silicon carbide.

14. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the barrier layer includes: forming an initial barrier layer on the layer to be etched; forming a second patterned layer on the initial barrier layer, wherein the second patterned layer exposes a portion of the top surface of the initial barrier layer; etching the initial barrier layer using the second patterned layer as a mask until the top surface of the second core layer is exposed, thereby forming the barrier layer.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer is different from that of the second core layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the barrier layer includes nitride, oxide or oxynitride.

17. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate and a first mask layer located on the substrate, and the spacer material layer and the first core layer are located on the first mask layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The material of the first mask layer includes: one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon carbide nitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

19. The method for forming a semiconductor structure according to claim 17, wherein: After forming the first opening and the second opening, the first mask layer is etched using the second core layer and the sidewall material layer as masks to form a first groove and a second groove in the first mask layer, wherein the first opening exposes the first groove and the second opening exposes the second groove.

20. The method for forming a semiconductor structure according to claim 19, wherein: After forming the first groove and the second groove, the method further includes: etching the substrate using the first mask layer as a mask to form a first target groove and a second target groove in the substrate, wherein the first groove exposes the first target groove and the second groove exposes the second target groove.

21. The method for forming a semiconductor structure according to claim 20, wherein: After forming the first target groove and the second target groove, the method further includes: forming a first conductive layer in the first target groove; and forming a second conductive layer in the second target groove.

22. The method for forming a semiconductor structure according to claim 21, wherein: The material of the first conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

23. The method for forming a semiconductor structure according to claim 21, wherein: The material of the second conductive layer includes: one or more combinations of copper, aluminum, tungsten, cobalt, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride and graphene.

Images