Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of initial dummy gate structures on the substrate, the initial gate structure including a first dummy gate layer, a first mask layer, and a second dummy gate layer; forming a sidewall material layer on sidewalls and top surfaces of the initial dummy gate structures; forming a dielectric material layer on the substrate; performing a first planarization process on the dielectric material layer and the sidewall material layer until a top surface of the second dummy gate layer is exposed, the first planarization process having a smaller polishing rate on the second dummy gate layer than on the dielectric material layer and the sidewall material layer. The method can ensure that the first planarization process stops at the surface of the second dummy gate layer, and has a relatively flat processing interface, and effectively improves the uniformity of the height of the initial sidewall. The top surface of the formed initial dielectric layer is higher than the top surface of the first dummy gate layer, which can effectively avoid the problem of short connection of adjacent gate structures in the subsequent process, and improve the performance of the formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] As technology nodes decrease, traditional gate dielectric layers become increasingly thinner, leading to increased transistor leakage current and wasted power in semiconductor devices. To address these issues, existing technologies offer a solution that replaces polysilicon gates with metal gates. The gate-last process is a key process for forming metal gates.

[0003] However, during the back gate process, the metal material of the metal gate degrades the isolation performance of the dielectric layer in the semiconductor structure, thereby affecting the performance of the semiconductor structure. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve the uniformity of the height of the initial sidewall and the second dummy gate layer, and the top surface of the formed initial dielectric layer is higher than the top surface of the first dummy gate layer, which can effectively avoid the problem of short circuit of subsequent adjacent gate structures, thereby improving the performance of the formed semiconductor structure.

[0005] To address the aforementioned problems, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of mutually discrete initial dummy gate structures on the substrate, the initial gate structures including a first dummy gate layer, a first mask layer located on the first dummy gate layer, and a second dummy gate layer located on the first mask layer; forming a sidewall material layer on the sidewalls and top surface of the initial dummy gate structures; forming a dielectric material layer on the substrate, the dielectric material layer covering the sidewalls of the sidewall material layer; performing a first planarization process on the dielectric material layer and the sidewall material layer until the top surface of the second dummy gate layer is exposed, thereby forming an initial dielectric layer and an initial sidewall, wherein the polishing rate of the first planarization process on the second dummy gate layer is less than the polishing rate on the dielectric material layer and the sidewall material layer, and the polishing rate of the first planarization process on the dielectric material layer and the sidewall material layer is within a preset polishing rate range.

[0006] Optionally, after the first planarization process, the method further includes: removing the second dummy gate layer and the initial sidewall located on the sidewall of the second dummy gate layer to form a sidewall; performing a second planarization process on the initial dielectric layer until the top surface of the first mask layer is exposed to form a dielectric layer, wherein the second planarization process has a greater polishing rate on the initial dielectric layer than on the first mask layer; and after forming the dielectric layer, removing the first mask layer and the sidewall of the sidewall of the first mask layer to form a first opening in the dielectric layer, wherein the first opening exposes the top surface of the first dummy gate layer.

[0007] Optionally, after removing the first mask layer, the method further includes: removing the first dummy gate layer, forming a second opening in the dielectric layer at the bottom of the first opening, and forming a gate structure in the second opening.

[0008] Optionally, the method for forming the gate structure includes: forming a gate material layer in the first opening, the second opening, and on the surface of the dielectric layer; performing a third planarization process on the gate material layer and the dielectric layer until the top surface of the sidewall is exposed, thereby forming the gate structure.

[0009] Optionally, the third planarization process includes a chemical mechanical polishing process.

[0010] Optionally, the initial pseudo-gate structure further includes: a second mask layer located on the second pseudo-gate layer, and a first protective layer located on the second mask layer.

[0011] Optionally, the method for forming the initial pseudo-gate structure includes: forming a first pseudo-gate material layer on the substrate; forming a first pseudo-gate material layer on the first pseudo-gate material layer; forming a second pseudo-gate material layer on the first mask material layer; forming a second mask material layer on the second pseudo-gate material layer; forming a patterned first protective layer on a portion of the second mask material layer; and etching the first pseudo-gate material layer, the first mask material layer, the second pseudo-gate material layer, and the second mask material layer using the first protective layer as a mask to form the initial pseudo-gate structure.

[0012] Optionally, the process for forming the sidewall material layer includes atomic layer deposition.

[0013] Optionally, the material of the dielectric material layer includes silicon oxide.

[0014] Optionally, the material of the sidewall material layer includes silicon nitride.

[0015] Optionally, the material of the first pseudo-gate layer includes polycrystalline silicon; the material of the second pseudo-gate layer includes polycrystalline silicon.

[0016] Optionally, the material of the first mask layer includes silicon nitride.

[0017] Optionally, the first planarization process includes a chemical mechanical polishing process.

[0018] Optionally, the second planarization process includes a chemical mechanical polishing process.

[0019] Optionally, after forming the dielectric layer and before removing the first mask layer, the method further includes: forming a patterned layer on the dielectric layer and the first mask layer, the patterned layer exposing a portion of the top surface of the first mask layer; etching the first mask layer and the first pseudo-gate layer using the patterned layer as a mask to form an isolation opening within the dielectric layer; and forming an isolation structure within the isolation opening.

[0020] Optionally, the isolation structure includes: a first isolation layer and a second protective layer located on the first isolation layer, wherein the top surface of the first isolation layer is flush with the top surface of the first pseudo-gate layer, and the top surface of the second protective layer is flush with the top surface of the dielectric layer.

[0021] Optionally, the substrate includes: a base and a plurality of mutually discrete fins located on the base, the initial pseudo-gate structure spanning the fins and the initial pseudo-gate structure covering a portion of the sidewalls and top surface of the fins.

[0022] Optionally, before forming the initial pseudo-gate structure, the method further includes: forming a second isolation layer on the substrate, the second isolation layer covering a portion of the sidewall of the fin, and the top surface of the second isolation layer being lower than the top surface of the fin.

[0023] Optionally, the method for forming the dielectric material layer includes: forming a dielectric material film on the substrate, the dielectric material film covering the sidewall material layer; and performing a fourth planarization process on the dielectric material film until the surface of the sidewall material layer is exposed, thereby forming the dielectric material layer.

[0024] Optionally, the widths of the initial pseudo-gate structures are different, and the spacing between adjacent initial pseudo-gate structures is different.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the method for forming the technical solution of the present invention, the initial gate structure includes a first dummy gate layer, a first mask layer located on the first dummy gate layer, and a second dummy gate layer located on the first mask layer. The grinding rate of the second dummy gate layer in the first planarization process is lower than the grinding rate of the dielectric material layer and the sidewall material layer, and the grinding rate of the dielectric material layer and the sidewall material layer in the first planarization process is within a preset grinding rate range. Therefore, it can ensure that the first planarization process stops at the surface of the second dummy gate layer and has a relatively flat processing interface, while also effectively improving the uniformity of the height of the formed initial sidewall.

[0027] Furthermore, the top surface of the initial dielectric layer is higher than the top surface of the first dummy gate layer, which in turn makes the top surface of the subsequently formed dielectric layer higher than the top surface of the first dummy gate layer. Even if a gate material layer remains on the surface of the dielectric layer during the subsequent formation of the gate structure, the portion of the dielectric layer above the first dummy gate layer will be removed during the subsequent planarization of the gate material layer to form the gate structure. At this time, the gate material layer on the surface of the dielectric layer will also be removed, effectively avoiding the problem of short circuit between adjacent gate structures, thereby improving the performance of the final semiconductor structure. Attached Figure Description

[0028] Figures 1 to 2 This is a schematic diagram of a semiconductor structure.

[0029] Figures 3 to 4 This is a schematic diagram of another semiconductor structure;

[0030] Figures 5 to 13 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] As described in the background section, the isolation performance of the dielectric layer formed in the prior art deteriorates, thereby affecting the performance of the semiconductor structure. This will be explained in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0033] Please refer to Figure 1 A substrate 100 is provided, on which a plurality of mutually discrete pseudo-gate structures 101 are provided. Each pseudo-gate structure 101 includes a pseudo-gate layer, a mask layer located on the pseudo-gate layer, and sidewalls (not shown) located on the sidewalls of the mask layer and the pseudo-gate layer. An initial dielectric layer (not shown) is formed on the substrate 100 and the pseudo-gate structures 101. The initial dielectric layer is planarized until the top surface of the pseudo-gate layer is exposed to form a dielectric layer 102.

[0034] Please refer to Figure 2 Remove the dummy gate layer, form a gate opening in the dielectric layer 102, and form a gate structure 103 in the gate opening.

[0035] In this embodiment, the material of the initial dielectric layer includes silicon oxide; the process for forming the initial dielectric layer includes fluid chemical vapor deposition; and the material of the mask layer includes silicon nitride.

[0036] However, the semiconductor structures prepared using the above method have poor performance because:

[0037] In this embodiment, the initial dielectric layer is planarized using a chemical mechanical polishing (CMP) process until the top surface of the dummy gate layer is exposed, forming the dielectric layer 102. During the planarization of the initial dielectric layer, the mask layer is also removed. Because the mask layer and the initial dielectric layer are made of different materials, the planarization rate on the initial dielectric layer is greater than the rate on the mask layer. Therefore, when the planarization stops at the surface of the dummy gate layer, a depression (e.g., ...) is formed on the dielectric layer 102. Figure 1 (As shown in Part A of the middle section).

[0038] Since a gate structure 103 needs to be formed within the gate opening subsequently, the method for forming the gate structure 103 includes: forming a gate material layer within the gate opening and on the dielectric layer 102; and planarizing the gate material layer until the top surface of the sidewall is exposed. During the planarization of the gate material layer, the gate material layer is easily deposited in the recesses of the dielectric layer 102. Because the gate material layer has conductive properties, the deposited gate material layer in the recesses of the dielectric layer 102 can easily cause short circuits in adjacent gate structures 103, thereby affecting the performance of the semiconductor structure.

[0039] To address the aforementioned issues, the prior art has proposed another method for forming semiconductor structures, which will be described in detail below with reference to the accompanying drawings.

[0040] Figures 3 to 4 This is a schematic diagram of the steps involved in forming another semiconductor structure.

[0041] Please refer to Figure 3A substrate 200 is provided, on which a plurality of mutually discrete pseudo-gate structures 201 are provided. The pseudo-gate structure 201 includes a pseudo-gate layer, a mask layer located on the pseudo-gate layer, sidewalls located on the mask layer and the pseudo-gate layer, and sidewalls (not shown) on the top surface of the mask layer. The sidewalls located on the top surface of the mask layer are removed. An initial dielectric layer is formed on the substrate 200 and the pseudo-gate structure 201. The initial dielectric layer (not shown) is planarized until the top surface of the mask layer is exposed to form a dielectric layer 202. After forming the dielectric layer 202, the mask layer is removed.

[0042] Please refer to Figure 4 Remove the dummy gate layer, form a gate opening in the dielectric layer 202, and form a gate structure 203 in the gate opening.

[0043] In this embodiment, the top surface of the formed dielectric layer 202 is higher than the top surface of the dummy gate layer. Even during the formation of the gate structure 203, the dielectric layer 202 is recessed to deposit the gate material layer. However, when the gate material layer is subsequently planarized, the portion of the dielectric layer 202 above the dummy gate layer is removed. Therefore, the recessed gate material layer is also removed, thereby avoiding the problem of short circuit between adjacent gate structures 203.

[0044] In this embodiment, the mask layers of each of the pseudo-gate structures 201 are on the same horizontal plane. Therefore, in order to make the surface of the planarized dielectric layer 202 horizontal, the final planarization process needs to be stopped on the mask layer. Since the sidewalls and the mask layer are made of the same material, and the sidewalls cover the mask layer, if the sidewalls located on the top surface of the mask layer are not removed, the planarization of the initial dielectric layer can only stop at the surface of the sidewalls, and cannot stop at the surface of the mask layer. Therefore, before performing the planarization, the sidewalls located on the top surface of the mask layer need to be removed.

[0045] However, due to the varying spacing between adjacent dummy gate structures 201, the process of removing the sidewalls located on the top surface of the mask layer is difficult to control, easily leading to uneven sidewall heights. For example, some dummy gate structures may not have their sidewalls removed at all, making subsequent dummy gate layer removal processes impossible; conversely, some dummy gate structures may have their sidewalls removed excessively, falling below the top surface of the dummy gate layer, thus losing their isolation function. These problems all affect the performance of the semiconductor structure.

[0046] Based on this, the present invention provides a method for forming a semiconductor structure. The initial gate structure includes a first dummy gate layer, a first mask layer, and a second dummy gate layer. Sidewall material layers are formed on the sidewalls and top surface of the initial dummy gate structure. A dielectric material layer is formed on a substrate. A first planarization process is performed on the dielectric material layer and the sidewall material layer until the top surface of the second dummy gate layer is exposed. The grinding rate of the first planarization process on the second dummy gate layer is lower than the grinding rate on the dielectric material layer and the sidewall material layer. This method ensures that the first planarization process stops at the surface of the second dummy gate layer, resulting in a relatively flat processing interface. It also effectively improves the uniformity of the initial sidewall height. Furthermore, the top surface of the formed initial dielectric layer is higher than the top surface of the first dummy gate layer, effectively avoiding the problem of short circuits between subsequent adjacent gate structures, thus improving the performance of the formed semiconductor structure.

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 5 to 13 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0049] Please refer to Figure 5 Provides a substrate.

[0050] In this embodiment, the substrate includes a base 300 and a plurality of mutually discrete fins 301 located on the base 300.

[0051] In this embodiment, the method for forming the substrate 300 and the fin 301 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate 300 and the fin 301.

[0052] In this embodiment, the substrate 300 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0053] In this embodiment, the fin 301 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0054] Please refer to Figure 6 A second isolation layer 302 is formed on the substrate, the second isolation layer 302 covers a portion of the sidewall of the fin 301, and the top surface of the second isolation layer 302 is lower than the top surface of the fin 301.

[0055] In this embodiment, the method for forming the second isolation layer 302 includes: forming an initial isolation layer (not shown) on the substrate; etching away a portion of the initial isolation layer to form the second isolation layer 302, wherein the top surface of the second isolation layer 302 is lower than the top surface of the fin 301.

[0056] The second isolation layer 302 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the second isolation layer 302 is made of silicon oxide.

[0057] Please refer to Figure 7 After the second isolation layer 302 is formed, a plurality of mutually independent initial dummy gate structures are formed on the substrate. The initial gate structures include a first dummy gate layer 303, a first mask layer 304 located on the first dummy gate layer 303, and a second dummy gate layer 305 located on the first mask layer 304.

[0058] In this embodiment, the initial pseudo-gate structure further includes: a second mask layer 306 located on the second pseudo-gate layer 305, and a first protective layer 307 located on the second mask layer 306.

[0059] In this embodiment, the method for forming the initial pseudo-gate structure includes: forming a first pseudo-gate material layer on the substrate; forming a first pseudo-gate material layer on the first pseudo-gate material layer; forming a second pseudo-gate material layer on the first mask material layer; forming a second mask material layer on the second pseudo-gate material layer; forming a patterned first protective layer on a portion of the second mask material layer; and etching the first pseudo-gate material layer, the first mask material layer, the second pseudo-gate material layer, and the second mask material layer using the first protective layer as a mask to form the initial pseudo-gate structure (not shown).

[0060] In this embodiment, the first pseudo-gate layer 303 is made of polysilicon; the second pseudo-gate layer 305 is made of polysilicon.

[0061] In this embodiment, the material of the first mask layer 304 is silicon nitride.

[0062] In this embodiment, the widths of the initial pseudo-gate structures are different, and the spacing between adjacent initial pseudo-gate structures is different.

[0063] Please refer to Figure 8 A sidewall material layer 308 is formed on the sidewalls and top surface of the initial pseudo-gate structure.

[0064] In this embodiment, the sidewall material layer 308 is formed using atomic layer deposition.

[0065] In this embodiment, the sidewall material layer 308 is made of silicon nitride.

[0066] Please refer to Figure 9 After the sidewall material layer 308 is formed, a dielectric material layer 309 is formed on the substrate, the dielectric material layer 309 covering the sidewall of the sidewall material layer 308.

[0067] In this embodiment, the method for forming the dielectric material layer 309 includes: forming a dielectric material film (not shown) on the substrate, the dielectric material film covering the sidewall material layer; performing a fourth planarization process on the dielectric material film until the surface of the sidewall material layer 308 is exposed, thereby forming the dielectric material layer 309.

[0068] In this embodiment, the dielectric material layer 309 is made of silicon oxide.

[0069] Please refer to Figure 10 The dielectric material layer 309 and the sidewall material layer 308 are subjected to a first planarization process until the top surface of the second pseudo-gate layer 305 is exposed, forming an initial dielectric layer 310 and an initial sidewall 311. The grinding rate of the second pseudo-gate layer 305 in the first planarization process is less than the grinding rate of the dielectric material layer 309 and the sidewall material layer 308, and the grinding rate of the dielectric material layer 309 and the sidewall material layer 308 in the first planarization process is within a preset grinding rate range.

[0070] In this embodiment, the preset grinding range means that the grinding rate of the first planarization process on the medium material layer 309 and the sidewall material layer 308 is basically the same.

[0071] In this embodiment, the initial gate structure includes a first dummy gate layer 303, a first mask layer 304 located on the first dummy gate layer 303, and a second dummy gate layer 305 located on the first mask layer 304. The first planarization process has a lower polishing rate on the second dummy gate layer 305 than on the dielectric material layer 309 and the sidewall material layer 308, and the polishing rate of the first planarization process on the dielectric material layer 309 and the sidewall material layer 308 is within a preset polishing rate range. Therefore, it can be ensured that the first planarization process stops on the surface of the second dummy gate layer 305 and has a relatively flat processing interface. At the same time, it also effectively improves the uniformity of the height of the formed initial sidewall 311.

[0072] Furthermore, the top surface of the initial dielectric layer 310 is higher than the top surface of the first dummy gate layer 303, which in turn makes the top surface of the subsequently formed dielectric layer higher than the top surface of the first dummy gate layer 303. Even during the subsequent formation of the gate structure, there will be gate material layer remaining on the surface of the dielectric layer. During the subsequent planarization of the gate material layer to form the gate structure, the portion of the dielectric layer higher than the first dummy gate layer 303 will be removed. At this time, the gate material layer on the surface of the dielectric layer will also be removed, effectively avoiding the problem of short circuit between adjacent gate structures, thereby improving the performance of the final semiconductor structure.

[0073] In this embodiment, the first planarization process employs a chemical mechanical polishing process.

[0074] Please refer to Figure 11 After the first planarization process, the second pseudo-gate layer 305 and the initial sidewall 311 located on the sidewall of the second pseudo-gate layer 305 are removed to form a sidewall 312; the initial dielectric layer 310 is subjected to a second planarization process until the top surface of the first mask layer 304 is exposed to form a dielectric layer 313. The grinding rate of the initial dielectric layer 310 in the second planarization process is greater than the grinding rate of the first mask layer 304.

[0075] In this embodiment, the initial dielectric layer 310 undergoes a second planarization process until the top surface of the first mask layer 304 is exposed, forming the dielectric layer 313. This ensures that the top surface of the formed dielectric layer 313 is higher than the top surface of the first dummy gate layer 303. Even during the subsequent formation of the gate structure, some gate material layer may remain on the surface of the dielectric layer 313. During the subsequent planarization of the gate material layer to form the gate structure, the portion of the dielectric layer 313 above the first dummy gate layer 303 is removed. At this time, the gate material layer on the surface of the dielectric layer 313 is also removed, effectively avoiding the problem of short circuits between adjacent gate structures, thereby improving the performance of the final semiconductor structure.

[0076] In this embodiment, the second planarization process employs a chemical mechanical polishing process.

[0077] Please refer to Figure 12 After forming the dielectric layer 313, a patterned layer (not shown) is formed on the dielectric layer 313 and the first mask layer 304, the patterned layer exposing a portion of the top surface of the first mask layer 304; the first mask layer 304 and the first pseudo gate layer 303 are etched using the patterned layer as a mask, and an isolation opening (not shown) is formed in the dielectric layer 313; an isolation structure 314 is formed in the isolation opening.

[0078] In the manufacturing process of integrated circuits, a gate-cutting process is required to cut the strip-shaped gate. After cutting, the gate corresponds to different transistors, which can improve the integration density of transistors. Furthermore, when multiple gates are arranged in a row along the extension direction, gate cutting can precisely reduce the mating distance between the disconnected gates after cutting. In this embodiment, the initial pseudo-gate structure is cut to meet the requirements of electrical design.

[0079] In this embodiment, the isolation structure 314 includes: a first isolation layer and a second protective layer (not shown) located on the first isolation layer. The top surface of the first isolation layer is flush with the top surface of the first pseudo gate layer 303, and the top surface of the second protective layer is flush with the top surface of the dielectric layer 313.

[0080] Please refer to Figure 13 After forming the isolation structure 314, the first mask layer 304 and the sidewall 312 of the sidewall of the first mask layer 304 are removed, and a first opening (not shown) is formed in the dielectric layer 313, the first opening exposing the top surface of the first dummy gate layer 303; the first dummy gate layer 303 is removed, and a second opening (not shown) is formed in the dielectric layer 313 at the bottom of the first opening; a gate structure 315 is formed in the second opening.

[0081] In this embodiment, the method for forming the gate structure 215 includes: forming a gate material layer (not shown) in the first opening, the second opening, and on the surface of the dielectric layer 213; performing a third planarization process on the gate material layer and the dielectric layer 313 until the top surface of the sidewall 312 is exposed, thereby forming the gate structure 315.

[0082] In this embodiment, during the process of forming the gate structure 315 by performing a third planarization process on the gate material layer, the dielectric layer 313 above the first dummy gate layer 303 is removed. At this time, the gate material layer on the surface of the dielectric layer 313 is also removed, which effectively avoids the problem of short circuit between adjacent gate structures 315, thereby improving the performance of the final semiconductor structure.

[0083] In this embodiment, the third planarization process employs a chemical mechanical polishing process.

[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of mutually discrete initial pseudo-gate structures are formed on the substrate. The initial pseudo-gate structure includes a first pseudo-gate layer, a first mask layer located on the first pseudo-gate layer, and a second pseudo-gate layer located on the first mask layer. A sidewall material layer is formed on the sidewalls and top surface of the initial pseudo-gate structure; A dielectric material layer is formed on the substrate, the dielectric material layer covering the sidewalls of the sidewall material layer; The dielectric material layer and the sidewall material layer are subjected to a first planarization process until the top surface of the second pseudo-gate layer is exposed, forming an initial dielectric layer and an initial sidewall. The grinding rate of the second pseudo-gate layer in the first planarization process is less than the grinding rate of the dielectric material layer and the sidewall material layer, and the grinding rate of the dielectric material layer and the sidewall material layer in the first planarization process is within a preset grinding rate range, so that the first planarization process stops on the surface of the second pseudo-gate layer to form a flat processing interface and improve the uniformity of the height of the formed initial sidewall. After the first planarization process, the second pseudo-gate layer and the initial sidewall located on the sidewall of the second pseudo-gate layer are removed to form the sidewall; The initial dielectric layer is subjected to a second planarization process until the top surface of the first mask layer is exposed, thereby forming a dielectric layer. The second planarization process has a greater polishing rate on the initial dielectric layer than on the first mask layer. After the dielectric layer is formed, the first mask layer and the sidewalls of the first mask layer sidewalls are removed, and a first opening is formed in the dielectric layer, the first opening exposing the top surface of the first pseudo gate layer; After removing the first mask layer, the first dummy gate layer is removed, and a second opening is formed in the dielectric layer at the bottom of the first opening; A gate structure is formed within the second opening; The method for forming the gate structure includes: forming a gate material layer in the first opening, in the second opening, and on the surface of the dielectric layer; The gate material layer and the dielectric layer are subjected to a third planarization process until the top surface of the sidewall is exposed, thus forming the gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The third planarization process includes: chemical mechanical polishing.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The initial pseudo-gate structure further includes: a second mask layer located on the second pseudo-gate layer, and a first protective layer located on the second mask layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the initial pseudo-gate structure includes: forming a first pseudo-gate material layer on the substrate; forming a first mask material layer on the first pseudo-gate material layer; forming a second pseudo-gate material layer on the first mask material layer; forming a second mask material layer on the second pseudo-gate material layer; forming a patterned first protective layer on a portion of the second mask material layer; and etching the first pseudo-gate material layer, the first mask material layer, the second pseudo-gate material layer, and the second mask material layer using the first protective layer as a mask to form the initial pseudo-gate structure.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the sidewall material layer includes atomic layer deposition.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the dielectric material layer includes silicon oxide.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sidewall material layer includes silicon nitride.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first pseudo-gate layer includes polycrystalline silicon; the material of the second pseudo-gate layer includes polycrystalline silicon.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first mask layer includes silicon nitride.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first planarization process includes: chemical mechanical polishing.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second planarization process includes a chemical mechanical polishing process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the dielectric layer and before removing the first mask layer, the method further includes: forming a patterned layer on the dielectric layer and the first mask layer, the patterned layer exposing a portion of the top surface of the first mask layer; etching the first mask layer and the first pseudo-gate layer using the patterned layer as a mask to form an isolation opening in the dielectric layer; and forming an isolation structure in the isolation opening.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The isolation structure includes: a first isolation layer and a second protective layer located on the first isolation layer, wherein the top surface of the first isolation layer is flush with the top surface of the first pseudo-gate layer, and the top surface of the second protective layer is flush with the top surface of the dielectric layer.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes a base and a plurality of mutually discrete fins located on the base, the initial pseudo-gate structure spanning the fins and covering a portion of the sidewalls and top surface of the fins.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Before forming the initial pseudo-gate structure, the method further includes: forming a second isolation layer on the substrate, the second isolation layer covering a portion of the sidewall of the fin, and the top surface of the second isolation layer being lower than the top surface of the fin.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the dielectric material layer includes: forming a dielectric material film on the substrate, the dielectric material film covering the sidewall material layer; and performing a fourth planarization process on the dielectric material film until the surface of the sidewall material layer is exposed, thereby forming the dielectric material layer.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The widths of some of the initial pseudo-gate structures are different, and the spacing between adjacent initial pseudo-gate structures is different.

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