Semiconductor device, power module, and method for manufacturing semiconductor device

Abstract

A semiconductor device, a power module and a method for manufacturing a semiconductor device that can easily improve insulation resistance are obtained. The second conductor plate (2) is separated from the first conductor plate (1). The back electrodes of multiple semiconductor elements (3) are connected to the first conductor plate. A relay substrate (7) is arranged on the second conductor plate. The relay substrate (7) has multiple first relay pads (10) and second relay pads (11) connected to the multiple first relay pads. The control electrodes (4) of the multiple semiconductor elements are respectively connected to the multiple first relay pads. The first conductor block (13) is connected to the surface electrodes (5) of the multiple semiconductor elements (3). The second conductor block (14) is connected to the second relay pad (11). The first conductor plate (1) is exposed from the first main surface (S1) of the packaging material (15). The second conductor plate (2) is not exposed from the first main surface (S1). The first and second conductor blocks (14) are exposed from the second main surface (S2).

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a power module and a method for manufacturing the semiconductor device. Background Art

[0002] In a module using SiC MOSFET, it is difficult to increase the area of ​​SiC MOSFET, so multiple chips are connected in parallel to increase the current capacity. A semiconductor device has been proposed in which multiple semiconductor elements and wiring elements are bonded to the same conductor plate, and control electrodes of the multiple semiconductor elements are connected in parallel through the circuit pattern of the wiring element (for example, refer to Patent Document 1).

[0003] Patent Document 1: International Publication No. 2020 / 110170

[0004] An oxide film is provided on the wiring element for insulation of the front and back sides. In the case of current semiconductor devices, the insulation between the conductor plate at the drain potential and the circuit pattern at the control potential is ensured by the oxide film. However, in the case of high-voltage semiconductor devices such as those for electric railway drives, the oxide film required to ensure insulation becomes thicker. Therefore, the manufacturing cost increases, and the productivity decreases due to the difficulty in producing a thick oxide film, and the reliability of the thick oxide film decreases. For example, if TEOS is deposited thickly, the wafer warps, the film peels off, the surface becomes rough, and the manufacturability and quality decrease. The practice of depositing an insulating film with a withstand voltage greater than or equal to 1.7 kV by an oxide film is not common for the process of ordinary power semiconductors. Therefore, it is difficult to improve the insulation tolerance in current semiconductor devices. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device, a power module, and a method for manufacturing a semiconductor device that can easily improve dielectric strength.

[0006] The semiconductor device according to the present invention is characterized in that it comprises: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor elements whose back electrodes are connected to the first conductor plate; a relay substrate provided on the second conductor plate, the relay substrate having a plurality of first relay pads and second relay pads connected to the plurality of first relay pads; a plurality of metal wires connecting control electrodes of the plurality of semiconductor elements to the plurality of first relay pads, respectively; a first conductor block connected to the surface electrodes of the plurality of semiconductor elements; a second conductor block connected to the second relay pads; and

[0007] A packaging material that packages the first conductor plate and the second conductor plate, the plurality of semiconductor elements, the relay substrate, the metal wire, the first conductor block and the second conductor block, wherein the packaging material has a first main surface and a second main surface opposite to each other, the first conductor plate is exposed from the first main surface, the second conductor plate is not exposed from the first main surface, and the first conductor block and the second conductor block are exposed from the second main surface.

[0008] Effects of the Invention

[0009] In the present invention, the first conductor plate on which a plurality of semiconductor elements are mounted and the second conductor plate on which a relay substrate is mounted are separately packaged by a packaging material. Furthermore, the first conductor plate is exposed from the first surface of the packaging material, but the second conductor plate is not exposed from the first surface of the packaging material. Thus, the first conductor plate and the second conductor plate can be insulated, so that the insulation resistance can be easily improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a plan view showing the interior of the semiconductor device according to the first embodiment.

[0011] Figure 2 is along Figure 1 I-II sectional view.

[0012] Figure 3 It is a plan view showing the interior of a modification of the semiconductor device according to the first embodiment.

[0013] Figure 4 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0014] Figure 5 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 6 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0016] Figure 7 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0017] Figure 8 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0018] Fig. 9 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0019] Fig.10 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0020] Fig.11 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0021] Fig.12 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0022] Fig.13 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0023] Fig.14 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0024] Fig.15 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0025] Fig.16 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0026] Fig.17 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0027] Fig.18 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0028] Fig.19 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0029] Fig. 20 It is a plan view showing the manufacturing process of the semiconductor device involved in the first embodiment.

[0030] Fig.21 It is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

[0031] Fig. 22 FIG. 1 is a plan view showing a power module using a plurality of semiconductor devices according to the first embodiment.

[0032] Fig.23 It is a plan view showing the interior of the semiconductor device according to the second embodiment.

[0033] Fig.24 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0034] Fig.25 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0035] Fig.26It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0036] Fig. 27 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0037] Fig.28 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0038] Fig.29 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0039] Fig.30 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0040] Fig.31 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0041] Fig.32 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0042] Fig.33 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0043] Fig.34 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0044] Fig.35 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0045] Fig.36 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0046] Fig.37 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0047] Fig.38 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0048] Fig.39 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0049] Fig.40 It is a top view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0050] Fig.41 It is a cross-sectional view showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0051] Fig.42 It is a plan view showing the interior of a semiconductor device according to a third embodiment.

[0052] Fig.43 is along Fig.42 I-II sectional view. DETAILED DESCRIPTION

[0053] A semiconductor device, a power module, and a method for manufacturing a semiconductor device according to the embodiments will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and duplicate descriptions may be omitted.

[0054] Implementation Method 1

[0055] Figure 1 This is a plan view showing the interior of the semiconductor device according to the first embodiment. Figure 2 is along Figure 1 The second conductor plate 2 is separated from the first conductor plate 1. A plurality of semiconductor elements 3 are mounted on the first conductor plate 1. The semiconductor element 3 has a control electrode 4 and a surface electrode 5 on the surface, and a back electrode 6 on the back. When the semiconductor element 3 is a MOSFET, the control electrode 4 is a gate electrode, the surface electrode 5 is a source electrode, and the back electrode 6 is a drain electrode.

[0056] The back electrodes 6 of the plurality of semiconductor elements 3 are connected to the first conductor plate 1. One interconnect substrate 7 is mounted on the second conductor plate 2. Alternatively, a plurality of interconnect substrates 7 may be mounted on the second conductor plate 2.

[0057] A bonding film is provided on the back surface of the back electrode 6 of the semiconductor element 3 and the back surface of the relay substrate 7. The bonding film is, for example, a layer formed by a sputtering method and is a laminated film composed of Ti / Ni / Ti / Au (or Ag) from the element side, or a layer formed by a plating method and is a laminated film composed of NiP / Pd / Au from the element side. The bonding film is connected to the first conductor plate 1 or the second conductor plate 2 by, for example, sintering bonding using silver or diffusion bonding using solder. In addition, when the thermal history before bonding is small and the Ni precipitation to the outermost surface is small, Ti or Pd can be omitted from the structure of the bonding film. In addition, the material of the first conductor plate 1 and the second conductor plate 2 is a metal such as copper.

[0058] The semiconductor element 3 is a MOSFET having a plurality of control electrodes 4, such as a gate pad, a Kelvin source pad, a temperature sensing diode pad, and a current sensing source pad. In addition, as the control electrode 4, a Kelvin source pad, a temperature sensing diode pad, a current sensing source pad, etc. may also be provided as required.

[0059] The relay substrate 7 is a wiring element in which an insulating film 9 is formed on a substrate 8 made of silicon, for example, and a circuit pattern is wound on the insulating film 9. The relay substrate 7 has a plurality of first relay pads 10 and second relay pads 11 connected to the plurality of first relay pads 10 through internal wiring as the circuit pattern. The internal wiring is, for example, aluminum wiring patterned on the insulating film 9 of the relay substrate 7.

[0060] The control electrodes 4 of the plurality of semiconductor elements 3 are connected to the plurality of first relay pads 10 respectively through a plurality of metal wires 12. The metal wires 12 are, for example, thin wires made of gold or silver, and have a diameter of 100 μmφ or less. In addition, by using a wire with a diameter of 50 μmφ or less, the loop height can be reduced and the resin thickness can be suppressed.

[0061] The first conductor block 13 is connected to the surface electrodes 5 of the plurality of semiconductor elements 3. The second conductor block 14 is connected to the second relay pad 11. The first conductor block 13 and the second conductor block 14 are blocks made of metal, for example, blocks made of copper. The first conductor block 13 and the second conductor block 14 are connected to the surface electrodes 5 and the second relay pad 11, respectively, by, for example, sintering bonding using silver or diffusion bonding using solder. In addition, in order to absorb the dimensional tolerance of the second conductor block 14 and the tolerance during bonding, the second relay pad 11 may be larger than the first relay pad 10.

[0062] If the surface electrode 5 is an electrode having a bonding film further formed on the aluminum wiring, the bonding property with the first conductor block 13 can be improved. In addition, by further forming a bonding film on a part of the first and second relay pads 10 and 11 of the relay substrate 7, the connectivity with the metal wire 12 and the second conductor block 14 can be improved respectively. The bonding film is, for example, a layer formed by a sputtering method and a laminated film composed of Ti / Ni / Ti / Au (or Ag) from the element side, or a layer formed by a plating method and a laminated film composed of NiP / Pd / Au from the element side.

[0063] The packaging material 15 packages the first and second conductor plates 1, 2, a plurality of semiconductor elements 3, a relay substrate 7, a metal wire 12, and the first and second conductor blocks 13, 14. The packaging material 15 has a first main surface S1 and a second main surface S2, and a side surface S3 that are opposite to each other. The first conductor plate 1 is exposed from the first main surface S1. The second conductor plate 2 is not exposed from the first main surface S1 but is exposed from the side surface S3. The second conductor plate 2 may also be exposed from the second main surface S2. The first and second conductor blocks 13, 14 are exposed from the second main surface S2. The electrical signals outside the device and inside the device are exchanged via the first and second conductor blocks 13, 14 exposed from the packaging material 15. In addition, Figure 31 is a top view showing the inside of a modified example of the semiconductor device according to Embodiment 1. By setting a portion 1a of the first conductor plate 1 in a terminal shape protruding from the packaging material 15, it can be used as a drain sensing terminal. The drain sensing terminal monitors and outputs the drain voltage, and therefore, for example, by providing a protection circuit outside the device, as one of the overcurrent detection functions, the voltage between the drain and the source of the semiconductor element 3 when it is turned on is monitored, and unsaturation (overcurrent such as short circuit) is detected.

[0064] The semiconductor element 3 and the relay substrate 7 are packaged by the packaging material 15, and the first conductor plate 1 and the second conductor plate 2 are insulated by the packaging material 15. In addition, the packaging material 15 is not particularly limited as long as it has insulating properties, and is, for example, epoxy resin. Below the second conductor plate 2, a recessed portion 16 is provided on the first main surface S1 of the packaging material 15.

[0065] Next, a method for manufacturing the semiconductor device according to Embodiment 1 will be described. Figure 4 , 6 , 8, 10, 12, 14, 16, 18, and 20 are plan views showing the manufacturing process of the semiconductor device involved in the first embodiment. Figure 5 , 7 , 9, 11, 13, 15, 17, 19, and 21 are cross-sectional views showing the manufacturing process of the semiconductor device involved in Embodiment 1.

[0066] First, if Figure 4 and Figure 5 As shown in FIG. 1 , the first conductor plate 1 and the second conductor plate 2 are prepared to be integrated with the external frame 17 and separated from each other. Figure 6 and Figure 7 As shown, in order to connect a plurality of semiconductor elements 3 to the first conductor plate 1, the back electrodes 6 of the plurality of semiconductor elements 3 are connected to the first conductor plate 1 by silver or solder. The relay substrate 7 is similarly connected to the second conductor plate 2. In addition, the description of the connection method is repeated and therefore omitted.

[0067] Next, if Figure 8 and Fig. 9 As shown, the first conductor block 13 is connected to the surface electrodes 5 of the plurality of semiconductor elements 3. The second conductor block 14 is connected to the second relay pad 11.

[0068] Next, if Fig.10 and Fig.11As shown, the control electrodes 4 of the plurality of semiconductor elements 3 and the plurality of first relay pads 10 are connected respectively by the plurality of metal wires 12. In this way, the connection is performed by the metal wires 12 after the first and second conductor blocks 13 and 14 are connected, thereby eliminating the possibility of interference between the metal wires 12 and the first and second conductor blocks 13 and 14 when connected. Therefore, the degree of freedom of the clamp used is expanded, so that the process of connecting the first and second conductor blocks 13 and 14 can be easily performed. In addition, the process of connecting by the metal wires 12 can also be performed before connecting the first and second conductor blocks 13 and 14. By first performing the process of connecting by the metal wires 12, the movable area of ​​the wire bonding tool for wire bonding is expanded, thereby improving the wire bonding control.

[0069] Next, if Fig.12 and Fig.13 As shown, the first and second conductor plates 1, 2, a plurality of semiconductor elements 3, a relay substrate 7, a metal wire 12, and the first and second conductor blocks 13, 14 are packaged by a packaging material 15. At this time, the first conductor plate 1 is exposed from the first main surface S1, and the second conductor plate 2 is not exposed from the first main surface S1.

[0070] Next, if Fig.14 and Fig.15 As shown in FIG. 1 , the second main surface S2 of the packaging material 15 is ground so that the first and second conductor blocks 13 and 14 are exposed from the second main surface S2. Fig.16 and Fig.17 As shown, the connection between the external frame 17 and the second conductor plate 2, which will become an integral part, is cut off to separate them from each other. In addition, when cutting, the cutting blade is separated from the packaging material 15 by an amount of interval larger than the blade width. Thus, the packaging material 15 is not damaged when cutting, and productivity is improved.

[0071] Next, if Fig.18 and Fig.19 As shown, the first conductor block 13 applies a drain voltage, which becomes a source potential, to the first conductor plate 1, and applies a gate signal to the second conductor block 14, thereby implementing a screening test for semiconductor devices for eliminating defective products. Fig. 20 and Fig.21 As shown, the connection between the outer frame 17 and the first conductor plate 1 is cut to separate them from each other. In addition, the cutting blade is separated from the packaging material 15 by a gap larger than the blade width during cutting. Thus, the packaging material 15 is not damaged during cutting, and productivity is improved.

[0072] Fig. 221 is a top view showing a power module using a plurality of semiconductor devices according to Embodiment 1. The first semiconductor device 18 and the second semiconductor device 19 are the semiconductor devices described above. The first conductor plate 1 of the first semiconductor device 18 is connected to the first circuit pattern 20 by a bonding material such as solder or a sintered material. The first conductor block 13 of the first semiconductor device 18 is connected to the second circuit pattern 22 by a wiring 21. The first conductor plate 1 of the second semiconductor device 19 is connected to the second circuit pattern 22 by a bonding material. The first conductor block 13 of the second semiconductor device 19 is connected to the third circuit pattern 24 by a wiring 23. In this way, the first semiconductor device 18 and the second semiconductor device 19 are used for the upper bridge arm and the lower bridge arm, respectively, to form a half-bridge circuit. In addition, the wirings 21 and 23 may be wirings obtained by ultrasonically bonding a wire or a strip made of aluminum or copper, or wirings obtained by connecting a frame made of copper by a bonding material such as solder or a sintered material.

[0073] The peripheral encapsulation material 30 such as gel or epoxy resin encapsulates the first and second semiconductor devices 18, 19, the first, second and third circuit patterns 20, 22, 24 to achieve insulation from the outside. The peripheral encapsulation material 30 insulates the circuit patterns and insulates the exposed surface of the second conductor plate 2 of the first semiconductor device 18 and the second semiconductor device 19 exposed from the side of the encapsulation material 15 from the second and third circuit patterns 22, 24 respectively. In addition, a cutout 25 is provided in the second circuit pattern 22 opposite to the exposed surface of the second conductor plate 2 of the second semiconductor device 19. Thus, the insulation distance between the second conductor plate 2 of the source potential and the second circuit pattern 22 of the drain potential can be lengthened. Similarly, a cutout 25 is provided in the third circuit pattern 24 opposite to the exposed surface of the second conductor plate 2 of the first semiconductor device 18. In addition, it is preferred that the cutout 25 has a size that allows the peripheral encapsulation material 30 to enter.

[0074] As described above, in this embodiment, the first conductor plate 1 on which the plurality of semiconductor elements 3 are mounted and the second conductor plate 2 on which the relay substrate 7 is mounted are separately packaged by the packaging material 15. Furthermore, the first conductor plate 1 is exposed from the first main surface S1 of the packaging material 15, but the second conductor plate 2 is not exposed from the first main surface S1 of the packaging material 15. Thus, the first conductor plate 1 and the second conductor plate 2 can be insulated, and thus the insulation resistance can be easily improved.

[0075] In addition, the control electrodes 4 of the plurality of semiconductor elements 3 are connected in parallel through the relay substrate 7. The back electrode 6 of the semiconductor element 3 is a drain electrode, and the front electrode 5 is a source electrode. Thus, the semiconductor device as a whole is equivalent to a MOSFET in which the second conductor block 14 is used as a gate electrode, the first conductor block 13 is used as a source electrode, and the first conductor plate 1 is used as a drain electrode. Thus, cost reduction and miniaturization of the semiconductor device can be achieved by improving the assemblability of the semiconductor device.

[0076] In addition, when the semiconductor device is connected to the circuit pattern of the insulating substrate, the high potential of the circuit pattern is applied to the first conductor plate 1. On the other hand, the low potential of the lower surface of the relay substrate 7 is applied to the second conductor plate 2. Therefore, a recessed portion 16 is provided on the first main surface S1 of the packaging material 15 below the second conductor plate 2. As a result, the creepage distance between the exposed portion of the first conductor plate 1 and the exposed portion of the second conductor plate 2 can be extended, so that the insulation resistance can be further improved. However, the recessed portion 16 may not be provided.

[0077] In addition, before packaging by the packaging material 15, the first conductor plate 1 and the second conductor plate 2 are integrated with the external frame 17. Therefore, the first conductor plate 1 and the second conductor plate 2 are an integral part before the packaging is completed. After packaging by the packaging material 15, the first conductor plate 1 and the second conductor plate 2 are cut off from the frame 17. As a result, the manufacture of the semiconductor device becomes easy. In addition, a plurality of semiconductor devices can be manufactured at one time, thereby reducing the manufacturing cost. Furthermore, by integrating with the external frame 17, the position control of the first conductor plate 1 and the second conductor plate 2 becomes easy, and the insulation can be easily ensured, thereby improving the yield of the semiconductor device.

[0078] In addition, after the second conductor plate 2 is cut and before the first conductor plate 1 is cut, a screening test for semiconductor devices for eliminating defective products is performed. By performing the screening test before the first conductor plate 1 is cut, the drain potentials of a plurality of semiconductor devices can be connected at the same time, so the screening test can be performed efficiently. In addition, the positional accuracy of the first and second conductor blocks 13 and 14 corresponding to the source electrodes and control electrodes of the plurality of semiconductor devices becomes high, so that the potential can be easily obtained. As a result, the screening test of a plurality of semiconductor devices can be performed at the same time, and the manufacturing cost of the semiconductor devices can be suppressed.

[0079] Implementation Method 2

[0080] Fig.231 is a top view showing the inside of the semiconductor device according to Embodiment 2. A cutout 26 is provided in the packaging material 15. The cutout 26 is disposed between the separated first conductor plate 1 and the second conductor plate 2. The cut surfaces of the first conductor plate 1 and the second conductor plate 2 are exposed at the cutout 26, but when constituting a power module, the semiconductor device is covered with a peripheral packaging material 30, thereby improving the insulation of the first conductor plate 1 and the second conductor plate 2.

[0081] Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. Fig.24 , 26 , 28, 30, 32, 34, 36, 38, and 40 are top views showing the manufacturing process of the semiconductor device involved in the second embodiment. Fig.25 , 27 , 29, 31, 33, 35, 37, 39, and 41 are cross-sectional views showing the manufacturing process of the semiconductor device involved in the second embodiment.

[0082] First, if Fig.24 and Fig.25 As shown in FIG. 1 , the first conductor plate 1 and the second conductor plate 2 are integrated with the external frame 17 and connected to each other via the bridge portion 27. Next, as shown in FIG. Fig.26 and Fig. 27 As shown, in order to connect the plurality of semiconductor elements 3 to the first conductor plate 1, the back electrodes 6 of the plurality of semiconductor elements 3 are connected to the first conductor plate 1 by silver or solder. The second conductor plate 2 is also connected to the interconnect substrate 7 in the same manner.

[0083] Next, if Fig.28 and Fig.29 As shown, the first conductor block 13 is connected to the surface electrodes 5 of the plurality of semiconductor elements 3. The second conductor block 14 is connected to the second relay pad 11.

[0084] Next, if Fig.30 and Fig.31 As shown, the control electrodes 4 of the plurality of semiconductor elements 3 and the plurality of first relay pads 10 are connected via a plurality of metal wires 12 , respectively.

[0085] Next, if Fig.32 and Fig.33 As shown, the first and second conductor plates 1, 2, the plurality of semiconductor elements 3, the interconnect substrate 7, the metal wires 12, and the first and second conductor blocks 14 are packaged by the packaging material 15. At this time, the packaging material 15 is provided with a cutout portion 26 for exposing the bridge portion 27.

[0086] Next, if Fig.34 and Fig.35As shown in FIG. 1 , the second main surface S2 of the packaging material 15 is ground so that the first and second conductor blocks 13 and 14 are exposed from the second main surface S2. Fig.36 and Fig.37 As shown, the bridge portion 27 exposed at the cutout portion 26 is cut to separate the first conductor plate 1 and the second conductor plate 2 from each other.

[0087] Next, if Fig.38 and Fig.39 As shown, the first conductor block 13 is electrically connected to the source electrode, i.e., the surface electrode 5, and the first conductor plate 1 is electrically connected to the drain electrode, i.e., the back electrode 6. In addition, the second conductor block 14 is electrically connected to the gate electrode, i.e., the control electrode 4. By applying a voltage between the first conductor block 13 and the first conductor plate 1, thereby applying a voltage between the source electrode and the drain electrode, and by applying a voltage to the second conductor block 14, thereby applying a voltage to the gate electrode, a screening test for semiconductor devices for eliminating defective products is implemented. At this time, the insulation between the first conductor plate 1 and the second conductor plate 2 can also be ensured by sandwiching an insulating plate at the cutout portion 26. Finally, as shown Fig.40 and Fig.41 As shown in FIG. 1 , the connection portion between the external frame 17 and the first conductor plate 1 is cut to separate them from each other.

[0088] As described above, in this embodiment, the second conductor plate 2 is connected to the first conductor plate 1 not through the external frame 17 but through the bridge portion 27. Therefore, the first conductor plate 1 and the second conductor plate 2 are more firmly fixed, and the deflection of the second conductor plate 2 caused by the pressing force during wire bonding is suppressed, thereby improving the yield rate.

[0089] In addition, when the material of the wire is Au, the material may be heated. By connecting the first conductor plate 1 and the second conductor plate 2 via the bridge portion 27, both can be heated, thereby improving the bonding properties of the wire bonding.

[0090] Implementation 3

[0091] Fig.42 It is a plan view showing the interior of a semiconductor device according to a third embodiment. Fig.43 is along Fig.42 sectional view taken along the line I-II of FIG. A source conductor block 28 is connected to the second conductor plate 2. The source pads 29 of the plurality of semiconductor elements 3 are connected to the second conductor plate 2 via wires 31. The first relay pads 10 and the second relay pads 11 of the relay substrate 7 are insulated from the second conductor plate 2 and the source conductor block 28 via an insulating film 9. In addition, there may be a plurality of source conductor blocks 28.

[0092] The source conductor block 28 is exposed from the second main surface S2 of the packaging material 15 and functions as a source control electrode. As a result, the second conductor plate 2 can be fixed to the source potential, so the floating part can be eliminated. Therefore, when the semiconductor device is turned on and off at high speed and the voltage vibrates sharply, unexpected voltage damage can be prevented. In addition, the exposed portion of the second conductor plate 2 can be used as a source control electrode instead of the source conductor block 28. In this case, a part of the second conductor plate 2 can be deformed in a manner that is exposed at a suitable position for serving as a source control electrode. In addition, the source pad and its lead wiring at the relay substrate 7 can be reduced, so the size of the relay substrate 7 can also be reduced.

[0093] In addition, the semiconductor element 3 is not limited to being formed by silicon, and can also be formed by a wide bandgap semiconductor having a larger bandgap than silicon. Examples of wide bandgap semiconductors are silicon carbide, gallium nitride materials, or diamond. Semiconductor elements formed by such wide bandgap semiconductors can be miniaturized due to their high voltage resistance and allowable current density. By using the miniaturized semiconductor element, a semiconductor device in which the semiconductor element is assembled can also be miniaturized and highly integrated. In addition, since the semiconductor element has high heat resistance, the heat dissipation fins of the radiator can be miniaturized, and the water cooling part can be air-cooled, thereby further miniaturizing the semiconductor device. In addition, since the power loss of the semiconductor element is low and efficient, the semiconductor device can be made efficient.

[0094] Description of the label

[0095] 1 1st conductor plate, 2 2nd conductor plate, 3 semiconductor element, 6 back electrode, 7 relay substrate, 10 1st relay pad, 11 2nd relay pad, 12 metal wire, 13 1st conductor block, 14 2nd conductor block, 15 packaging material, 16 recessed portion, 17 frame, 20 1st circuit pattern, 22 2nd circuit pattern, 24 3rd circuit pattern, 25, 26 cutout portion, 27 bridge portion, 28 source conductor block, 30 peripheral packaging material, S1 1st main surface, S2 2nd main surface

Claims

1. A semiconductor device, characterized in that: have: The first conductor plate; a second conductor plate, which is separated from the first conductor plate; A plurality of semiconductor elements, the back electrodes of which are connected to the first conductor plate; a relay substrate disposed on the second conductor plate, the relay substrate having a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires connecting the control electrodes of the plurality of semiconductor elements to the plurality of first relay pads, respectively; a first conductor block connected to the surface electrodes of the plurality of semiconductor elements; a second conductor block connected to the second relay pad; as well as a packaging material that packages the first and second conductor plates, the plurality of semiconductor elements, the interconnect substrate, the metal wires, the first and second conductor blocks, The packaging material has a first main surface and a second main surface facing each other, The first conductor plate is exposed from the first main surface. The second conductor plate is not exposed from the first main surface, The first conductor block and the second conductor block are exposed from the second main surface.

2. The semiconductor device according to claim 1, wherein: The back electrode is a drain electrode, and the surface electrode is a source electrode.

3. The semiconductor device according to claim 1, wherein: A recessed portion is provided on the first main surface of the packaging material below the second conductor plate.

4. The semiconductor device according to claim 2, wherein: A recessed portion is provided on the first main surface of the packaging material below the second conductor plate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The package further includes a source conductor block connected to the second conductor plate, the source conductor block being exposed from the second main surface of the package material.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that The semiconductor element is formed of a wide bandgap semiconductor.

7. The semiconductor device according to claim 5, wherein: The semiconductor element is formed of a wide bandgap semiconductor.

8. A power module, characterized in that: have: A first semiconductor device and a second semiconductor device, each of which is a semiconductor device according to any one of claims 1 to 7; a first circuit pattern connected to the first conductor plate of the first semiconductor device; a second circuit pattern connected to the first conductor block of the first semiconductor device and the first conductor plate of the second semiconductor device; a third circuit pattern connected to the first conductor block of the second semiconductor device; as well as A peripheral packaging material packages the first semiconductor device, the second semiconductor device, the first circuit pattern, the second circuit pattern, and the third circuit pattern.

9. The power module according to claim 8, characterized in that: A cutout portion is provided in the second circuit pattern so as to face an exposed surface of the second conductor plate of the second semiconductor device that is exposed from a side surface of the packaging material.

10. A method for manufacturing a semiconductor device, characterized in that: It has the following processes: Mounting a plurality of semiconductor elements on a first conductor plate, and connecting back electrodes of the plurality of semiconductor elements to the first conductor plate; Mounting a relay substrate on a second conductor plate separated from the first conductor plate, the relay substrate having a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; Connecting a first conductor block to surface electrodes of the plurality of semiconductor elements; Connecting a second conductor block to the second relay pad; connecting the control electrodes of the plurality of semiconductor elements and the plurality of first relay pads respectively through a plurality of metal wires; as well as The first and second conductor plates, the plurality of semiconductor elements, the interconnect substrate, the metal wires, the first and second conductor blocks are packaged with a packaging material. The packaging material has a first main surface and a second main surface facing each other, The first conductor plate is exposed from the first main surface of the package material, the second conductor plate is not exposed from the first main surface, and the first conductor block and the second conductor block are exposed from the second main surface.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Before being packaged by the packaging material, the first conductor plate and the second conductor plate are integrated with the frame. After being encapsulated by the encapsulation material, the first conductor plate and the second conductor plate are cut off from the frame.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: A screening test of the semiconductor device is performed after the second conductor plate is cut and before the first conductor plate is cut.

13. The method for manufacturing a semiconductor device according to claim 10, wherein: Before being packaged by the packaging material, the first conductor plate and the second conductor plate are connected by a bridge portion. When the packaging is performed by the packaging material, a cutout portion is provided in the packaging material to expose the bridge portion. After encapsulation with the encapsulation material, the bridge portion exposed at the cutout portion is cut off.

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