Semiconductor memory device

Abstract

The semiconductor memory device of the embodiment includes: a substrate; a first conductive layer spaced apart from the substrate in a first direction and extending in a second direction; a second conductive layer and a third conductive layer spaced apart from the substrate and the first conductive layer in the first direction and arranged in the second direction; a first semiconductor layer facing the first and second conductive layers; a second semiconductor layer facing the first and third conductive layers; a first bit line electrically connected to the first semiconductor layer; and a second bit line electrically connected to the second semiconductor layer. At least a portion of the operating parameters when performing a specific operation on a memory cell corresponding to the first conductive layer is different from at least a portion of the operating parameters when performing a specific operation on a memory cell corresponding to the second and third conductive layers.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-10074 (filed on January 26, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes: a substrate; a plurality of conductive layers deposited in a direction intersecting with the surface of the substrate; a semiconductor layer facing the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layers. The gate insulating layer has a memory section capable of storing data, such as an insulating charge storage layer like silicon nitride (Si3N4) or a conductive charge storage layer like a floating gate. Summary of the Invention

[0005] The implementation provides a semiconductor memory device that operates well.

[0006] A semiconductor memory device according to one embodiment includes: a substrate; a first conductive layer that is spaced apart from the substrate in a first direction intersecting the substrate surface and extends in a second direction intersecting the first direction; a second conductive layer that is spaced apart from the substrate and the first conductive layer in the first direction and extends in the second direction; a third conductive layer that is spaced apart from the substrate and the first conductive layer in the first direction, extends in the second direction, is aligned with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; and a first semiconductor layer that extends in the first direction and is connected to the first conductive layer. The first and second conductive layers are opposite each other; a first charge storage unit is disposed between the first conductive layer and the first semiconductor layer; a second charge storage unit is disposed between the second conductive layer and the first semiconductor layer; the second semiconductor layer extends in a first direction and is opposite to the first conductive layer and the third conductive layer; a third charge storage unit is disposed between the first conductive layer and the second semiconductor layer; a fourth charge storage unit is disposed between the third conductive layer and the second semiconductor layer; a first bit line is electrically connected to the first semiconductor layer; and a second bit line is electrically connected to the second semiconductor layer. For example, when a specific operation is performed on the first memory cell including the first charge storage unit, the magnitude and supply time of one or more voltages supplied to the first conductive layer, the magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing begins, and the sensing time are set as the first operation parameters. Furthermore, when performing a specific operation on a second storage cell containing a second charge storage section, the magnitude and supply time of one or more voltages supplied to the second and third conductive layers, the magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing begins, and the sensing time are set as second operation parameters. In this case, at least a portion of the second operation parameters differs from at least a portion of the first operation parameters.

[0007] A semiconductor memory device according to one embodiment includes: a substrate; a first conductive layer that is spaced apart from the substrate in a first direction intersecting the substrate surface and extends in a second direction intersecting the first direction; a second conductive layer that is spaced apart from the substrate and the first conductive layer in a first direction and extends in a second direction; a third conductive layer that is spaced apart from the substrate and the first conductive layer in a first direction, extends in a second direction, is aligned with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; a first semiconductor layer that extends in a first direction and faces the first conductive layer and the second conductive layer; a second semiconductor layer that extends in a first direction and faces the first conductive layer and the third conductive layer; a first wiring that is electrically connected to the first conductive layer, the second conductive layer, and the third conductive layer; an operating voltage output circuit that is electrically connected to the first wiring; and a variable resistor circuit that is disposed on the current path between the first wiring and the operating voltage output circuit.

[0008] A semiconductor memory device according to one embodiment includes: a substrate; a first conductive layer that is spaced apart from the substrate in a first direction intersecting the substrate surface and extends in a second direction intersecting the first direction; a second conductive layer that is spaced apart from the substrate and the first conductive layer in a first direction and extends in a second direction; a third conductive layer that is spaced apart from the substrate and the first conductive layer in a first direction, extends in a second direction, is aligned with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; a first semiconductor layer that extends in a first direction and faces the first and second conductive layers; a second semiconductor layer that extends in a first direction and faces the first and third conductive layers; and a fourth conductive layer. A first conductive layer is disposed between a substrate and a first conductive layer, connecting one end of the first semiconductor layer and one end of the second semiconductor layer; a first wiring is disposed between a substrate and a fourth conductive layer, electrically connecting the second conductive layer and the third conductive layer; a first contact extends in a first direction, one end of the first direction being closer to the substrate than the fourth conductive layer, and the other end of the first direction being farther from the substrate than the second conductive layer, and is disposed on the current path of the second conductive layer and the first wiring; and a second contact extends in a first direction, one end of the first direction being closer to the substrate than the fourth conductive layer, and the other end of the first direction being farther from the substrate than the third conductive layer, and is disposed on the current path of the third conductive layer and the first wiring. Attached Figure Description

[0009] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0010] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment.

[0011] Figure 3 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0012] Figure 4 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0013] Figure 5 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0014] Figure 6 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0015] Figure 7 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0016] Figure 8 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0017] Figure 9 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0018] Figure 10 This is a schematic top view of a memory die (MD).

[0019] Figure 11 This is a schematic cross-sectional view of a memory die (MD).

[0020] Figure 12 yes Figure 10 A schematic enlarged view of part A shown in the diagram.

[0021] Figure 13 It is an omission Figure 12 The diagram shows a schematic top view representing a portion of the structure.

[0022] Figure 14 It is an omission Figure 12 The diagram shows a schematic top view representing a portion of the structure.

[0023] Figure 15 It is an omission Figure 12 The diagram shows a schematic top view representing a portion of the structure.

[0024] Figure 16 It is an omission Figure 12 The diagram shows a schematic top view representing a portion of the structure.

[0025] Figure 17 yes Figure 10 A schematic enlarged view of part B shown.

[0026] Figure 18 yes Figure 17 A schematic enlarged view of part C.

[0027] Figure 19 yes Figure 11 A schematic enlarged view of part D.

[0028] Figure 20 yes Figure 12 A schematic enlarged view.

[0029] Figure 21 It is Figure 20 The structure shown is a schematic cross-sectional view taken along line E-E' and viewed in the direction of the arrow.

[0030] Figure 22A It is a schematic histogram used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0031] Figure 22BThis is a table illustrating the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data.

[0032] Figure 22C This is another example of a table showing the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data.

[0033] Figure 23 It is a schematic cross-sectional view used to illustrate the reading action.

[0034] Figure 24 It is a timing diagram used to explain the reading action.

[0035] Figure 25 This is a timing diagram used to explain the read operation of the semiconductor memory device in the second embodiment.

[0036] Figure 26 This is a flowchart used to explain the write operation of the semiconductor memory device in the third embodiment.

[0037] Figure 27 It is a schematic cross-sectional view used to illustrate the programming actions contained in the write operation.

[0038] Figure 28 It is a schematic cross-sectional view used to illustrate the verification actions included in the write operation.

[0039] Figure 29 It is a timing diagram used to illustrate the write operation.

[0040] Figure 30 It is a timing diagram used to illustrate the write operation.

[0041] Figure 31 This is a timing diagram used to explain the write operation of the semiconductor memory device in the fourth embodiment.

[0042] Figure 32 This is a schematic circuit diagram illustrating a portion of the semiconductor memory device according to the fifth embodiment.

[0043] Figure 33 This is a schematic circuit diagram showing the configuration of the variable resistor circuit VR1.

[0044] Figure 34 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the sixth embodiment.

[0045] Figure 35 It is an omission Figure 34 A schematic top view representing a part of the composition.

[0046] Figure 36This is a schematic top view used to illustrate a variation of the semiconductor memory device of the sixth embodiment.

[0047] Figure 37 This is a schematic top view used to illustrate a variation of the semiconductor memory device of the sixth embodiment. Detailed Implementation

[0048] Next, with reference to the accompanying drawings, the semiconductor memory device according to the embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and some components may be omitted for ease of explanation. Furthermore, common parts in multiple embodiments may be labeled with the same reference numerals, and descriptions may be omitted.

[0049] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0050] Furthermore, in this specification, the term "control circuit" sometimes refers to peripheral circuits such as a sequence generator installed on the memory die, sometimes refers to a controller die or controller chip connected to the memory die, and sometimes refers to a configuration that includes both of the above.

[0051] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, the first component can be directly connected to the second component, or the first component can be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0052] Furthermore, in this specification, when it is mentioned that the first component is "connected between" the second and third components, it is intended to mean that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0053] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0054] Furthermore, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0055] Furthermore, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction intersecting the first direction along the specific surface is referred to as the second direction, and the direction intersecting the specific surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any one of the X, Y, and Z directions.

[0056] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a component as a lower surface or lower end, it means the surface or end of the component on the substrate side; when referring to an upper surface or upper end, it means the surface or end of the component opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0057] [First Implementation]

[0058] [Memory System 10]

[0059] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10 in the first embodiment.

[0060] The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host computer 20. The memory system 10 may be, for example, a memory chip, memory card, SSD, or other system capable of storing user data. The memory system 10 includes multiple memory dies (MD) and controller dies (CD).

[0061] The memory die (MD) stores user data. The memory die (MD) comprises multiple memory blocks (BLKs). Each memory block (BLK) comprises multiple page blocks (PGs). The memory block (BLK) can also be the unit for erasure operations. The page (PG) can also be the unit for read and write operations.

[0062] controller bare CD such as Figure 1 As shown, multiple memory dies (MD) and a host computer (CD) are connected. The controller dies (CD) include, for example, a logic translation table (21), a file allocation table (FAT) (22), an erase count storage unit (23), an error correction code (ECC) circuit (24), and an MPU (Micro Processor Unit) (25).

[0063] The logical translation table 21 establishes a correspondence between the logical addresses received from the host computer 20 and the physical addresses of the pages PG allocated in the memory die MD, and stores them. The logical translation table 21 is implemented using, for example, RAM (Random Access Memory) not shown.

[0064] FAT22 stores FAT information indicating the status of each page group (PG). This FAT information includes, for example, information indicating "valid," "invalid," and "erased." For instance, a "valid" page PG stores valid data read according to commands from the host computer 20. Conversely, an "invalid" page PG stores invalid data that was not read according to commands from the host computer 20. Furthermore, in an "erased" page PG, no data was stored after the erasure process was performed. FAT22 is implemented using, for example, RAM (not shown).

[0065] The erase count storage unit 23 establishes and stores a correspondence between the physical address corresponding to the memory block BLK and the number of erase operations performed on the memory block BLK. The erase count storage unit 23 is implemented using, for example, RAM (not shown).

[0066] ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data if possible.

[0067] The MPU25 references the logic translation table 21, FAT22, erase count storage unit 23, and ECC circuit 24 to perform logic address to physical address conversion, bit error detection / correction, garbage collection (compression), wear leveling, and other processing.

[0068] [Circuit configuration of a memory die (MD)]

[0069] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figures 3-9 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0070] in addition, Figure 2 The diagram shows multiple control terminals. There are cases where these control terminals are represented as control terminals corresponding to a high-state active signal (positive logic signal). Additionally, there are cases where multiple control terminals are represented as control terminals corresponding to a low-state active signal (negative logic signal). Furthermore, there are cases where multiple control terminals are represented as control terminals corresponding to both a high-state active signal and a low-state active signal. Figure 2In this specification, the symbol for the control terminal corresponding to the active low-state signal includes an overline (high line). Additionally, the symbol for the control terminal corresponding to the active low-state signal includes a forward slash (" / "). Figure 2 Taking the record as an example, the specific form can be adjusted appropriately. For example, some or all of the high-state valid signals can be set as low-state valid signals, or some or all of the low-state valid signals can be set as high-state valid signals.

[0071] like Figure 2 As shown, the memory die MD includes a memory cell array MCA and peripheral circuitry PC. The PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequence generator SQC. Furthermore, the PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Additionally, the PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0072] [Circuit configuration of a memory cell array (MCA)]

[0073] Storage cell array MCA such as Figure 3 As shown, the system comprises multiple memory blocks BLK. Each memory block BLK has multiple string units SU. Each string unit SU has multiple memory strings MS. One end of each memory string MS is connected to the peripheral circuit PC via a bit line BL. Furthermore, the other end of each memory string MS is connected to the peripheral circuit PC via a common source line SL.

[0074] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. Hereinafter, the STD, STS, and STSb are sometimes simply referred to as the select transistors (STD, STS, STSb).

[0075] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to one memory string MS. These word lines WL are collectively connected to all memory strings MS in one memory block BLK.

[0076] The select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines (SGD, SGS, SGSb) are connected to the gate electrodes of the select transistors (STD, STS, STSb). One drain-side select gate line SGD connects to all memory strings MS in a single string cell SU. One source-side select gate line SGS connects to all memory strings MS in a single memory block BLK. One source-side select gate line SGSb connects to all memory strings MS in a single memory block BLK.

[0077] [Circuit configuration of voltage generation circuit VG]

[0078] Voltage generation circuit VG ( Figure 2 For example, Figure 4 As shown, the device includes multiple voltage generation units vg1 to vg3. During read, write, and erase operations, the voltage generation units vg1 to vg3 generate voltages of specific magnitudes, which are then supplied via voltage supply line L. VG Output. For example, during a write operation, the voltage generation unit vg1 outputs the programming voltage V, which will be described later. PGM Furthermore, during the readout operation, the voltage generation unit vg2 outputs the readout path voltage V, which will be described later. READ Furthermore, during the write operation, the voltage generation unit vg2 outputs the write path voltage V, which will be described later. PASS Furthermore, during the read operation, voltage generation unit vg3 outputs the read voltage (described later). Furthermore, during the write operation, voltage generation unit vg3 outputs the verification voltage (described later). Voltage generation units vg1 to vg3 can be, for example, boost circuits such as charge pump circuits, or buck circuits such as regulators. The buck circuit and boost circuit are respectively connected to the voltage supply line L. P For voltage supply line L P Supply voltage V CC or ground voltage V SS ( Figure 2 The voltage supply line L) P For example, it is connected to the pad electrode P. The operating voltage output from the voltage generation circuit VG is adjusted appropriately based on the control signal from the sequence generator SQC.

[0079] For example, the charge pump circuit 32 in the voltage generation circuit VG Figure 5 As shown, it includes a voltage output circuit 32a, a voltage divider circuit 32b, and a comparator 32c. The voltage output circuit 32a supplies voltage to line L. VG Output voltage V OUTThe voltage divider circuit 32b is connected to the voltage supply line L. VG Comparator 32c operates based on the voltage V output from voltage divider circuit 32b. OUT 'With reference voltage V REF The magnitude of the signal corresponds to the output feedback signal FB of the voltage output circuit 32a.

[0080] Voltage output circuit 32a, such as Figure 6 As shown, it includes multiple transistors 32a2a and 32a2b. These transistors 32a2a and 32a2b are alternately connected on the voltage supply line L. VG and voltage supply line L P Interval. For the voltage supply line L shown in the diagram. P Supply voltage V CC The gate electrodes of multiple transistors 32a2a and 32a2b connected in series are connected to their respective drain electrodes and capacitors 32a3. Furthermore, the voltage output circuit 32a includes an AND circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The AND circuit 32a4 outputs a logical sum of a clock signal CLK and a feedback signal FB. The level shifter 32a5a boosts the output signal of the AND circuit 32a4 and outputs it. The output terminal of the level shifter 32a5a is connected to the gate electrode of transistor 32a2a via capacitor 32a3. The level shifter 32a5b boosts the inverted signal of the output signal of the AND circuit 32a4 and outputs it. The output terminal of the level shifter 32a5b is connected to the gate electrode of transistor 32a2b via capacitor 32a3.

[0081] When the feedback signal FB is in the "H (high)" state, the clock signal CLK is output from the AND circuit 32a4. Simultaneously, electrons are drawn from the voltage supply line L... VG Transferred to voltage supply line L P Voltage supply line L VG The voltage increases. On the other hand, when the feedback signal FB is in the "L (low)" state, the clock signal CLK is not output from the AND circuit 32a4. Therefore, the voltage supply line L... VG The voltage does not increase.

[0082] Voltage divider circuit 32b, such as Figure 5 As shown, it includes a resistive element 32b2 and a variable resistive element 32b4. The resistive element 32b2 is connected to the voltage supply line L. VG The variable resistor element 32b4 is connected in series between the voltage divider terminal 32b1 and the voltage supply line L. P Interval. For the voltage supply line L P Supply ground voltage V SSThe resistance value of the variable resistor element 32b4 can be adjusted according to the operating voltage control signal V. CTRL Adjustment. Therefore, the voltage V at voltage divider terminal 32b1... OUT The size of ' can be controlled by the operating voltage control signal V CTRL Adjustment.

[0083] Variable resistor element 32b4, such as Figure 7 As shown, it has multiple current paths 32b5. These multiple current paths 32b5 are connected in parallel to the voltage divider terminal 32b1 and the voltage supply line L. P Multiple current paths 32b5 each have a resistor element 32b6 and a transistor 32b7 connected in series. The resistance values ​​of the resistor elements 32b6 in each current path 32b5 can be different. An operating voltage control signal V is input to the gate electrode of each transistor 32b7. CTRL Different bits. In addition, the variable resistor element 32b4 may also have a current path 32b8 that does not include transistor 32b7.

[0084] Comparator 32c, such as Figure 5 As shown, the output feedback signal FB. The feedback signal FB is, for example, the voltage V at voltage divider terminal 32b1. OUT 'Greater than the reference voltage V' REF In this case, it becomes the "L" state. Furthermore, the feedback signal FB, for example, is in the voltage V. OUT Less than the reference voltage V REF In this case, it becomes the "H" state.

[0085] [Circuit configuration of the row decoder RD]

[0086] Line decoder RD, for example Figure 4 As shown, it includes a block decoder (BLKD), a word line decoder (WLD), a driver circuit (DRV), and an address decoder (not shown).

[0087] The block decoder BLKD has multiple block decoding units blkd. These multiple block decoding units blkd correspond to multiple memory blocks BLK in the memory cell array MCA. Each block decoding unit blkd has multiple transistors T. BLK Multiple transistors T BLK Corresponding to multiple word lines WL in the memory block BLK. Transistor T BLK For example, a field-effect NMOS (N-Metal-Oxide-Semiconductor) transistor. Transistor T BLK The drain electrode of transistor T is connected to word line WL. BLK The source electrode is connected to the wiring CG. The wiring CG is connected to all block decoding units (blkd) in the block decoder BLKD. Transistor TBLK The gate electrode is connected to the signal line BLKSEL. Multiple signal lines BLKSEL are provided corresponding to all block decoding units (blkd). Furthermore, the signal line BLKSEL is connected to all transistors T in the block decoding unit (blkd). BLK .

[0088] In read and write operations, for example, with the address register ADR ( Figure 2 In the block address, one BLKSEL signal line becomes "H" and the other BLKSEL signal lines become "L". For example, a specific drive voltage with a positive value is supplied to one BLKSEL signal line, and a ground voltage V is supplied to the other BLKSEL signal lines. SS Therefore, all word lines WL in a memory block BLK corresponding to the block address are connected to all wiring CGs. Furthermore, all word lines WL in other memory blocks BLK become floating.

[0089] The word line decoder (WLD) has multiple word line decoding units (wld). These multiple word line decoding units (wld) correspond to multiple memory cells (MC) in the memory string (MS). In the example shown, the word line decoding unit (wld) has two transistors (T). WLS T WLU Transistor T WLS T WLU For example, a field-effect NMOS transistor. Transistor T WLS T WLU The drain electrode is connected to wiring CG. Transistor T WLS The source electrode is connected to the wiring CG S Transistor T WLU The source electrode is connected to the wiring CG U Transistor T WLS The gate electrode is connected to the signal line WLSEL. S Transistor T WLU The gate electrode is connected to the signal line WLSEL. U Signal line WLSEL S With one transistor T contained in all word line decoding units wld WLS Multiple corresponding settings are provided. Signal line WLSEL U The other transistor T contained in the all-word-line decoding unit wld WLU Multiple settings can be configured accordingly.

[0090] In read and write operations, for example, with the address register ADR ( Figure 2 The signal line WLSEL corresponding to the word line decoding unit wld of the page address in ) S It becomes the "H" state, and its corresponding WLSELU It becomes the "L" state. Additionally, the signal line WLSEL corresponds to the other word line decoding unit wld. S It becomes the "L" state, and its corresponding WLSEL U It becomes the "H" state. Additionally, the wiring CG... S Supply the voltage corresponding to the selected word line WL. Additionally, configure the wiring CG. U A voltage corresponding to the non-select word line WL is supplied. Therefore, the voltage corresponding to the select word line WL is supplied to one word line WL corresponding to the page address. Furthermore, the voltage corresponding to the non-select word line WL is supplied to the other word lines WL.

[0091] The driver circuit DRV, for example, has 6 transistors T DRV1 ~T DRV6 Transistor T DRV1 ~T DRV6 For example, a field-effect NMOS transistor. Transistor T DRV1 ~T DRV4 The drain electrode is connected to the wiring CG S Transistor T DRV5 T DRV6 The drain electrode is connected to the wiring CG U Transistor T DRV1 The source electrode is supplied via voltage line L VG1 It is connected to the output terminal of the voltage generation unit vg1. Transistor T DRV2 T DRV5 The source electrode is supplied via voltage line L VG2 It is connected to the output terminal of the voltage generation unit vg2. Transistor T DRV3 The source electrode is supplied via voltage line L VG3 It is connected to the output terminal of the voltage generation unit VG3. Transistor T DRV4 T DRV6 The source electrode is supplied via voltage line L P Connected to the pad electrode P. For transistor T. DRV1 ~T DRV6 The gate electrodes are connected to signal lines VSEL1 to VSEL6 respectively.

[0092] In read-out and write-out operations, such as those related to wired CG... S One of the corresponding signal lines VSEL1 to VSEL4 is in the "H" state, and the others are in the "L" state. Furthermore, regarding the wiring CG... U One of the two corresponding signal lines, VSEL5 and VSEL6, becomes the "H" state, and the other becomes the "L" state.

[0093] An address decoder not shown, for example, follows the sequence generator SQC ( Figure 2 The control signals are sequentially referenced to the address register ADR. Figure 2 The row address RA of the block address and page address is specified. The address decoder decodes the signal lines BLKSEL and WLSEL. S WLSEL U The voltage control is in either "H" or "L" state.

[0094] in addition, Figure 4 In the example, in the row decoder RD, block decoding units blkd are set for each memory block BLK. However, this configuration can be modified appropriately. For example, block decoding units blkd can also be set for each of two or more memory blocks BLK.

[0095] [Circuit configuration of the Sensing Amplifier Module (SAM)]

[0096] Sensing Amplifier Module SAM ( Figure 2 For example, Figure 8 As shown, the device includes multiple sense amplifier units (SAUs). Each sense amplifier unit (SAU) corresponds to multiple bit lines (BLs). Each sense amplifier unit (SAU) includes a sense amplifier (SA), wiring (LBUS), and latch circuits (SDL, DL0~DLn). L (n L (Numbers are natural numbers). The pre-charge transistor 55 is connected to the LBUS wiring. Figure 9 The wiring LBUS is connected to the wiring DBUS via a switching transistor DSW.

[0097] Sensing amplifier SA such as Figure 9 As shown, a sensing transistor 41 is included. The sensing transistor 41 discharges the charge on the wiring LBUS based on the current flowing in the bit line BL. The source electrode of the sensing transistor 41 is connected to a voltage V supplied to ground. SS The voltage supply line is connected to the LBUS wiring via a switching transistor 42. The gate electrode is connected to the bit line BL via the sensing node SEN, the discharge transistor 43, the node COM, the clamping transistor 44, and the withstand transistor 45. Additionally, the sensing node SEN is connected to the internal control signal line CLKSA via a capacitor 48.

[0098] Furthermore, the sensing amplifier SA includes a voltage transfer circuit. This voltage transfer circuit, based on data latched in the latch circuit SDL, connects node COM and sensing node SEN to the supplied voltage V. DD The voltage supply line or the voltage V supplied SRCThe voltage supply line is selectively turned on. The voltage transmission circuit includes node N1, charging transistor 46, charging transistor 49, charging transistor 47, and discharging transistor 50. Charging transistor 46 is connected between node N1 and sensing node SEN. Charging transistor 49 is connected between node N1 and node COM. Charging transistor 47 is connected between node N1 and the supplied voltage V. DD The voltage supply line is between the discharge transistor 50 and the supplied voltage V. SRC The voltage supply lines are connected. Additionally, the gate electrodes of charging transistor 47 and discharging transistor 50 are connected together to node INV_S of the latch circuit SDL.

[0099] Additionally, the sensing transistor 41, switching transistor 42, discharging transistor 43, clamping transistor 44, charging transistor 46, charging transistor 49, and discharging transistor 50 are, for example, enhancement-mode NMOS transistors. The breakdown transistor 45 is, for example, a depletion-mode NMOS transistor. The charging transistor 47 is, for example, a PMOS (P-Metal-Oxide-Semiconductor) transistor.

[0100] Furthermore, the gate electrode of the switching transistor 42 is connected to signal line STB. The gate electrode of the discharging transistor 43 is connected to signal line XXL. The gate electrode of the clamping transistor 44 is connected to signal line BLC. The gate electrode of the withstand transistor 45 is connected to signal line BLS. The gate electrode of the charging transistor 46 is connected to signal line HLL. The gate electrode of the charging transistor 49 is connected to signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequence generator SQC.

[0101] The latch circuit SDL includes nodes LAT_S and INV_S, inverter 51, inverter 52, switching transistor 53, and switching transistor 54. Inverter 51 has an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 has an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switching transistor 53 is disposed in the current path between node LAT_S and wiring LBUS. Switching transistor 54 is disposed in the current path between node INV_S and wiring LBUS. Switching transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of switching transistor 53 is connected to the sequence generator SQC via signal line STL. The gate electrode of switching transistor 54 is connected to the sequence generator SQC via signal line STI.

[0102] Latch circuits DL0~DLn LIt is constructed in a manner largely similar to the latch circuit SDL. However, as mentioned above, the node INV_S of the latch circuit SDL is connected to the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. The latch circuits DL0 to DLnL differ from the latch circuit SDL in this respect.

[0103] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequence generator SQC via the signal line DBS.

[0104] In addition, such as Figure 8 As illustrated, the signal lines STB, HLL, XXL, BLX, BLC, and BLS are commonly connected among all the sense amplifier units SAU contained in the sense amplifier module SAM. Furthermore, the voltage V supplied... DD The voltage supply line and the supplied voltage V SRC The voltage supply lines are shared among all the sense amplifier units (SAUs) contained in the sense amplifier module (SAM). Similarly, the signal lines STI and STL of the latch circuit SDL are shared among all the sense amplifier units (SAUs) contained in the sense amplifier module (SAM). Likewise, the latch circuits DL0 to DLn... L The signal lines STI and STL correspond to the signal lines TI0 to TIn. L TL0~TLn L Each of the sense amplifier units (SAUs) contained in the sense amplifier module (SAM) is connected together. On the other hand, multiple signal lines (DBS) are provided corresponding to each of the sense amplifier units (SAUs) contained in the sense amplifier module (SAM).

[0105] [Circuit configuration of the cache memory CM]

[0106] Cache memory CM ( Figure 2 It has multiple latching circuits. These multiple latching circuits are connected to the latching circuits within the sense amplifier module (SAM) via a DBUS wiring system. The data DAT contained in these multiple latching circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuit (I / O).

[0107] In addition, a decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR. The switching circuit, based on the output signal of the decoding circuit, causes the latch circuit corresponding to the column address CA to connect to the bus DB. Figure 2 ) Conduction.

[0108] [Circuit configuration of Sequence Generator (SQC)]

[0109] Sequence generator SQC ( Figure 2 According to the command data D stored in the command register CMR CMD The internal control signals are output to the line decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. In addition, the sequence generator SQC outputs state data D, appropriately representing its own state. ST Output to the status register STR.

[0110] In addition, the sequence generator SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. When the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is essentially disabled. Conversely, when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is enabled.

[0111] [Circuit configuration of input / output control circuit (I / O)]

[0112] The input / output control circuit (I / O) includes data signal input / output terminals DQ0-DQ7, trigger signal input / output terminals DQS and / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. The multiple input circuits, multiple output circuits, shift register, and buffer circuit are respectively connected to the power supply voltage V. CCQ and grounding voltage V SS The terminals.

[0113] Based on the internal control signals from the logic circuit CTR, data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR. Furthermore, based on the internal control signals from the logic circuit CTR, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit.

[0114] The multiple input circuits include, for example, comparators connected to any one of the data signal input / output terminals DQ0 to DQ7, or to both the trigger signal input / output terminals DQS and / DQS. The multiple output circuits include, for example, an OCD (Off-Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7, or to any one of the trigger signal input / output terminals DQS and / DQS.

[0115] [Circuit Structure of the CTR Logic Circuit]

[0116] Logic circuit CTR ( Figure 2The controller receives external control signals from the controller die CR via external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and correspondingly outputs internal control signals to the input / output control circuit I / O.

[0117] [Construction of Memory Die (MD)]

[0118] Figure 10 This is a schematic top view of a memory die (MD). Figure 11 This is a schematic cross-sectional view of a memory die (MD). Additionally, Figure 11 It is a diagram used to illustrate the schematic structure of a memory die (MD), and does not represent the specific number, shape, or configuration of components. Figure 12 yes Figure 10 A schematic enlarged view of the portion indicated by A in the diagram. However, Figure 12 in, omit Figure 10 A portion of the structure (the first hookup region R, described later) constitutes... HU1 ). Figures 13-16 It is an omission Figure 12 A schematic top view of a portion of the structure shown. Figure 17 yes Figure 10 A schematic enlarged view of the part shown as B in the diagram. Figure 18 yes Figure 17 A schematic enlarged view of the part indicated by C. Figure 19 yes Figure 11 A schematic enlarged view of the part indicated by D in the diagram. Figure 20 yes Figure 12 A schematic enlarged view. Figure 21 It is Figure 20 The structure shown is a schematic cross-sectional view taken along line E-E' and viewed in the direction of the arrow.

[0119] in addition, Figures 13-16 It is a diagram. Figure 12 Among the multiple conductive layers 110 described, there are diagrams of conductive layers (conductive layer 200, conductive layer 210, conductive layer 220, or conductive layer 230) located at specific height positions. Furthermore, Figures 13-16 In the text, the composition of the first and fourth memory blocks BLKs counted from the negative side of the Y direction is omitted among the multiple memory blocks BLKs arranged in the Y direction.

[0120] For example, memory die MD Figure 10 As shown, a semiconductor substrate 100 is provided. In the illustrated example, four memory cell array regions R arranged in the X and Y directions are disposed on the semiconductor substrate 100. MCA In addition, the storage cell array region R MCA Features: Two memory hole regions R arranged in the X direction MHTwo first connection regions R arranged in the X direction between these memory hole regions. HU1 ; and the second connection region R located between these first connection regions. HU2 .

[0121] For example, memory die MD Figure 11 As shown, it includes: a semiconductor substrate 100; and a transistor layer L. TR The wiring layer D0 is disposed on the semiconductor substrate 100; the transistor layer L is disposed on the transistor layer L. TR Above; wiring layer D1, positioned above wiring layer D0; wiring layer D2, positioned above wiring layer D1; memory cell array layer L MCA1 It is positioned above the wiring layer D2; the memory cell array layer L MCA2 Set in the storage cell array layer L MCA1 Above; wiring layer M0, located on the memory cell array layer L. MCA2 Above; and a wiring layer not shown, positioned above wiring layer M0.

[0122] [Structure of semiconductor substrate 100]

[0123] The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, there are N-type well regions containing N-type impurities such as phosphorus (P), P-type well regions containing P-type impurities such as boron (B), semiconductor substrate regions without N-type well regions and P-type well regions, and an insulating region 100I.

[0124] [Transistor layer L] TR [Construction]

[0125] For example, Figure 11 As shown, a wiring layer GC is disposed on the upper surface of the semiconductor substrate 100, separated by an insulating layer (not shown). The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc contained in the wiring layer GC are respectively connected to a contact CS.

[0126] The N-type well region, P-type well region, and semiconductor substrate region of semiconductor substrate 100 function as channel regions for multiple transistors Tr constituting peripheral circuit PC, and as an electrode for multiple capacitors, respectively.

[0127] The multiple electrodes gc contained in the wiring layer GC function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrode of multiple capacitors.

[0128] The contact CS extends in the Z direction and its lower end is connected to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact CS and the semiconductor substrate 100. The contact CS may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W).

[0129] [Construction of wiring layers D0, D1, and D2]

[0130] For example, Figure 11 As shown, the wiring layers D0, D1, and D2 contain multiple wirings electrically connected to at least one of the configurations in the memory cell array MCA and the peripheral circuit PC.

[0131] Wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may also include multilayer films of metals such as titanium nitride (TiN) barrier conductive films and tungsten (W).

[0132] [Storage cell array layer L] MCA1 L MCA2 memory hole area R MH [Construction]

[0133] For example, Figure 12 As shown, in the storage cell array layer L MCA1 L MCA2 This configuration includes multiple memory blocks (BLKs) arranged in the Y direction. For example, a memory block (BLK) might be... Figure 17 As shown, it has multiple string cells SU arranged in the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction. For example, between two adjacent string cells SU in the Y direction... Figure 18 As shown, an insulating layer SHE is set between string units such as silicon oxide (SiO2).

[0134] Memory block BLK, for example Figure 11 As shown, it includes: a plurality of conductive layers 110 arranged in the Z direction; and a plurality of semiconductor layers 120 extending in the Z direction. Furthermore, the memory block BLK, for example, as... Figure 19 As shown, it has multiple gate insulating films 130 respectively disposed between multiple conductive layers 110 and multiple semiconductor layers 120.

[0135] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction. Figure 19 ).

[0136] Below the conductive layer 110, for example, Figure 11 As shown, a conductive layer 111 is provided. The conductive layer 111 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer such as silicon oxide (SiO2) is provided between the conductive layer 111 and the conductive layer 110.

[0137] Below the conductive layer 111, a conductive layer 112 is disposed. The conductive layer 112 may also contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, the conductive layer 112 may also contain, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 111.

[0138] Conductive layer 112 serves as the source line SL ( Figure 3 To perform its function. The conductive layer 112 is disposed on the memory cell array layer L. MCA1 Conductive layer 112, for example, for the memory cell array region R MCA ( Figure 10 All memory blocks BLK contained therein are configured together.

[0139] Conductive layer 111 serves as the source-side gate selection line SGSb ( Figure 3 The gate electrodes of the multiple source-side selection transistors (STSb) connected to it function. The conductive layer 111 is disposed on the memory cell array layer L. MCA1 Two memory hole regions R are distributed along the X direction. MH Two first connection regions R are set between these memory hole regions. HU1 and the second connection region R located between these first connection regions. HU2 It extends in the X direction. The conductive layer 111 is electrically independent in each memory block BLK.

[0140] Furthermore, among the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side selected gate line (SGS). Figure 3 The conductive layer 110, along with the gate electrodes of the multiple source-side transistors (STS) connected to it, functions as a conductive layer. The conductive layer 110 is disposed on the memory cell array layer L. MCA1Two memory hole regions R are distributed along the X direction. MH Two first connection regions R are set between these memory hole regions. HU1 and the second connection region R located between these first connection regions. HU2 It extends in the X direction. The plurality of conductive layers 110 are electrically independent in each memory block BLK.

[0141] In addition, multiple conductive layers 110 located above it serve as word lines WL ( Figure 3 A part of ) and multiple storage units MC (connected to it) Figure 3 The gate electrode of the plurality of conductive layers 110 functions as follows: Figure 13 As illustrated, it is set in the memory cell array layer L MCA1 Two memory hole regions R are distributed along the X direction. MH Two first connection regions R are set between these memory hole regions. HU1 ( Figure 13 (Omitted in Chinese.) Reference: Figure 10 ), and the second connection region R disposed between these first connection regions. HU2 Extending in the X direction. The plurality of conductive layers 110 have two memory hole regions R. MH The memory has two parts 201 and a part 202 connecting the two parts 201. The two parts 201 are electrically connected via part 202. Furthermore, the plurality of conductive layers 110 are electrically independent in each memory block BLK. In the following description, this conductive layer 110 may be referred to as conductive layer 200.

[0142] Furthermore, above it, a group of a pair of conductive layers 110 arranged in the X direction is deposited in the Z direction. This group of conductive layers 110 serves as the word line WL (…). Figure 3 A part of ) and multiple storage units MC connected to it Figure 3 The gate electrode of the memory cell array layer L functions as a group. MCA1 The two conductive layers 110 are, for example, as shown in... Figure 14 As illustrated, they are distributed across one or the other memory hole region R. MH One or another first connection region R HU1 ( Figure 14 (Omitted in Chinese.) Reference: Figure 10 ), and the second connecting region R HU2A portion of it extends in the X direction. The two conductive layers 110 are electrically connected via a contact CC and wiring. Furthermore, the plurality of conductive layers 110 are electrically independent in each memory block BLK. Additionally, in the following description, this conductive layer 110 may be referred to as conductive layer 210.

[0143] In addition, multiple conductive layers 110 located above it serve as word lines WL ( Figure 3 A part of ) and multiple storage units MC (connected to it) Figure 3 The gate electrode of the plurality of conductive layers 110 functions as follows: Figure 15 As illustrated, it is set in the memory cell array layer L MCA2 The two memory hole regions R are arranged in the X direction. MH Two first connection regions R are set between these memory hole regions. HU1 ( Figure 15 (Omitted in Chinese.) Reference: Figure 10 ), and the second connection region R disposed between these first connection regions. HU2 Extending in the X direction. The plurality of conductive layers 110 have two memory hole regions R. MH The memory has two parts 221 and a part 222 connecting the two parts 221. The two parts 221 are electrically connected via part 222. Furthermore, the plurality of conductive layers 110 are electrically independent in each memory block BLK. In the following description, this conductive layer 110 may be referred to as conductive layer 220.

[0144] Furthermore, above it, a group of a pair of conductive layers 110 arranged in the X direction is deposited in the Z direction. This group of conductive layers 110 serves as the word line WL (…). Figure 3 A part of ) and multiple storage units MC (connected to it) Figure 3 The gate electrode of the memory cell array layer L functions as a group. MCA2 The two conductive layers 110 are, for example, as shown in... Figure 16 As illustrated, each is distributed across one or another memory hole region R. MH One or another first connection region R HU1 ( Figure 16 (Omitted in Chinese.) Reference: Figure 10 ), and the second connecting region R HU2 A portion of it extends in the X direction. The two conductive layers 110 are electrically connected via a contact CC and wiring. Furthermore, the plurality of conductive layers 110 are electrically independent in each memory block BLK. Additionally, in the following description, this conductive layer 110 may be referred to as conductive layer 230.

[0145] In addition, one or more conductive layers 110 located above it are disposed in the memory cell array layer L. MCA2 As the drain-side selected gate line SGD and the multiple drain-side selected transistors STD connected to it ( Figure 3 The gate electrode of the plurality of conductive layers 110 functions as follows: Figure 17 As illustrated, the width in the Y direction is smaller than that of the other conductive layers 110. Furthermore, between two adjacent conductive layers 110 in the Y direction, for example... Figure 18 As illustrated, an inter-string insulating layer SHE is provided. The plurality of conductive layers 110 are electrically independent in each string unit SU.

[0146] Semiconductor layer 120, for example Figure 18 As shown, the semiconductor layer 120 is arranged in a specific pattern in the X and Y directions. The semiconductor layer 120 serves as a memory string (MS). Figure 3 The multiple memory cells MC and the channel regions of the selection transistors (STD, STS, STSb) contained therein function. The semiconductor layer 120 is, for example, a polycrystalline silicon (Si) semiconductor layer. The semiconductor layer 120 has, for example, a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. Figure 19 ).

[0147] Semiconductor layer 120, for example Figure 11 As shown, it has a storage cell array layer L MCA1 The included semiconductor region 120 L and storage cell array layer L MCA2 The included semiconductor region 120 U The lower end of semiconductor layer 120 is connected to conductive layer 112. The upper end of semiconductor layer 120 is connected to bit line BL via contacts Ch and Vy.

[0148] Semiconductor Area 120 L It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 L The outer periphery is composed of memory cell array layers L MCA1 The semiconductor region 120 is surrounded by a plurality of conductive layers 110 and 111, and faces the plurality of conductive layers 110 and 111. L The lower end (e.g., located in the lower end of the memory cell array layer L) MCA1 The diameter of the plurality of conductive layers 110 and the portion below the conductive layer 111 is smaller than that of the semiconductor region 120. L The upper end (e.g., located in the memory cell array layer L) MCA1 The diameter of the portion above the multiple conductive layers 110 contained therein.

[0149] Semiconductor Area 120U It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U The outer periphery is composed of memory cell array layers L MCA2 The included plurality of conductive layers 110 surround and face the plurality of conductive layers 110. Additionally, the semiconductor region 120 U The lower end (e.g., located in the lower end of the memory cell array layer L) MCA2 The diameter of the portion below the multiple conductive layers 110 is smaller than that of the semiconductor region 120. U The upper end (e.g., located in the memory cell array layer L) MCA2 The diameter of the portion above the plurality of conductive layers 110, and the semiconductor region 120 L The diameter of the upper end.

[0150] Gate insulating film 130 ( Figure 19 The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a channel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The channel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charges such as silicon nitride (Si3N4). The channel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 112.

[0151] in addition, Figure 19 This illustrates an example where the gate insulating film 130 comprises a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also comprise a floating gate, such as polycrystalline silicon containing N-type or P-type impurities.

[0152] [Storage cell array layer L] MCA1 L MCA2 The first connection region R HU1 [Construction]

[0153] like Figure 17 As shown, in the first connection region R HU1 Each of these is configured with a small contact connection area r corresponding to the memory block BLK. CC1 In addition, a contact connection area R is set in the region corresponding to a portion of the memory block BLK. C4T .

[0154] In the small area r of the contact point CC1The X-direction ends of multiple conductive layers 110, which function as drain-side selected gate lines (SGD), are provided. Furthermore, in the contact connection small region r... CC1 The device has multiple contacts CC arranged in a matrix when viewed from the Z direction. The multiple contacts CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contacts CC may also comprise, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0155] Among the contacts CC arranged in the X direction, the region R closest to the memory hole is... MH The contact point is connected to the first conductive layer 110 counting from the top. Additionally, the second contact point is near the memory hole region R. MH The contact point is connected to the second conductive layer 110 counting from the top. Similarly, the a-th (a is a natural number) region near the memory hole R... MH The contacts are connected to the a-th conductive layer 110 from the top. The plurality of contacts CC are connected to the drain electrode of transistor Tr via wiring m0 of wiring layer M0, contact C4, wiring d0, d1, d2 in wiring layers D0, D1, D2 and contact CS.

[0156] Furthermore, in the first connection region R HU1 A support structure HR is provided near the contact CC. The support structure HR extends in the Z direction and is connected to the conductive layer 112 at its lower end. The support structure HR contains, for example, silicon oxide (SiO2).

[0157] In the contact connection area R C4T Between the two inter-block insulating layers ST arranged in the Y direction, two insulating layers ST arranged in the Y direction are set. O Furthermore, in the two insulating layers ST O Between them, small areas for connection are set up. C4T Furthermore, in the inter-block insulation layer ST and the insulation layer ST O Between them, a conductive layer is set to connect small areas r 110 The region extends along the inter-block insulation layer ST in the X direction.

[0158] Insulation layer ST O Extending in the Z direction, at the lower end it connects with conductive layer 112 ( Figure 11 Connection. Insulation layer ST O For example, it contains silicon dioxide (SiO2).

[0159] Contact connection small area r C4T For example, Figure 11 As shown, it has multiple insulating layers 110A arranged in the Z direction and multiple contacts C4 extending in the Z direction.

[0160] The insulating layer 110A is a generally plate-shaped insulating layer extending in the X direction. The insulating layer 110A may also include an insulating layer such as silicon nitride (SiN). An insulating layer such as silicon oxide (SiO2) is disposed between the plurality of insulating layers 110A arranged in the Z direction.

[0161] Multiple contacts C4 are arranged in the X direction. Contacts C4 can also comprise laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). For example... Figure 11 As shown, the outer peripheral surface of contact C4 is surrounded by insulating layer 110A and insulating layer 101, respectively, and is connected to insulating layer 110A and insulating layer 101. Contact C4 extends in the Z direction, and is connected to wiring m0 in wiring layer M0 at its upper end and wiring d2 in wiring layer D2 at its lower end.

[0162] Conductive layer connects small areas r 110 For example, Figure 17 As shown, a narrow portion 110 having a plurality of conductive layers 110 arranged in the Z direction. C4T .

[0163] [Storage cell array layer L] MCA1 L MCA2 The second connection region R HU2 [Construction]

[0164] like Figure 12 As shown, in the second connection region R HU2 Corresponding to multiple memory blocks (BLK), multiple contact connection areas (r) are configured. CC2 , and the connection area R of multiple of the aforementioned contacts C4T .

[0165] In the small area r of the contact point CC2 It is part of multiple conductive layers 110 that function as word lines WL or source-side gate lines SGS. Furthermore, in the contact connection small region r CC2 It sets up multiple junctions CC arranged in the X direction when viewed from the Z direction. For example... Figure 21 As shown, the plurality of contacts CC are respectively connected to the conductive layer 110. Furthermore, as... Figure 20 As shown, the plurality of contacts CC are connected to the drain electrode of transistor Tr via wiring m0 of wiring layer M0, contact C4, wiring d0, d1, d2 in wiring layers D0, D1, D2 and contact CS.

[0166] In addition, such as Figure 13 As shown, a portion 202 of the conductive layer 200 has a small contact connection area r. CC2 Narrow section 110 CC2 Furthermore, in the Y direction, it is related to the narrow portion 110. CC2An opening 102 is provided in the adjacent area. CC2 Narrow section 110 CC2 Connection area R with the contact C4T Narrow section 110 C4T Together, this makes two adjacent portions 201 in the X direction conductive. Furthermore, only one contact CC is connected in the conductive layer 200. At the opening 102... CC2 A contact CC is set to connect to the conductive layer 110 located further below.

[0167] In addition, such as Figure 14 As shown, no [structure] is provided between the two conductive layers 210 arranged in the X direction. Figure 13 The illustrated narrow portion 110 CC2 Furthermore, contacts CC are connected to the two conductive layers 210 respectively. Additionally, an opening 102 is provided between the two conductive layers 210. CC2 At opening 102 CC2 A contact CC is set to connect to the conductive layer 110 located further below.

[0168] In addition, such as Figure 15 As shown, a portion 222 of the conductive layer 220 has a small contact connection area r. CC2 Narrow section 110 CC2 Furthermore, in the Y direction, it is related to the narrow portion 110. CC2 An opening 102 is provided in the adjacent area. CC2 Narrow section 110 CC2 Connection area R with the contact C4T Narrow section 110 C4T Together, this makes two adjacent portions 221 in the X direction conductive. Furthermore, only one contact CC is connected in the conductive layer 220. At the opening 102... CC2 A contact CC is set to connect to the conductive layer 110 located further below.

[0169] In addition, such as Figure 16 As shown, no such feature is provided between the two conductive layers 230 arranged in the X direction. Figure 15 The illustrated narrow portion 110 CC2 Furthermore, contacts CC are connected to the two conductive layers 230 respectively. Additionally, an opening 102 is provided between the two conductive layers 230. CC2 At opening 102 CC2 A contact CC is set to connect to the conductive layer 110 located further below.

[0170] [Construction of wiring layer M0, etc.]

[0171] like Figure 11As shown, the wiring layer M0 contains multiple wirings, for example, electrically connected to the memory cell array layer L. MCA1 L MCA2 The composition and transistor layer L TR At least one of the components in.

[0172] The wiring layer M0 contains multiple wirings m0. The multiple wirings m0 may also contain, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0173] A portion of the multiple wirings m0 is used as bit line BL ( Figure 3 ) to perform its function. Bit line BL, for example, Figure 18 As shown, they extend in the X and Y directions. Furthermore, the plurality of bit lines BL are each connected to one semiconductor layer 120 contained in each string unit SU.

[0174] In addition, a portion of multiple wirings m0 is used as Figures 13-16 The illustrated wiring m0a performs its function. Wiring m0a is the wiring that forms the current path between the contacts CC and C4, extending in the Y direction.

[0175] Furthermore, as described above, a wiring layer is disposed above the wiring layer M0. Each of the wiring layers contains multiple wirings. The multiple wirings may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and tantalum nitride (TaN) and metal films such as copper (Cu).

[0176] A portion of the multiple wirings as Figure 14 and Figure 16 The illustrated wiring m1a performs its function. Wiring m1a is a current path route provided between the contacts CC and C4, extending in the X direction.

[0177] [Threshold voltage of memory cell MC]

[0178] Next, refer to Figure 22A , Figure 22B and Figure 22C The threshold voltage of the memory cell MC is explained.

[0179] Figure 22A This is a schematic histogram used to illustrate the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 22B This is a table illustrating the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data. Figure 22C This is another example of a table showing the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data.

[0180] Figure 22A In the example, the threshold voltage of the memory cell MC is controlled to have 8 states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Furthermore, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA Less than the verification voltage V VFYB Furthermore, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB Less than the verification voltage V VFYC Similarly, the threshold voltage of the memory cell MC controlled in states C to F is greater than the verification voltage V. VFYC ~Verification voltage V VFYF Less than the verification voltage V VFYD ~Verification voltage V VFYG Furthermore, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG Less than the readout path voltage V READ .

[0181] also, Figure 22A In the example, a readout voltage V is set between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. CGAR Furthermore, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBR Similarly, readout voltage V is set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G. CGBR ~Read the voltage V CGGR .

[0182] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erase state. The memory cell MC in the Er state is assigned, for example, the data "111".

[0183] Furthermore, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er. The memory cell MC for state A is assigned, for example, the data "101".

[0184] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. The memory cell MC for state B is assigned, for example, the data "001".

[0185] Similarly, states C through G in the figure correspond to threshold voltages that are higher than the threshold voltages corresponding to states B through F. The storage cells MC for these states are assigned, for example, data “011”, “010”, “110”, “100”, and “000”.

[0186] In addition, such as Figure 22B In the illustrated allocation scenario, the low-order data can be read through a single readout voltage V. CGDR The median data can be determined by three readout voltages V. CGAR V CGCR V CGFR The high-order data can be determined by three readout voltages V. CGBR V CGER V CGGR Discrimination.

[0187] In addition, the number of bits, the number of states, and the data allocation for each state recorded in the storage unit MC can be changed appropriately.

[0188] For example, such as Figure 22C In the illustrated allocation scenario, the low-order data can be read through a single readout voltage V. CGDR The median data can be determined by two readout voltages V. CGBR V CGFR The high-order data can be determined by four readout voltages V. CGAR V CGCR V CGER V CGGR Discrimination.

[0189] [Read the action]

[0190] Next, the read operation of the semiconductor memory device in this embodiment will be described.

[0191] Figure 23 It is a schematic cross-sectional view used to illustrate the reading action. Figure 24 It is a timing diagram used to explain the reading action.

[0192] Additionally, in the following explanation, the word line WL of the action object is referred to as the selection word line WL. S The word lines WL other than these are called non-selective word lines WL. U In addition, the following description explains that the multiple storage units MC contained in the string unit SU of the action object are connected to the select word line WL. S An example of performing a read operation on a storage unit (hereinafter referred to as a "selected storage unit MC"). Furthermore, in the following description, this configuration comprising multiple selected storage units MCs may be referred to as a selected page PG.

[0193] At the time point t101 of reading the action, for example... Figure 24 As shown, for the non-selected word line WL U Supply readout path voltage V READThe non-selected memory cell MC is set to the ON state. Additionally, a read voltage (reference) is supplied to the select word line WLs for reading. Figure 22A The reading voltage V is explained. CGAR ~V CGGR (any one of them) or a voltage greater than it. In addition, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG Voltage V SG The degree to which an electronic channel is formed in the channel region of a selector transistor (STD, STS, STSb) determines the extent to which the selector transistor (STD, STS, STSb) is turned on.

[0194] A waiting time Ta is set between the time points t101 and t102 of the read-out action. The waiting time Ta is used, for example, to select the word line WL. S Charging time.

[0195] At the time point t102 of the readout action, select the word line WL. S The readout voltage supplied for reading (reference) Figure 22A The reading voltage V is explained. CGAR ~V CGGR (any one of them). Thus, for example, Figure 23 As shown, some of the selected storage units MC are in the ON state, while the remaining selected storage units MC are in the OFF state.

[0196] At time t103 of the readout action, for example, charging the bit line BL, etc. For example, making Figure 9 The latching circuit SDL latches "H", setting the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". This supplies voltage V to bit line BL and sensing node SEN. DD They begin to be charged. Furthermore, for example, for the source line SL (… Figure 3 Supply voltage V SRC They begin to charge. Voltage V SRC For example, it has a ground voltage V SS The same magnitude. Voltage V SRC It can also be, for example, slightly greater than the ground voltage V. SS And sufficiently smaller than voltage V DD The voltage.

[0197] Between time points t103 and t104 during the readout operation, a waiting time Tb is set. The waiting time Tb is, for example, the waiting time used to allow the current in the bit line BL to converge.

[0198] At the readout point t104, for example, the voltage of signal line BLC is reduced. At this time, the voltage of signal line BLC is adjusted to the level of clamping transistor 44 connected to signal line BLC. Figure 9 The voltage is maintained at a certain level to maintain the ON state. Simultaneously, the voltage on bit line BL decreases.

[0199] At time points t104 to t105 of the readout action ( Figure 24 Between these two points, a waiting time Tc is set. The waiting time Tc is, for example, the waiting time used to stabilize the current in the bit line BL. Hereinafter, the waiting time Tc will be referred to as the "stabilization waiting time".

[0200] At the time point t105 of the readout action, the sensor amplifier module SAM ( Figure 2 The system detects the on / off state of the memory cell MC and obtains data representing the state of the memory cell MC. Hereinafter, this action will be referred to as a sensing action. In a sensing action, for example, the signal lines STB, XXL, BLC, BLS, HLL, BLX ( Figure 9 The state of the selected memory cell MC is set to "L, H, H, H, L, L". As a result, the charge on the sensing node SEN connected to the selected memory cell MC in the ON state is released via the bit line BL, and the voltage of the sensing node decreases. On the other hand, the charge on the sensing node SEN connected to the selected memory cell MC in the OFF state is maintained, thus maintaining the voltage of the sensing node.

[0201] At time points t105 to t106 of the readout action ( Figure 24 Between these points, a waiting time Td is set. The waiting time Td is, for example, the waiting time used to detect the state of the memory cell MC. Hereinafter, the waiting time Td will be referred to as the "sensing time".

[0202] The sensing action ends at time t106 of the readout action. For example, the signal lines STB, XXL, BLC, BLS, HLL, and BLX ( Figure 9 The state of the sensor is set to "L, L, L, L, L, L". This disconnects the sensing node SEN from the bit line BL. Furthermore, the current supply to the bit line BL is terminated.

[0203] Additionally, although the illustration is omitted, at a specific time point after the readout action t106, the charging transistor 55 ( Figure 9 The wiring LBUS is charged, and then the signal line STB is temporarily set to the "H" state. Here, the sensing transistor 41 becomes either on or off depending on the charge of the sensing node SEN. Therefore, the voltage of the wiring LBUS becomes either "H" or "L" depending on the charge of the sensing node SEN. Afterwards, the voltage is controlled by the latch circuit SDL or latch circuits DL0 to DLn.L Any one of them will latch the data of the wiring LBUS.

[0204] At the time point t107 of the readout action, select the word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0205] in addition, Figure 24 The text explains that during the readout action, the selected word line WL... S Only one readout voltage V is supplied CGDR For example, performing one sensing action in the stated state. This action, for example, occurs in situations such as... Figure 22B Data is allocated in the state shown, and execution is performed when the low-order data is determined.

[0206] For example, in the case of determining the median data, the selected word line WL S Supply readout voltage V CGAR In this state, one sensing action is performed. Additionally, the selection word line WL... S Supply readout voltage V CGCR In this state, one sensing action is performed. Additionally, the selection word line WL... S Supply readout voltage V CGFR In the state described, one sensing action is performed.

[0207] For example, when determining high-order data, select word line WL. S A readout voltage is supplied, and a sensing operation is performed once in the stated state. Additionally, the select word line WL... S Supply readout voltage V CGER In this state, one sensing action is performed. Additionally, the selection word line WL... S Supply readout voltage V CGGR In the state described, one sensing action is performed.

[0208] [Uneven wiring resistance in readout operation]

[0209] For reference Figure 13 and Figure 15 As explained, conductive layers 200 and 220 have two memory hole regions R. MH The two parts 201 and 221, and the parts 202 and 222 connected to the two parts 201 and 221. In addition, the two parts 201 and 221 are electrically connected via the parts 202 and 222.

[0210] In addition, as referenced Figure 14 and Figure 16As explained, two conductive layers 210 arranged in the X direction or two conductive layers 230 arranged in the X direction are separated in the X direction and electrically connected via contact CC and wiring m0a and m1a.

[0211] Here, for ease of manufacturing, the multiple conductive layers 110 contain highly heat-resistant materials such as tungsten (W) or molybdenum (Mo). On the other hand, the wirings m0a and m1a contain highly conductive materials such as copper (Cu). In this configuration, for example, the wiring resistance between the two portions 201 of conductive layer 200 and the wiring resistance between the two portions 221 of conductive layer 220 are greater than the wiring resistance between the two conductive layers 210 arranged in the X direction and the wiring resistance between the two conductive layers 230 arranged in the X direction.

[0212] Here, for example, consider conductive layer 200 or conductive layer 220 as the select word line WL S In the case where the action parameters for the read operation are set, either conductive layer 210 or either conductive layer 230 becomes the select word line WL. S In some cases, the selected storage unit (MC) that should be determined to be in a disconnected state may be determined to be in an on state.

[0213] [Adjustment of motion parameters]

[0214] In the first embodiment, conductive layer 200 or conductive layer 220 is the select word line WL. S In this case, action parameter A is used in the read operation. Furthermore, conductive layer 210 or conductive layer 230 is used to select the word line WL. S In this case, action parameter B is used in the readout action. At least a portion of action parameter B differs from action parameter A.

[0215] Action parameters A and B include, for example, references Figure 24 The waiting times are Ta, Tb, Tc, and Td, as specified in the description.

[0216] The waiting time for action parameter B can also be shorter than the waiting time Ta for action parameter A. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the readout action, the select word line WL can be suppressed. S Overcharging. Additionally, the waiting time Ta for action parameter B can be the same as the waiting time Ta for action parameter A.

[0217] The waiting time Tb for action parameter B can also be longer than the waiting time Tb for action parameter A. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the read operation, the current of the bit line BL can be suppressed to the level that cancels out the current of the select word line WL. SThe extent of the impact of overcharging. Additionally, the waiting time Tb for action parameter B can be the same as the waiting time Tb for action parameter A.

[0218] The waiting time Tc for action parameter B can also be longer than the waiting time Tc for action parameter A. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the readout operation, the cell current can be stabilized to cancel the select word line WL. S The extent of the impact of overcharging. Additionally, the waiting time Tc of action parameter B can be the same as the waiting time Tc of action parameter A.

[0219] The waiting time Td (sensing time) of action parameter B can also be shorter than the waiting time Td (sensing time) of action parameter A. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the readout operation, the amount of charge reduction at the sensing node SEN can be suppressed to offset the select word line WL. S The extent of the impact of overcharging. Additionally, the waiting time Td for action parameter B can be the same as the waiting time Td for action parameter A.

[0220] In addition, action parameters A and B, for example, are included in the selection word line WL supplied between time points t101 and t102. S The voltage. For example, when using operating parameter A, the voltage can also be voltage Va0. Furthermore, when using operating parameter B, the voltage can also be voltage Va1. Voltages Va0 and Va1 have readout voltages ( Figure 24 In the example, the read voltage V CGDR The voltage Va1 can also be less than the voltage Va0. Therefore, conductive layer 210 or conductive layer 230 is used to select the word line WL. S During the readout action, the select word line WL can be suppressed. S Overcharging. Additionally, voltage Va1 can be the same as voltage Va0.

[0221] Furthermore, operating parameters A and B may include, for example, the voltage supplied to the signal line BLC between time points t103 and t104. For example, when using operating parameter A, this voltage may also be voltage Vb0. Furthermore, when using operating parameter B, this voltage may also be voltage Vb1. Voltage Vb1 may also be less than voltage Vb0. Thus, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the read operation, the current of the bit line BL can be suppressed to the level that cancels out the current of the select word line WL. S The extent of the effects of overcharging. Additionally, voltage Vb1 can be the same as voltage Vb0.

[0222] In this embodiment, the following adjustment is made: the conductive layer 210 or the conductive layer 230 is the select word line WL. S The action parameter B of the readout action, and the conductive layer 200 or conductive layer 220 are used as the select word line WL. S The operating parameter A differs depending on the time. Therefore, the readout operation in this case is consistent with the cell characteristics, improving the quality of the semiconductor memory device.

[0223] Furthermore, when the waiting time Ta or the voltage Va0 and Va1 are different in action parameters A and B, it is not necessary for the waiting time Tc of action parameter B to be longer than the waiting time Tc of action parameter A. Therefore, the conductive layer 210 or conductive layer 230 can be reduced to a smaller value for the select word line WL. S The time required for the reading action.

[0224] [Second Implementation]

[0225] Next, refer to Figure 25 The semiconductor memory device of the second embodiment will be described. Figure 25 It is a timing diagram used to illustrate the read operation of the semiconductor memory device.

[0226] In the first embodiment, refer to Figure 24 This example illustrates how the read action is executed. However, this is merely an example, and the execution method for the read action can be adjusted accordingly.

[0227] For example, the semiconductor memory device of the second embodiment is configured in essentially the same way as the semiconductor memory device of the first embodiment. Furthermore, the read operation of the second embodiment is performed in essentially the same way as the read operation of the first embodiment.

[0228] However, in the readout operation of the second embodiment, at time point t101, the selected word line WL is... S Supply readout path voltage V READ .

[0229] Furthermore, in the readout operation of the second embodiment, at time point t102, the selected word line WL is... S Supply readout voltage ( Figure 25 In the example, to read the voltage V CGDR Voltages below 1000 ohms.

[0230] Furthermore, in the readout operation of the second embodiment, a waiting time Te is set between time points t102 and t103. The waiting time Te is used, for example, to pause the selection word line WL. S The waiting time for the charge to discharge.

[0231] Furthermore, in the readout operation of the second embodiment, at time point t103, the selected word line WL is...S Supply readout voltage.

[0232] Furthermore, the action parameters A and B in the second embodiment include, for example, a waiting time Te.

[0233] The waiting time Te of action parameter B can also be shorter than the waiting time Te of action parameter A. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the readout action, the select word line WL can be suppressed. S Excessive discharge. Furthermore, if the parameters other than time Te differ between action parameters A and B, the waiting time Te of action parameter B can be the same as the waiting time Te of action parameter A.

[0234] Furthermore, the operation parameters A and B in the second embodiment include, for example, parameters supplied to the selection word line WL between time points t102 and t103. S The voltage. For example, when using operating parameter A, the voltage can also be voltage Ve0. Furthermore, when using operating parameter B, the voltage can also be voltage Ve1. Voltages Ve0 and Ve1 have readout voltages ( Figure 25 In the example, to read the voltage V CGDR The voltage Ve1 can also be greater than the voltage Ve0. Therefore, conductive layer 210 or conductive layer 230 is used to select the word line WL. S During the readout action, the select word line WL can be suppressed. S Excessive discharge. Additionally, voltage Ve1 can be the same as voltage Ve0.

[0235] [Third Implementation]

[0236] Next, refer to Figures 26-30 The semiconductor memory device of the third embodiment will be described.

[0237] In the first and second embodiments, examples of adjusting motion parameters used for reading out actions have been described. However, this aspect is merely illustrative, and the motion parameters used in which the action is adjusted may be appropriately modified.

[0238] For example, the semiconductor memory device of the third embodiment is basically constructed in the same way as the semiconductor memory device of the first or second embodiment. However, in the semiconductor memory device of the third embodiment, the operating parameters used in the write operation are adjusted. In addition, during the read operation of the semiconductor memory device of the third embodiment, the operating parameters may be adjusted in the same manner as in the first or second embodiment, or the operating parameters may not be adjusted.

[0239] [Write action]

[0240] Next, the write operation of the semiconductor memory device in this embodiment will be described.

[0241] Figure 26 It is a flowchart used to illustrate the write operation. Figure 27 It is a schematic cross-sectional view used to illustrate the programming actions included in the write operation. Figure 28 It is a schematic cross-sectional view used to illustrate the verification actions included in a write operation. Figure 29 and Figure 30 It is a flowchart used to explain the write operation.

[0242] In step S101, for example, Figure 26 As shown, the number of loops n W Set to 1. Number of loops n W This is a variable representing the number of write cycles. Additionally, for example, user data written to the storage unit MC is latched into the sense amplifier unit SAU ( Figure 9 The latch circuits DL0 to DLn L .

[0243] In step S102, a programming action is performed. The programming action involves selecting the word line WL. S The action of supplying a programming voltage to increase the threshold voltage of the memory cell MC. This action, for example, occurs in... Figure 29 The execution will take place from time point t121 to time point t125.

[0244] At programming point t121, for example, the bit line BL of the memory cell connected to multiple select memory cells MC for threshold voltage adjustment. W Supply voltage V SRC Bit lines BL connected to memory cells that do not undergo threshold voltage adjustment among multiple selectable memory cells (MCs) P Supply voltage V DD For example, make it similar to the bit line BL. W The corresponding latch circuit SDL ( Figure 9 Latch "L" to make it parallel to bit line BL P The corresponding latch circuit SDL ( Figure 9 Latch "H". Furthermore, set the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, L, H". Below, some memory cells that undergo threshold voltage adjustment within multiple selectable memory cells (MCs) are referred to as "write memory cells (MCs)," while memory cells that do not undergo threshold voltage adjustment are referred to as "disabled memory cells (MCs)."

[0245] At time t122 ​​of the programming action, select word line WL S and non-selective word line WL USupply write path voltage V PASS In addition, the gate line SGD supply voltage V is selected on the drain side. SGD Write path voltage V PASS For example, having a reference Figure 22A Explanation of readout path voltage V READ The above values. Voltage V SGD With less than reference Figure 23 , Figure 24 The voltage V is explained SG Furthermore, the degree to which the drain-side selector transistor STD is turned on or off is determined by the voltage of the bit line BL.

[0246] At time point t123 of the programming action, select word line WL S Supply programming voltage V PGM Programming voltage V PGM Greater than the write path voltage V PASS .

[0247] Here, for example, Figure 27 As shown, for the connection on bit line BL W The channel supply voltage V of semiconductor layer 120 SRC In this semiconductor layer 120 with select word line WL S A relatively large electric field is generated between them. As a result, electrons in the channels of semiconductor layer 120 pass through channel insulating film 131 ( Figure 19 ), tunneling to the charge storage membrane 132 ( Figure 19 This leads to an increase in the threshold voltage for writing to the memory cell MC.

[0248] In addition, the connection to the bit line BL P The channels of the semiconductor layer 120 become electrically floating, and the potential of the channels is transmitted through the non-select word line WL. U The capacitive coupling rises to the write path voltage V. PASS Left and right. In this semiconductor layer 120, there is a select word line WL. S In this process, only an electric field smaller than any of the aforementioned electric fields is generated. Therefore, electrons in the channels of semiconductor layer 120 do not tunnel to charge storage film 132. Figure 19 Therefore, the threshold voltage of the memory cell MC is prevented from increasing.

[0249] Between time points t123 and t124 during the programming action, a waiting time Tf is set. The waiting time Tf is, for example, the waiting time used to increase the threshold voltage for writing to the memory cell MC.

[0250] At time t124 of the programming action, select word line WL S and non-selective word line WL USupply write path voltage V PASS .

[0251] At time t125 of the programming action, select word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0252] Step S103 ( Figure 26 In the process, the verification action is performed.

[0253] At the verification point t131, for example... Figure 29 As shown, select word line WL S and non-selective word line WL U Supply readout path voltage V READ All memory cells (MC) are turned on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG Set the select transistors (STD, STS, STSb) to the ON state.

[0254] At time t132 of the verification action, select word line WL. S Supply a specific verification voltage (reference) Figure 22A The verification voltage V is explained. VFYA ~V VFYG (any one of them). Thus, for example, Figure 28 As shown, some of the selected storage units MC are in the ON state, while the remaining selected storage units MC are in the OFF state.

[0255] Furthermore, at time point t132, for example, bit line BL is charged. At this time, for example, based on latch circuits DL0 to DLn... L The data within, for connections in a specific state ( Figure 29 In the example, the bit line BL of the memory cell MC corresponding to state A) Figure 29 In the example, a voltage V is supplied to the bit line (BLA). DD Supply voltage V to other bit lines BL SRC .

[0256] During the verification of actions at time points t133 to t134, for example... Figure 29 As shown, the sensing action is performed. At this time, the latch circuits DL0 to DLn can also be activated. L Latching represents the on / off state of the storage unit MC, etc.

[0257] During the verification process from time point t135 to time point t137, the storage units MC in other states are... Figure 29In the example, state B undergoes the same processing as at time points t132 to t134. Additionally, Figure 29 In this context, the bit line BL connected to the memory cell MC corresponding to state B is denoted as bit line BL. B .

[0258] During the verification action from time point t138 to time point t140, the storage unit MC in other states is... Figure 29 In the example, state C undergoes the same processing as time points t132 to t134. Additionally, Figure 29 In this context, the bit line BL connected to the memory cell MC corresponding to state C is denoted as bit line BL. C .

[0259] At time t141, select word line WL S and non-selective word line WL U Supply readout path voltage V READ All memory cells (MC) are turned on. Additionally, a voltage V is supplied to the select gate lines (SGD, SGS, SGSb). SG Set the select transistors (STD, STS, STSb) to the ON state.

[0260] At time t142 of the verification action, select word line WL. S Non-selective word line WL U and select the gate line (SGD, SGS, SGSb) to supply ground voltage V SS .

[0261] The data latched in the latch circuit SDL is then transmitted to a counter circuit (not shown). The counter circuit counts the number of memory cells MC whose threshold voltage reaches the target value, or the number of memory cells MC whose threshold voltage does not reach the target value.

[0262] in addition, Figure 29 In the example, it indicates that the selection word line WL is selected during the verification action. S Supply 3 verification voltages V VFYA V VFYB V VFYC For example. However, the verification action supplies the selection word line WL S The number of verification voltages can be two or fewer, four or more, or, for example, ... Figure 30 As illustrated, based on the number of loops n W And change.

[0263] Step S104 ( Figure 26In step S105, the result of the verification action is determined. For example, referring to the counter circuit, if the number of memory cells MC whose threshold voltage has not reached the target value is a certain number or more, the verification is determined to be FAIL, and the process proceeds to step S107. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is a certain number or less, the verification is determined to be PASS, and the process proceeds to step S107.

[0264] In step S105, the number of iterations n is determined. W Has a specific number N been reached? W If the condition is not met, proceed to step S106. If the condition is met, proceed to step S108.

[0265] In step S106, the number of iterations n w Add 1, proceed to step S102. Furthermore, in step S106, for example, the programming voltage V... PGM Apply a specific voltage dV. Therefore, for example, Figure 30 As shown, the programming voltage V PGM With the number of loops n W The increase of also increases.

[0266] In step S107, in the status register STR( Figure 2 The state data D of the subject whose write operation has been successfully completed is stored in the memory. ST The write operation ends. Additionally, the status data D... ST The action is read based on the status and output to the controller's bare CD. Figure 1 ).

[0267] In step S108, in the status register STR( Figure 2 The state data D of the subject whose write operation did not complete normally is stored in ) ST The write operation ends.

[0268] [Uneven wiring resistance during write operations]

[0269] As described above, the conductive layer 200 has two portions 201 ( Figure 13 The wiring resistance between the two parts of the conductive layer 220 and the two parts 221 ( Figure 15 The wiring resistance between the two conductive layers arranged in the X direction is greater than that of the two conductive layers arranged in the X direction. Figure 14 Wiring resistance between ) and two conductive layers 230 arranged in the X direction. Figure 16 Wiring resistance between )

[0270] Here, for example, consider conductive layer 200 or conductive layer 220 as the select word line WL SIn the case where the write operation parameters are set, either conductive layer 210 or either conductive layer 230 is selected as the word line WL. S In some cases, the threshold voltage of the selected memory cell MC may need to be increased to a level higher than required.

[0271] [Adjustment of motion parameters]

[0272] In the semiconductor memory device of the third embodiment, the conductive layer 200 or the conductive layer 220 is a select word line WL. S In this case, action parameter C is used during the write operation. Additionally, conductive layer 210 or conductive layer 230 is used to select the word line WL. S In the case of [specific action], action parameter D is used in the readout action. At least a portion of action parameter D differs from action parameter C.

[0273] Action parameters C and D contain, for example, references Figure 29 The specified waiting time Tf.

[0274] The waiting time Tf for action parameter D can also be shorter than the waiting time Tf for action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During a write operation, the increase in the threshold voltage of the selected memory cell MC can be suppressed. Furthermore, the latency Tf of operation parameter D can be the same as the latency Tf of operation parameter C.

[0275] In addition, the action parameters C and D include, for example, the programming voltage V. PGM The initial value (number of loops n) W Programming voltage V when it is 1 PGM For example, Figure 30 As shown, when using operating parameter C, the voltage can also be voltage Vf0. Furthermore, when using operating parameter D, the voltage can also be voltage Vf1. Voltage Vf1 can also be less than voltage Vf0. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During a write operation, the increase in the threshold voltage of the selected memory cell MC can be suppressed. Additionally, voltage Vf1 can be the same as voltage Vf0.

[0276] [Fourth Implementation]

[0277] Next, refer to Figure 31 The semiconductor memory device of the fourth embodiment will be described. Figure 31 This is a flowchart used to explain the write operation of the semiconductor memory device.

[0278] In the third embodiment, refer to Figures 26-30This example illustrates how to perform a write operation. However, this is merely an example, and the actual execution method for a write operation can be adjusted accordingly.

[0279] For example, the semiconductor memory device of the fourth embodiment is configured in essentially the same way as the semiconductor memory device of the third embodiment. However, the write operation of the fourth embodiment differs from that of the third embodiment. The write operation of the fourth embodiment is performed in essentially the same way as that of the third embodiment.

[0280] However, in the write operation of the fourth embodiment, at time point t132, the word line WL is selected. S The initial verification voltage used in the supply verification operation ( Figure 31 In the example, to verify the voltage V VFYA (or less than its voltage).

[0281] Furthermore, in the write operation of the fourth embodiment, a waiting time Te' is set between time points t132 and t231. The waiting time Te' is used, for example, to select the word line WL. S The waiting time for the charge to discharge.

[0282] Furthermore, in the write operation of the fourth embodiment, at times t231, t233, and t235, the word line WL is selected. S Supply verification voltage ( Figure 31 In the example, to verify the voltage V VFYA V VFYB V VFYC ).

[0283] Furthermore, in the write operation of the fourth embodiment, a waiting time Tb' is set between time points t132 and t232, t135 and t234, and t138 and t236. The waiting time Tb' is, for example, a waiting time used to allow the current of the bit line BL to converge.

[0284] Furthermore, in the write operation of the fourth embodiment, the voltage of the signal line BLC is reduced at times t232, t234, and t236. At this time, the voltage of the signal line BLC is adjusted to reduce the voltage of the clamping transistor 44 connected to the signal line BLC. Figure 9 The voltage that maintains the on state.

[0285] Furthermore, in the write operation of the fourth embodiment, a waiting time Tc' is set between time points t232 and t133, between time points t234 and t136, and between time points t236 and t139. The waiting time Tc' is, for example, a waiting time used to stabilize the current of the bit line BL. Hereinafter, the waiting time Tc' will be referred to as the "stabilization waiting time".

[0286] Furthermore, in the write operation of the fourth embodiment, a waiting time Td' is set between time points t133 and t134, t136 and t137, and t139 and t140. The waiting time Td' is, for example, a waiting time used to detect the state of the memory cell MC. Hereinafter, the waiting time Td' will be referred to as the "sensing time".

[0287] Furthermore, in the write operation of the fourth embodiment, at times t135 and t138, the word line WL is selected. S The verification voltage used next in the supply verification process ( Figure 31 In the example, to verify the voltage V VFYB V VFYC (or a voltage greater than it.)

[0288] Furthermore, in the write operation of the fourth embodiment, a waiting time Ta' is set between time points t135 and t233, and between time points t138 and t235. The waiting time Ta' is, for example, used to select the word line WL. S Charging time.

[0289] Furthermore, the action parameters C and D in the fourth embodiment include, for example, waiting times Ta', Tb', Tc', Td', and Te'.

[0290] The waiting time Ta' of action parameter D can also be shorter than the waiting time Ta' of action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the select word line WL can be suppressed. S Overcharging. Additionally, the waiting time Ta' of action parameter D can be the same as the waiting time Ta' of action parameter C.

[0291] The waiting time Tb' of action parameter D can also be longer than the waiting time Tb' of action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the current of the bit line BL can be suppressed to the level that cancels out the current of the select word line WL. S The extent of the impact of overcharging. Additionally, the waiting time Tb' of action parameter D can be the same as the waiting time Tb' of action parameter C.

[0292] The waiting time Tc' of action parameter D can also be longer than the waiting time Tc' of action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the cell current can be stabilized to offset the select word line WL. SThe extent of the impact of overcharging. Additionally, the waiting time Tc' of action parameter D can be the same as the waiting time Tc' of action parameter C.

[0293] The waiting time Td' (sensing time) of action parameter D can also be shorter than the waiting time Td' (sensing time) of action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the amount of charge reduction at the sensing node SEN can be suppressed to the point of offsetting the select word line WL. S The extent of the impact of overcharging. Additionally, the waiting time Td' of action parameter D can be the same as the waiting time Td' of action parameter C.

[0294] The waiting time Te' of action parameter D can also be shorter than the waiting time Te' of action parameter C. Therefore, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the select word line WL can be suppressed. S Excessive discharge. Additionally, the waiting time Te' of action parameter D can be the same as the waiting time Te' of action parameter C.

[0295] In addition, the action parameters C and D, for example, are included in the time points t132 to t231 and supplied to the selection word line WL. S The voltage. For example, the voltage when using operating parameter D can be greater than the voltage when using operating parameter C. Therefore, conductive layer 210 or conductive layer 230 is used to select the word line WL. S During the write operation, the select word line WL can be suppressed. S Excessive discharge. Alternatively, the voltage can be the same.

[0296] Furthermore, the operating parameters C and D include, for example, the voltage supplied to the signal line BLC between time points t132 and t232. For example, the voltage when using operating parameter D may be lower than the voltage when using operating parameter C. Thus, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During a write operation, the increased current to the bit line BL can be offset by the current to the select word line WL. S The extent of the effect of over-discharge. Additionally, the voltage can also be the same.

[0297] Furthermore, the operating parameters C and D include, for example, the voltage supplied to the signal line BLC between time points t135 and t234, and between time points t138 and t236. For example, the voltage when using operating parameter D can be greater than the voltage when using operating parameter C. Thus, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the current of the bit line BL can be suppressed to the level that cancels out the current of the select word line WL. SThe extent of the effects of overcharging. Additionally, the voltage can also be the same.

[0298] In addition, action parameters C and D, for example, those contained between time points t135 and t233, and between time points t138 and t235, are supplied to the selection word line WL. S The voltage. For example, the voltage when using operating parameter D can be lower than the voltage when using operating parameter C. Thus, conductive layer 210 or conductive layer 230 serves as the select word line WL. S During the write operation, the select word line WL can be suppressed. S Overcharging. Alternatively, the voltage can also be the same.

[0299] [Fifth Implementation]

[0300] Next, refer to Figure 32 The semiconductor memory device of the fifth embodiment will be described. Figure 32 This is a schematic circuit diagram representing a portion of the semiconductor memory device.

[0301] The semiconductor memory device of the fifth embodiment is basically constructed in the same way as any of the semiconductor memory devices in the first to fourth embodiments. However, in the semiconductor memory device of the fifth embodiment, for example, Figure 32 As shown, in the voltage generation unit vg1 and transistor T DRV1 A variable resistor circuit VR1 is set in the current path between them. Furthermore, a voltage generation unit vg3 and transistor T... DRV3 The current path between them is equipped with a variable resistor circuit VR3.

[0302] Figure 33 This is a schematic circuit diagram showing the configuration of the variable resistor circuit VR1. The variable resistor circuit VR1 has a series connection between the voltage generation unit vg1 and the transistor T. DRV1 N resistor units U VR The plurality of resistor units U VR A transistor S connected in parallel between the input and output terminals VR and resistor element R VR N transistors S VR The gate electrodes are respectively connected to signal lines S1 to S2. N N resistive elements R VR All resistors can also have different resistance values. For example, the resistance value of the variable resistor circuit VR1 can be determined based on the input to signal lines S1 to S2. N N bits of data, while the control is 2. N Although the diagram is omitted, the variable resistor circuit VR3 has the same structure as the variable resistor circuit VR1.

[0303] In the fifth embodiment, the action parameters A and B are included, for example, the time points t101 to t102 of the readout action. Figure 24 The N-bit data is input to the variable resistor circuit VR3 between time points t102 and t103, and between time points t103 and t106. For example, the resistance value of the variable resistor circuit VR3 when using operation parameter B can be greater than the resistance value of the variable resistor circuit VR3 when using operation parameter A. Alternatively, the resistance value of the variable resistor circuit VR3 when using operation parameter B can be the same as the resistance value of the variable resistor circuit VR3 when using operation parameter A.

[0304] Furthermore, the operation parameters C and D in the fifth embodiment include, for example, the timing points t123 to t124 of the write operation. Figure 29 The N-bit data is input to the variable resistor circuit VR1 between () and (). For example, the resistance value of the variable resistor circuit VR1 when using operating parameter D can be greater than the resistance value of the variable resistor circuit VR1 when using operating parameter C. Alternatively, the resistance value of the variable resistor circuit VR1 when using operating parameter D can be the same as the resistance value of the variable resistor circuit VR1 when using operating parameter C.

[0305] Furthermore, the operation parameters C and D in the fifth embodiment include, for example, the timing points t131 to t132 of the write operation. Figure 29 Between ) and time points t132 to t231 ( Figure 31 (between time points t132 and t134) Figure 31 ), between time points t135 and t233 ( Figure 31 (between time points t234 and t137) Figure 31 ), between time points t138 and t235 ( Figure 31 ), between t236 and t140 ( Figure 31 The N-bit data is input to the variable resistor circuit VR3. For example, the resistance value of the variable resistor circuit VR3 when using operating parameter D can be greater than the resistance value of the variable resistor circuit VR3 when using operating parameter C. Alternatively, the resistance value of the variable resistor circuit VR3 when using operating parameter D can be the same as the resistance value of the variable resistor circuit VR3 when using operating parameter C.

[0306] In addition, in the fifth embodiment, any one of the operation parameters exemplified in the first to fourth embodiments may be adjusted, or it may not be adjusted.

[0307] In addition, such as Figure 32 and Figure 33 The circuit configuration shown is merely an example; the actual configuration can be adjusted accordingly. For example, Figure 32In the example, either the variable resistor circuit VR1 or VR3 can be omitted. Furthermore, for example... Figure 32 In the example, transistor T in the driver circuit DRV DRV1 T DRV3 Variable resistor circuits VR1 and VR3 are provided in the current path between the voltage generation units vg1 and vg3 and the conductive layer 110. However, the variable resistor circuit only needs to be provided in the current path between the voltage generation units vg1 and vg3 and the conductive layer 110. For example, the variable resistor circuit can also be provided in the transistor T in the driver circuit DRV. DRV1 T DRV3 With wiring CG S The current path between them.

[0308] [Sixth Implementation]

[0309] Next, refer to Figure 34 and Figure 35 The semiconductor memory device of the sixth embodiment will be described. Figure 34 This is a schematic top view showing a portion of the semiconductor memory device. Figure 35 It is an omission Figure 34 A schematic top view representing a part of the composition.

[0310] In embodiments 1 to 5, the effect of uneven wiring resistance is suppressed by adjusting the operating parameters of at least one of the read and write operations. However, this method is merely an example, and the method for suppressing uneven wiring resistance can be appropriately adjusted.

[0311] For example, the semiconductor memory device of the sixth embodiment is configured in the same way as any of the semiconductor memory devices in the first to fifth embodiments.

[0312] However, for example, as referenced Figure 20 As explained, in the semiconductor memory devices of embodiments 1 to 5, two conductive layers 210 arranged in the X direction are connected to a contact C4 via a low-resistance wiring m1a extending in the X direction, and are connected to a transistor Tr via the contact C4. Similarly, two conductive layers 230 arranged in the X direction are connected to a contact C4 via a low-resistance wiring m1a extending in the X direction, and are connected to a transistor Tr via the contact C4.

[0313] On the other hand, for example, Figure 34As shown, in the semiconductor memory device of the sixth embodiment, two conductive layers 230 arranged in the X direction are each connected to a wiring mA extending in the Y direction via a contact CC, and are connected to different contacts C4 via the wiring. Furthermore, two conductive layers 210 arranged in the X direction are each connected to a wiring mA extending in the Y direction via a contact CC, and are connected to different contacts C4 via the wiring. Additionally, for example... Figure 35 As shown, in the semiconductor memory device of the sixth embodiment, two conductive layers 230 arranged in the X direction are connected to at least one of the wirings d0, d1, and d2 extending in the X direction via two contacts C4. Furthermore, two conductive layers 210 arranged in the X direction are connected to at least one of the wirings d0, d1, and d2 extending in the X direction via two contacts C4.

[0314] Here, for reference Figure 11 As explained, wiring d0, d1, and d2, like conductive layer 110, contain a highly heat-resistant material such as tungsten (W). Therefore, with this configuration, the difference between the wiring resistance between the two portions 201 of conductive layer 200 and the wiring resistance between the two portions 221 of conductive layer 220, and the wiring resistance between the two conductive layers 210 arranged in the X direction and the wiring resistance between the two conductive layers 230 arranged in the X direction can be suppressed.

[0315] In addition, in the sixth embodiment, any of the operating parameters exemplified in the first to fifth embodiments may be adjusted, or they may not be adjusted.

[0316] In addition, such as Figure 34 and Figure 35 The configuration shown is merely an example; the actual configuration can be adjusted accordingly. For example, Figure 35 In the example, the wiring d0, d1, d2 used to electrically connect the two conductive layers 210 arranged in the X direction has a generally straight shape extending in the X direction. Similarly, the wiring d0, d1, d2 used to electrically connect the two conductive layers 230 arranged in the X direction has a generally straight shape extending in the X direction. However, for example, as Figure 36 As shown, such wiring d0, d1, d2 can also have multiple generally straight sections dy extending in the Y direction and arranged in the X direction. Furthermore, for example... Figure 37 As shown, these wirings d0, d1, and d2 can also have multiple generally straight sections dx extending in the X direction and arranged in the Y direction. With this configuration, the wiring resistance between the two conductive layers 210 arranged in the X direction and the wiring resistance between the two conductive layers 230 arranged in the X direction can be further increased.

[0317] [Other Implementation Methods]

[0318] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, the configuration and operation described above are merely illustrative, and the specific configuration and operation can be adjusted appropriately.

[0319] For example, the memory cell array (MCA) of embodiments 1 to 6 is referred to as follows. Figure 11 As explained, it has two memory cell array layers L arranged in the Z direction. MCA1 L MCA2 In addition, the storage cell array layer L MCA1 A portion of the conductive layer 200 among the multiple conductive layers 110 contained therein Figure 13 It comprises two portions 201 arranged in the X direction and a portion 202 connected thereto, and a pair of conductive layers 210 arranged in the X direction are disposed above it. Figure 14 In addition, the storage cell array layer L MCA2 A portion of the conductive layer 220 among the multiple conductive layers 110 contained therein Figure 15 It comprises two portions 221 arranged in the X direction and a portion 222 connected thereto, and a pair of conductive layers 230 arranged in the X direction are disposed above it. Figure 16 ).

[0320] However, this configuration is merely an example, and the specific configuration can be adjusted accordingly.

[0321] For example, in the memory cell array (MCA) of embodiments 1 to 6, the memory cell array layer L may be omitted. MCA2 In this case, the storage cell array layer L MCA1 It may also have multiple conductive layers 110 that function as drain-side selected gate lines (SGD), etc. Figure 17 ).

[0322] Furthermore, in the memory cell array (MCA) of embodiments 1 to 6, for example, the memory cell array layer L may also be included. MCA1 With memory cell array layer L MCA2 In this configuration, one or more memory cell array layers are provided. Each memory cell array layer may also contain multiple conductive layers 110. Furthermore, a portion of the multiple conductive layers 110 may have two parts arranged in the X direction and a portion connected to them. Additionally, a pair of conductive layers 110 arranged in the X direction may be provided above it.

[0323] Furthermore, in the description of the semiconductor memory device in embodiments 1 to 6, a configuration of multiple memory transistors having NAND connections was illustrated as a configuration of the memory cell array (MCA). However, this configuration is merely an example, and the connection method of the memory transistors can be appropriately adjusted. For example, a configuration of multiple memory transistors having NOR connections can also be used as a configuration of the memory cell array (MCA).

[0324] Furthermore, as illustrated in the examples above, a configuration in which the gate insulating film contains an insulating or conductive charge storage portion is presented as a memory transistor. However, this configuration is merely illustrative, and the configuration of the gate insulating film of a memory transistor can be appropriately adjusted. For example, a configuration in which the gate insulating film contains a strong dielectric can also be used as a memory transistor.

[0325] Furthermore, as illustrated in the examples above, a configuration with multiple memory transistors was shown as a configuration of the memory cell array (MCA). However, this configuration is merely illustrative, and the specific configuration can be adjusted accordingly. For example, a configuration other than that with memory transistors could also be used as the configuration of the memory cell array (MCA).

[0326] For example, a memory cell array (MCA) can also be DRAM (Dynamic Random Access Memory). DRAM includes one or more capacitors and one or more transistors. During write and read operations, the capacitors are charged and discharged. Word lines are connected to the gate electrode of the transistors, and bit lines are connected to the source or drain of the transistors. A memory cell array (MCA) can be configured, for example, to have multiple word lines arranged in the Z-direction, or multiple bit lines arranged in the Z-direction.

[0327] Furthermore, a memory cell array (MCA) can also be an SRAM (Static Random Access Memory). An SRAM has two CMOS (Complementary Metal Oxide Semiconductor) inverters. The input terminal of one is connected to the output terminal of the other, and the output terminal of one is connected to the input terminal of the other.

[0328] In addition, the memory cell array (MCA) can also be a magnetoresistive random access memory (MRAM) or a spin transfer torque (STT-MRAM) or other magnetoresistive memories. MRAM and STT-MRAM consist of a pair of strongly magnetic films and a channel insulating film. The pair of strongly magnetic films are arranged opposite each other. The channel insulating film is disposed between the pair of strongly magnetic films. The magnetization direction of the strongly magnetic films changes according to the write operation.

[0329] Furthermore, the memory cell array (MCA) can also be a resistive random access memory (ReRAM) or similar resistive random access memory. ReRAM comprises a pair of electrodes and a metal oxide, etc. The metal oxide, etc., is disposed between the pair of electrodes. Conductive filaments, such as oxygen defects, are formed within the metal oxide, etc., according to a write operation. The pair of electrodes are connected or disconnected via these conductive filaments, etc.

[0330] Furthermore, the memory cell array (MCA) can also be a phase-change memory such as PCRAM (Phase Change Random Access Memory) or PCM (Phase Change Memory). Phase-change memory can also contain sulfide films such as GeSbTe. The crystallization state of the sulfide film can also change according to the write operation.

[0331] also, Figure 36 In the example, the wiring d0, d1, d2 used to electrically connect two conductive layers 210 and two conductive layers 230 arranged in the X direction have multiple generally straight portions dy extending in the Y direction and arranged in the X direction. Furthermore, Figure 37 In the example, the wiring d0, d1, d2 used to electrically connect the two conductive layers 210 and 230 arranged in the X direction have multiple generally straight portions dx extending in the X direction and arranged in the Y direction. However, this configuration is merely an example, and the specific configuration can be adjusted accordingly. For example, Figure 20 In the example, the wiring m0a and m1a used to electrically connect two conductive layers 210 and two conductive layers 230 arranged in the X direction have multiple generally straight portions extending in the Y direction and arranged in the X direction. Similarly, Figure 20 In the example, the wiring m0a and m1a used to electrically connect the two conductive layers 210 and the two conductive layers 230 arranged in the X direction have multiple generally straight portions extending in the X direction and arranged in the Y direction.

[0332] [other]

[0333] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: Substrate: The first conductive layer is spaced apart from the substrate in a first direction intersecting the surface of the substrate, and extends in a second direction intersecting the first direction; A second conductive layer is spaced apart from the substrate and the first conductive layer in the first direction and extends in the second direction; The third conductive layer is spaced apart from the substrate and the first conductive layer in the first direction, extends in the second direction, is arranged with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; A first semiconductor layer extends in the first direction and faces the first conductive layer and the second conductive layer; A first charge storage unit is disposed between the first conductive layer and the first semiconductor layer; A second charge storage section is disposed between the second conductive layer and the first semiconductor layer; A second semiconductor layer extends in the first direction and faces the first conductive layer and the third conductive layer. A third charge storage section is disposed between the first conductive layer and the second semiconductor layer; A fourth charge storage section is disposed between the third conductive layer and the second semiconductor layer; The first bit line is electrically connected to the first semiconductor layer; and The second bit line is electrically connected to the second semiconductor layer; and When performing a specific operation on the first storage cell containing the first charge storage section, the magnitude and supply time of one or more voltages supplied to the first conductive layer, the magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing begins, and the sensing time are set as the first operation parameters. When performing the specific operation on the second storage cell containing the second charge storage section, the magnitude and supply time of one or more voltages supplied to the second conductive layer and the third conductive layer, the magnitude and supply time of one or more voltages supplied to the first bit line, the stabilization waiting time until sensing begins, and the sensing time are set as the second operation parameters. At least a portion of the second action parameter is different from at least a portion of the first action parameter.

2. The semiconductor memory device according to claim 1, wherein When the specific action is performed on the second memory cell, at least one of the magnitudes and supply times of one or more voltages supplied to the second conductive layer and the third conductive layer is less than at least one of the magnitudes and supply times of one or more voltages supplied to the first conductive layer when the specific action is performed on the first memory cell.

3. The semiconductor memory device according to claim 1, wherein... When the specific action is performed on the second memory cell, at least one of the magnitudes and supply times of one or more voltages supplied to the first bit line is greater than at least one of the magnitudes and supply times of one or more voltages supplied to the first bit line when the specific action is performed on the first memory cell.

4. The semiconductor memory device according to claim 1, wherein The stable waiting time until sensing begins when performing the specific action on the second storage unit is greater than the stable waiting time until sensing begins when performing the specific action on the first storage unit.

5. The semiconductor memory device according to claim 1, wherein... The sensing time when performing the specific action on the second storage unit is less than the sensing time when performing the specific action on the first storage unit.

6. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At the first time point, a first voltage is supplied to the first conductive layer. At a second time point later than the first time point, a second voltage lower than the first voltage is supplied to the first conductive layer. In the read operation targeting the second storage unit At the third time point, a third voltage is supplied to the second conductive layer and the third conductive layer. At a fourth time point later than the third time point, a fourth voltage lower than the third voltage is supplied to the second conductive layer and the third conductive layer. The time from the 3rd time point to the 4th time point is shorter than the time from the 1st time point to the 2nd time point.

7. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At the first time point, a first voltage is supplied to the first conductive layer. At a second time point later than the first time point, a second voltage lower than the first voltage is supplied to the first conductive layer. In the read operation targeting the second storage unit At the third time point, a third voltage is supplied to the second conductive layer and the third conductive layer. At a fourth time point later than the third time point, a fourth voltage, which is smaller than or the same as the third voltage, is supplied to the second conductive layer and the third conductive layer. The third voltage is less than the first voltage.

8. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At the first time point, a first voltage is supplied to the first conductive layer. At a second time point later than the first time point, a second voltage lower than the first voltage is supplied to the first conductive layer. At the fifth time point between the first time point and the second time point, a fifth voltage, lower than the second voltage, is supplied to the first conductive layer. In the read operation targeting the second storage unit At the third time point, a third voltage is supplied to the second conductive layer and the third conductive layer. At a fourth time point later than the third time point, a fourth voltage lower than the third voltage is supplied to the second conductive layer and the third conductive layer. At a sixth time point between the third and fourth time points, a sixth voltage, lower than the fourth voltage, is supplied to the second and third conductive layers. The time from the 6th time point to the 4th time point is shorter than the time from the 5th time point to the 2nd time point.

9. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At the first time point, a first voltage is supplied to the first conductive layer. At a second time point later than the first time point, a second voltage lower than the first voltage is supplied to the first conductive layer. At the fifth time point between the first time point and the second time point, a fifth voltage, lower than the second voltage, is supplied to the first conductive layer. In the read operation targeting the second storage unit At the third time point, a third voltage is supplied to the second conductive layer and the third conductive layer. At a fourth time point later than the third time point, a fourth voltage lower than the third voltage is supplied to the second conductive layer and the third conductive layer. At the sixth time point, between the third and fourth time points, a sixth voltage, which is smaller than or equal to the fourth voltage, is supplied to the second and third conductive layers. The sixth voltage is greater than the fifth voltage.

10. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At time 7, a 7th voltage is supplied to the 1st bit line. At the 8th time point, which is later than the 7th time point, an 8th voltage, which is lower than the 7th voltage, is supplied to the 1st bit line. In the read operation targeting the second storage unit At time 9, a 9th voltage is supplied to the 1st bit line. At the 10th time point, which is later than the 9th time point, a 10th voltage, which is lower than the 9th voltage, is supplied to the 1st bit line. The time from the 9th time point to the 10th time point is longer than the time from the 7th time point to the 8th time point.

11. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At time 7, a 7th voltage is supplied to the 1st bit line. At the 8th time point, which is later than the 7th time point, an 8th voltage, which is lower than the 7th voltage, is supplied to the 1st bit line. In the read operation targeting the second storage unit At time 9, a 9th voltage is supplied to the 1st bit line. At the 10th time point, which is later than the 9th time point, a 10th voltage, which is lower than the 9th voltage, is supplied to the 1st bit line. The 9th voltage is greater than the 7th voltage.

12. The semiconductor memory device according to claim 1, comprising: A first transistor has a gate electrode electrically connected to the first bit line; and The second transistor is disposed on the current path between the first transistor and the first bit line; and The specific action is the reading action. In the read operation targeting the first storage unit At time point 7, voltage 11 is supplied to the gate electrode of the second transistor. At time 8, which is later than time 7, a 12th voltage, lower than the 11th voltage, is supplied to the gate electrode of the second transistor. In the read operation targeting the second storage unit At time 9, a 13th voltage is supplied to the gate electrode of the second transistor. At the 10th time point, which is later than the 9th time point, a 14th voltage, which is lower than the 13th voltage, is supplied to the gate electrode of the 2nd transistor. The time from the 9th time point to the 10th time point is longer than the time from the 7th time point to the 8th time point.

13. The semiconductor memory device according to claim 1, comprising: A first transistor has a gate electrode electrically connected to the first bit line; and The second transistor is disposed on the current path between the first transistor and the first bit line; and The specific action is the reading action. In the read operation targeting the first storage unit At time point 7, voltage 11 is supplied to the gate electrode of the second transistor. At time 8, which is later than time 7, a 12th voltage, lower than the 11th voltage, is supplied to the gate electrode of the second transistor. In the read operation targeting the second storage unit At time 9, a 13th voltage is supplied to the gate electrode of the second transistor. At the 10th time point, which is later than the 9th time point, a 14th voltage, which is lower than the 13th voltage, is supplied to the gate electrode of the 2nd transistor. The 13th voltage is greater than the 11th voltage.

14. The semiconductor memory device according to claim 1, wherein The specific action is the reading action. In the read operation targeting the first storage unit At time 8, the 8th voltage is supplied to the 1st bit line. The first sensing action begins at the 11th hour, which is later than the 8th hour. In the read operation targeting the second storage unit At the 10th time point, the 10th voltage is supplied to the 1st bit line. The second sensing action begins at the 12th hour, which is later than the 10th hour. The time from the 10th hour to the 12th hour is shorter than the time from the 8th hour to the 11th hour.

15. The semiconductor memory device according to claim 1, wherein The specific action is a write action. The write operation involves multiple programming actions. In the first programming action of the write operation targeting the first storage unit At time 13, a voltage 15 is supplied to the first conductive layer. At time 14, which is later than time 13, a voltage 16, lower than the voltage 15, is supplied to the first conductive layer. In the first programming action of the write operation targeting the second storage unit At time 15, a voltage of the 17th value is supplied to the second conductive layer and the third conductive layer. At time 16, which is later than time 15, a voltage 18, lower than the voltage 17, is supplied to the second conductive layer and the third conductive layer. The time from the 15th hour to the 16th hour is shorter than the time from the 13th hour to the 14th hour.

16. The semiconductor memory device according to claim 1, wherein The specific action is a write action. The write operation involves multiple programming actions. In the first programming action of the write operation targeting the first storage unit At time 13, a voltage 15 is supplied to the first conductive layer. At time 14, which is later than time 13, a voltage 16, lower than the voltage 15, is supplied to the first conductive layer. In the first programming action of the write operation targeting the second storage unit At time 15, a voltage of the 17th value is supplied to the second conductive layer and the third conductive layer. At time 16, which is later than time 15, a voltage 18, lower than the voltage 17, is supplied to the second conductive layer and the third conductive layer. The 17th voltage is less than the 15th voltage.

17. A semiconductor memory device comprising: Substrate: The first conductive layer is spaced apart from the substrate in a first direction intersecting the surface of the substrate, and extends in a second direction intersecting the first direction; A second conductive layer is spaced apart from the substrate and the first conductive layer in the first direction and extends in the second direction; A third conductive layer is spaced apart from the substrate and the first conductive layer in the first direction, extends in the second direction, is aligned with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; a first semiconductor layer extends in the first direction and faces the first conductive layer and the second conductive layer. The second semiconductor layer extends in the first direction and faces the first conductive layer and the third conductive layer; The first wiring is electrically connected to the first conductive layer, the second conductive layer, and the third conductive layer; The operating voltage output circuit is electrically connected to the first wiring; and A variable resistor circuit is disposed on the current path between the first wiring and the operating voltage output circuit.

18. A semiconductor memory device comprising: Substrate: The first conductive layer is spaced apart from the substrate in a first direction intersecting the surface of the substrate, and extends in a second direction intersecting the first direction; A second conductive layer is spaced apart from the substrate and the first conductive layer in the first direction and extends in the second direction; The third conductive layer is spaced apart from the substrate and the first conductive layer in the first direction, extends in the second direction, is arranged with the second conductive layer in the second direction, and is electrically connected to the second conductive layer; A first semiconductor layer extends in the first direction and faces the first conductive layer and the second conductive layer; The second semiconductor layer extends in the first direction and faces the first conductive layer and the third conductive layer; A fourth conductive layer is disposed between the substrate and the first conductive layer, and is connected to one end of the first semiconductor layer and one end of the second semiconductor layer; The first wiring is disposed between the substrate and the fourth conductive layer, and is electrically connected to the second conductive layer and the third conductive layer; The first contact extends in the first direction, with one end of the first direction being closer to the substrate than the fourth conductive layer, and the other end of the first direction being farther from the substrate than the second conductive layer, and is disposed on the current path of the second conductive layer and the first wiring. and The second contact extends in the first direction, with one end of the first direction closer to the substrate than the fourth conductive layer and the other end of the first direction farther from the substrate than the third conductive layer, and is disposed on the current path of the third conductive layer and the first wiring.

19. The semiconductor memory device of claim 18, wherein The first wiring has multiple first parts. If a specific direction intersecting the first direction and the second direction is designated as the third direction, The plurality of first portions then extend in the second direction and are arranged in the third direction, or extend in the third direction and are arranged in the second direction.

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