Semiconductor devices

Abstract

According to one embodiment, a semiconductor device includes: a polysilicon semiconductor; an intermediate insulating layer disposed on the polysilicon semiconductor; an oxide semiconductor disposed on the intermediate insulating layer; a second insulating layer disposed on the intermediate insulating layer and the oxide semiconductor; a gate electrode disposed on the second insulating layer and located directly above the oxide semiconductor; a first conductive layer that contacts the polysilicon semiconductor via a first contact hole penetrating the intermediate insulating layer and the second insulating layer, and contacts the oxide semiconductor via a second contact hole penetrating the second insulating layer; and a second conductive layer that is stacked with the first conductive layer between the first contact hole and the second contact hole, the first conductive layer having an extension extending from the second contact hole to the gate electrode, the second conductive layer not being stacked on the extension, and the thickness of the first conductive layer being less than the thickness of the second conductive layer.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2021-009377, filed on January 25, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] For example, regarding liquid crystal display devices, the following technology has been proposed: a technology in which transistors having oxide semiconductors are provided in the pixel circuit of the display area, and transistors having silicon semiconductors are provided in the driving circuit of the peripheral area. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device capable of suppressing the performance degradation of transistors.

[0006] One embodiment of a semiconductor device includes:

[0007] An insulating substrate; a first insulating layer disposed above the insulating substrate; a polysilicon semiconductor disposed above the first insulating layer; an intermediate insulating layer disposed above the polysilicon semiconductor; an oxide semiconductor disposed above the intermediate insulating layer; a second insulating layer disposed above the intermediate insulating layer and the oxide semiconductor; a gate electrode disposed above the second insulating layer and located directly above the oxide semiconductor; a first conductive layer contacting the polysilicon semiconductor via a first contact hole penetrating the intermediate insulating layer and the second insulating layer, and contacting the oxide semiconductor via a second contact hole penetrating the second insulating layer; and a second conductive layer stacked with the first conductive layer between the first contact hole and the second contact hole, the first conductive layer having an extension extending from the second contact hole to the gate electrode, the second conductive layer not stacked on the extension, and the thickness of the first conductive layer being smaller than the thickness of the second conductive layer.

[0008] According to one embodiment, a semiconductor device capable of suppressing transistor performance degradation can be provided. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing a structural example of the semiconductor device 1 according to an embodiment.

[0010] Figure 2 This is a diagram illustrating the manufacturing method of transistors TR1 and TR2.

[0011] Figure 3 This is a diagram illustrating the manufacturing method of transistors TR1 and TR2.

[0012] Figure 4 This is a diagram illustrating the manufacturing method of transistors TR1 and TR2.

[0013] Figure 5 This is a diagram illustrating the manufacturing method of transistors TR1 and TR2.

[0014] Figure 6 This is a cross-sectional view of semiconductor SC2 after impurity implantation.

[0015] Figure 7 This is a graph representing the results of the first simulation.

[0016] Figure 8 This is a graph representing the results of the second simulation.

[0017] Figure 9 This is a cross-sectional view showing another structural example of the semiconductor device 1 in this embodiment.

[0018] Figure 10 This is a cross-sectional view showing another structural example of the semiconductor device 1 in this embodiment. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0020] Furthermore, the disclosure is merely one example, and appropriate modifications that maintain the spirit of the invention can be readily conceived by those skilled in the art, and are of course included within the scope of this invention. Additionally, to make the description clearer, the drawings sometimes schematically represent the width, thickness, shape, etc., of various parts compared to the actual embodiment, but this is merely an example and does not limit the interpretation of the invention. Furthermore, in this specification and the various drawings, the same reference numerals are used to denote constituent elements that perform the same or similar functions as those described above in the previously presented figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0021] The semiconductor device 1 of this embodiment can be applied to various display devices such as liquid crystal display devices, organic electroluminescent display devices, electrophoretic display devices, and LED display devices, as well as various sensors such as electrostatic capacitive sensors and optical sensors, and other electronic devices.

[0022] Figure 1 This is a cross-sectional view showing a structural example of the semiconductor device 1 according to this embodiment.

[0023] Semiconductor device 1 includes a substrate 10, insulating layers 11 to 15, transistors TR1 and TR2, and a connection electrode CN. For example, insulating layer 11 corresponds to a first insulating layer, insulating layers 12 to 14 correspond to intermediate insulating layers, insulating layer 15 corresponds to a second insulating layer, and insulating layer 14 corresponds to a third insulating layer.

[0024] Transistor TR1 has a semiconductor (first semiconductor) SC1 and a gate electrode GE1. Semiconductor SC1 is, for example, a polycrystalline silicon semiconductor, but it can also be other silicon-based semiconductors. Gate electrode GE1 is an electrode electrically connected to the gate line.

[0025] Transistor TR2 comprises a semiconductor SC2 (second semiconductor) and a gate electrode GE2. Semiconductor SC2 is, for example, an oxide semiconductor. Gate electrode GE2 is an electrode electrically connected to the gate line.

[0026] The connecting electrode CN is the electrode that directly electrically connects transistors TR1 and TR2. Connecting electrode CN functions as either the source or drain electrode of transistor TR1. Similarly, connecting electrode CN also functions as either the source or drain electrode of transistor TR2. In transistor TR1, the electrode (the other of the source and drain electrodes) connected to connecting electrode CN across the gate electrode GE1 is omitted from the diagram. Similarly, in transistor TR2, the electrode (the other of the source and drain electrodes) connected to connecting electrode CN across the gate electrode GE2 is omitted from the diagram.

[0027] The substrate 10 is an insulating substrate, formed of insulating materials such as glass or resin film. The insulating layer 11 is disposed on top of the substrate 10.

[0028] Semiconductor SC1 is disposed on insulating layer 11. Insulating layer 12 is disposed on insulating layer 11 and covers semiconductor SC1.

[0029] The gate electrode GE1 is located directly above the semiconductor SC1, disposed on the insulating layer 12, and covered by the insulating layer 13. The light-shielding layer LS is disposed correspondingly to the transistor TR2, on the insulating layer 12, and covered by the insulating layer 13. That is, the gate electrode GE1 and the light-shielding layer LS are located on the same layer, which is a metal layer formed of the same material. The insulating layer 14 is disposed on the insulating layer 13.

[0030] Semiconductor SC2 is located directly above the light-shielding layer LS and is disposed on the insulating layer 14. The insulating layer 15 is disposed on the insulating layer 14 and covers the semiconductor SC2. That is, in Figure 1In the example shown, insulating layers 12 to 14, serving as intermediate insulating layers, are sandwiched between semiconductor SC1 and semiconductor SC2. The intermediate insulating layer is disposed on semiconductor SC1, and semiconductor SC2 is disposed on the intermediate insulating layer.

[0031] The gate electrode GE2 is located directly above the semiconductor SC2 and is disposed on the insulating layer 15. The gate electrode GE2 is at the same potential as, for example, the light-shielding layer LS. The connection electrode CN is disposed on the insulating layer 15. That is, the gate electrode GE2 and the connection electrode CN are located in the same layer, which is a metal layer formed of the same material.

[0032] The connecting electrode CN is electrically connected to the semiconductor SC1 in the first contact hole CH1 that penetrates the insulating layers 12 to 15. Additionally, the connecting electrode CN is electrically connected to the semiconductor SC2 in the second contact hole CH2 that penetrates the insulating layer 15.

[0033] The connection electrode CN is configured as a stack of a first conductive layer L1 and a second conductive layer L2. The second conductive layer L2 is stacked on top of the first conductive layer L1. The first conductive layer L1 is in contact with the semiconductor SC1 via a first contact hole CH1 and with the semiconductor SC2 via a second contact hole CH2. In addition, the first conductive layer L1 has an extension EX extending from the position in the second contact hole CH2 where it contacts the semiconductor SC2 toward the gate electrode GE2.

[0034] The second conductive layer L2 is stacked between the first contact hole CH1 and the second contact hole CH2, and is formed by the first conductive layer L1. Additionally, in Figure 1 In the example shown, the second conductive layer L2 extends further into the transistor TR1 and is stacked on top of the first conductive layer L1 in the first contact hole CH1. However, the second conductive layer L2 does not contact the semiconductor SC1 in the first contact hole CH1. The end face S1 of the second conductive layer L2 on the transistor TR1 side is located closer to the gate electrode GE1 side than the position where it overlaps with the first contact hole CH1.

[0035] On the other hand, the second conductive layer L2 does not extend into the transistor TR2 and is not stacked with the first conductive layer L1 in the second contact hole CH2. That is, the end face S2 of the second conductive layer L2 on the transistor TR2 side does not overlap with the second contact hole CH2. Furthermore, the second conductive layer L2 is not stacked on the extension EX.

[0036] The gate electrode GE2 is configured as a stacked structure similar to that of the connection electrode CN. That is, the gate electrode GE2 has a first layer L11 formed of the same material as the first conductive layer L1 and a second layer L12 formed of the same material as the second conductive layer L2, with the second layer L12 stacked on top of the first layer L11.

[0037] Immediately above the insulating layer 15, the film thickness T1 of the first conductive layer L1 is smaller than the film thickness T2 of the second conductive layer L2 (T1 < T2). The film thickness T2 of the second conductive layer L2 is 3 times or more the film thickness T1 of the first conductive layer L1. In one example, the film thickness T1 is about 30 nm and the film thickness T2 is about 100 nm.

[0038] The first conductive layer L1 is formed of a material different from that of the second conductive layer L2. When selecting the materials for the first conductive layer L1 and the second conductive layer L2 respectively, the density of the material forming the first conductive layer L1 is preferably smaller than the density of the material forming the second conductive layer L2. In one example, the material forming the first conductive layer L1 contains at least one of titanium (Ti) and aluminum (Al), and the material forming the second conductive layer L2 contains at least one of molybdenum (Mo) and tungsten (W).

[0039] However, since the first conductive layer L1 contacts the semiconductor SC2 which is an oxide semiconductor, it is preferably formed of a material that is difficult to oxidize. For example, the first conductive layer L1 is preferably a single-layer body of a titanium-based material, or a laminate in which an aluminum-based layer is laminated on a titanium-based layer, etc.

[0040] The insulating layers 11 to 15 are transparent inorganic insulating layers formed of, for example, silicon nitride (SiN), silicon oxide (SiO), etc. Each of the insulating layers 11 to 15 may be a single-layer body formed of a single insulating material, or a laminate formed of multiple insulating materials.

[0041] In one example, the insulating layer 11 is a laminate of silicon nitride and silicon oxide, the insulating layer 12 is formed of silicon oxide, the insulating layer 13 is formed of silicon nitride, and the insulating layers 14 and 15 are formed of silicon oxide.

[0042] Next, Figure 1 An example of a method for manufacturing the transistors TR1 and TR2 shown is described.

[0043] Figures 2 to 5 is a diagram for explaining the method for manufacturing the transistors TR1 and TR2. In addition, in the Figures 2 to 5 cross-sectional view, the illustration of the base material 10 is omitted.

[0044] First, as Figure 2 shown, the insulating layer 11, the semiconductor (polycrystalline silicon semiconductor) SC1, the insulating layer 12, the gate electrode GE1 and the light-shielding layer LS, the insulating layers 13 and 14, the semiconductor (oxide semiconductor) SC2, and the insulating layer 15 are formed in sequence.

[0045] Furthermore, before forming semiconductor SC2, impurities are implanted into semiconductor SC1 using the gate electrode GE1 as a mask. The implanted impurities are, for example, phosphorus (P) in the n-channel type and boron (B) in the p-channel type.

[0046] After the insulating layer 15 is formed, a first contact hole CH1 is formed that extends through the insulating layers 12 to 15 to the semiconductor SC1, and a second contact hole CH2 is formed that extends through the insulating layer 15 to the semiconductor SC2. A portion of the semiconductor SC1 is exposed in the first contact hole CH1, and a portion of the semiconductor SC2 is exposed in the second contact hole CH2.

[0047] Next, as Figure 3 As shown, after forming a metal film on the insulating layer 15, the metal film is patterned to form a first conductive layer L1 connecting the electrode CN and a first layer L11 of the gate electrode GE2. The first conductive layer L1 contacts the semiconductor SC1 in the first contact hole CH1 and contacts the semiconductor SC2 in the second contact hole CH2, and also has an extension EX. The first layer L11 is located directly above the semiconductor SC2 and is separated from the first conductive layer L1. The region of the semiconductor SC2 that contacts the first conductive layer L1 has low resistance because oxygen is absorbed by the first conductive layer L1.

[0048] Next, as Figure 4 As shown, after forming the metal film, the metal film is patterned to form a second conductive layer L2 connecting the electrode CN and a second layer L12 for the gate electrode GE2. The second conductive layer L2 overlaps with the first conductive layer L1 in the first contact hole CH1, and also overlaps with the first conductive layer L1 between the first contact hole CH1 and the second contact hole CH2. The second layer L12 overlaps with the first layer L11 and is separate from the second conductive layer L2.

[0049] Next, as Figure 5 As shown, ion implantation is performed on semiconductor SC2 using the gate electrode GE2 as a mask. For example, boron (B) is implanted into semiconductor SC2 as an impurity via ion implantation. Alternatively, other impurities such as phosphorus (P) can be implanted into semiconductor SC2 instead of boron.

[0050] During such ion implantation, the high-density and relatively thick second conductive layers L2 and L12 have a strong ability to prevent impurity implantation. Therefore, the region directly below the gate electrode GE2, which is the stack of the first layer L11 and the second layer L12, is almost free of impurities.

[0051] On the other hand, impurities are implanted in the region directly beneath the thin first conductive layer L1 and in the region where the insulating layer 15 is exposed. In particular, the first conductive layer L1 is formed of a low-density material, making it easy for impurities to pass through. Therefore, in regions such as the region directly beneath the extension EX, where only the first conductive layer L1 covers the insulating layer 15, impurities are easily implanted. Thus, impurities are implanted in the region directly beneath the extension EX in the semiconductor SC2 and in the region between the first conductive layer L1 and the gate electrode GE2, resulting in low resistance in these regions.

[0052] However, as mentioned above, when transistor TR1 is an n-channel type, the impurity implanted into semiconductor SC1 is phosphorus. In this case, if boron is to be implanted into semiconductor SC2 as an impurity, the impurities contained in semiconductor SC1 and semiconductor SC2 are of different types. Therefore, when implanting the impurity into semiconductor SC2, protection is needed to prevent the impurity (boron) from being implanted into semiconductor SC1. Therefore, in the first contact hole CH1, a second conductive layer L2 is stacked on top of the first conductive layer L1.

[0053] In addition, when the semiconductor SC1 of the p-channel transistor TR1 contains boron as an impurity and phosphorus is to be implanted into the semiconductor SC2 as an impurity, a second conductive layer L2 is stacked on the first contact hole CH1 above the first conductive layer L1 in order to suppress the implantation of unwanted impurities into the semiconductor SC2.

[0054] However, if the impurities contained in semiconductor SC1 and semiconductor SC2 are the same, the second conductive layer L2 of the first contact hole CH1 can be omitted. For example, if the impurity contained in semiconductor SC1 is phosphorus and phosphorus is to be implanted into semiconductor SC2 as an impurity, or if the impurity contained in semiconductor SC1 is boron and boron is to be implanted into semiconductor SC2 as an impurity, the second conductive layer L2 of the first contact hole CH1 can be omitted.

[0055] Figure 6 This is a cross-sectional view of semiconductor SC2 after impurity implantation.

[0056] Semiconductor SC2 has regions A1 to A5. The following describes each region in detail.

[0057] Region A1 (first region) is located directly below the gate electrode GE2. Region A2 (second region) is located directly below the extension EX. Region A3 (third region) is located between region A1 and region A2, and is connected to both regions A1 and A2. Region A4 is located on the opposite side of region A3, separated by region A1. That is, region A1 is located between region A3 and region A4, and is connected to both regions A3 and A4. Regions A3 and A4 overlap the regions in the insulating layer 15 exposed from the first conductive layer L1 and the first layer L11. Region A5 is the region in the second contact hole CH2 that contacts the first conductive layer L1.

[0058] The impurity concentration in regions A2 to A5 is higher than that in region A1. Furthermore, the impurity concentrations in regions A2 to A5 are approximately equal. For example, boron (B) is implanted as an impurity in each of regions A2 to A5, but almost no boron is implanted in region A1. That is, region A1 corresponds to the channel region of semiconductor SC2. The impurity concentration in this specification can be expressed as the number of impurities per unit volume. Additionally, for oxide semiconductors, a high impurity concentration means a higher number of oxygen vacancies per unit volume, or a higher number of defects per unit volume.

[0059] Alternatively, in another perspective, in semiconductor SC2, regions A2 to A5 have lower resistance compared to region A1. The resistance values ​​of each region from A2 to A4 are approximately equal. Region A5 is in contact with the first conductive layer L1, and its resistance is even lower than that of region A2.

[0060] Next, calculations are performed through simulation. Figure 6 The cross-sectional view shown depicts the impurity concentrations in portions P1 and P2 enclosed by dashed lines. In this simulation, the boron concentration is calculated as the impurity concentration.

[0061] Part P1 is the region A2 of the first conductive layer L1 extension EX, the insulating layer 15, the semiconductor SC2, and the insulating layer 14 stacked together.

[0062] Part P2 is the region where the first conductive layer L1 is absent, and is the region A3 where the insulating layer 15, the semiconductor SC2, and the insulating layer 14 are stacked.

[0063] Figure 7 This is a graph representing the results of the first simulation. Here, the acceleration energy during ion implantation is set to 30 keV, and the ion dose is set to 1*10⁻⁶. 15 ions / cm 2 .

[0064] The horizontal axis of the graph represents the distance (nm) in the depth direction relative to the interface between the insulating layer 15 and the semiconductor SC2. Regarding the position in the depth direction, the left side of the graph corresponds to the upper direction of portions P1 and P2, and the right side corresponds to the lower direction of portions P1 and P2. In the upper part of the graph, the extent of the extension EX is denoted as "EX", the extent of the insulating layer 15 as "15", the extent of the semiconductor SC2 as "SC2", and the extent of the insulating layer 14 as "14".

[0065] The thickness of the extension EX is approximately 30 nm, the thickness of the insulating layer 15 is approximately 100 nm, and the thickness of the semiconductor SC2 is approximately 50 nm.

[0066] The vertical axis of the graph represents the concentration of boron as an impurity (atoms / cm³). 3 ).

[0067] The figure also shows part of the simulation results B1 for P1 and part of the simulation results B2 for P2.

[0068] according to Figure 7 The first simulation results shown confirm that although the impurity concentration of semiconductor SC2 (region A2) in part P1 is lower than that of semiconductor SC2 (region A3) in part P2, a concentration of impurities sufficient to reduce the resistance of region A2 can be injected into region A2 located directly below the extension EX.

[0069] Figure 8 This is a graph representing the results of the second simulation. Here, the acceleration energy during ion implantation is set to 50 keV, and the ion dose is set to 1*10. 15 ions / cm 2 The figure also shows part of the simulation results B1 for P1 and part of the simulation results B2 for P2.

[0070] according to Figure 8 The second simulation results show that the impurity concentration of semiconductor SC2 (region A2) in part P1 is higher than that in part P2 (region A3). This second simulation also confirms that a sufficient concentration of impurities for low resistance can be implanted into region A2. Furthermore, it was confirmed that the impurity concentration balance in each region of semiconductor SC2 can be adjusted by regulating the acceleration energy.

[0071] As described above, the connection electrode CN, which directly connects the polysilicon semiconductor SC1 and the oxide semiconductor SC2, is configured as a stack of a thinner first conductive layer L1 and a thicker second conductive layer L2. However, the second conductive layer L2 is not disposed in the region closer to the gate electrode GE2 than the second contact hole CH2 where the first conductive layer L1 contacts the semiconductor SC2.

[0072] When a thicker connection electrode CN is formed, the extension EX, which is closer to the gate electrode GE2 than the second contact hole CH2, becomes an awning. During ion implantation of the semiconductor SC2, this awning may hinder the implantation of impurities into region A2 directly below the extension EX. In this case, region A2 is not sufficiently reduced in resistance, and the desired performance of transistor TR2 cannot be obtained.

[0073] According to the above-described embodiment, when ion implantation is performed on the semiconductor SC2, implanting impurities into regions A2 and A3 between the contact site between the first conductive layer L1 and the semiconductor SC2 and the channel region A1 can reduce the resistance of these regions A2 and A3. Therefore, a transistor TR2 with the desired performance is provided.

[0074] Furthermore, a second conductive layer L2 is provided on the first contact hole CH1, which contacts the first conductive layer L1 and the semiconductor SC1. Therefore, even if the impurities implanted into the semiconductor SC1 are different from those implanted into the semiconductor SC2, the implantation of different types of impurities into the semiconductor SC1 can be suppressed. This suppresses the increase in contact resistance between the semiconductor SC1 and the connecting electrode CN. Therefore, it suppresses the decrease in the driving capability of the transistor TR1. In addition, no additional process is needed to suppress the implantation of unwanted impurities into the semiconductor SC1, thus suppressing the increase in manufacturing costs.

[0075] Figure 9 This is a cross-sectional view showing another structural example of the semiconductor device 1 in this embodiment.

[0076] Figure 9 The structural example shown is similar to Figure 1 Compared to the structural example shown, the second conductive layer L2 is different. Furthermore, the first conductive layer L1 is different from... Figure 1 Similarly, in the illustrated structural example, the semiconductor SC1 is contacted via the first contact hole CH1, and the semiconductor SC2 is contacted via the second contact hole CH2. Furthermore, the first conductive layer L1 has an extension EX extending from the position in the second contact hole CH2 where it contacts the semiconductor SC2 towards the gate electrode GE2.

[0077] The second conductive layer L2 is stacked with the first conductive layer L1 between the first contact hole CH1 and the second contact hole CH2, stacked with the first conductive layer L1 in the first contact hole CH1, and further stacked with the first conductive layer L1 in the second contact hole CH2. However, the second conductive layer L2 is not stacked on the extension EX. That is, the end face S2 of the second conductive layer L2 on the transistor TR2 side overlaps with the second contact hole CH2.

[0078] In this structural example, impurity implantation into region A5 of semiconductor SC2, which overlaps with the second contact hole CH2, is suppressed. However, since region A5 is in contact with the connecting electrode CN, the oxygen in region A5 is absorbed by the connecting electrode CN, thus region A5 is sufficiently low in resistance.

[0079] Furthermore, in this structural example, since the second conductive layer L2 is not stacked on the extension EX, the same effect as the above structural example can be obtained.

[0080] Figure 10 This is a cross-sectional view showing another structural example of the semiconductor device 1 in this embodiment.

[0081] Figure 10 The structural example shown is similar to Figure 1 Compared to the structural example shown, the second conductive layer L2 is different. That is, the second conductive layer L2 is stacked on the first conductive layer L1 between the first contact hole CH1 and the second contact hole CH2.

[0082] On the other hand, the second conductive layer L2 does not extend into the transistor TR1, nor does it overlap with the first conductive layer L1 in the first contact hole CH1. That is, the end face S1 of the second conductive layer L2 on the transistor TR1 side does not overlap with the first contact hole CH1. In addition, the second conductive layer L2 does not overlap with the first conductive layer L1 in the second contact hole CH2, nor does it overlap with the extension EX.

[0083] In this structural example, the impurities contained in semiconductor SC1 are the same as those contained in semiconductor SC2. Therefore, when impurities are implanted into semiconductor SC2, even if the same type of impurities are implanted into semiconductor SC1, the performance of transistor TR1 will not be degraded.

[0084] Furthermore, in this structural example, since the second conductive layer L2 is not stacked on the extension EX, the same effect as the above structural example can be obtained.

[0085] According to this embodiment, a semiconductor device capable of suppressing transistor performance degradation can be provided.

[0086] Based on the semiconductor device described above as an embodiment of the present invention, all semiconductor devices that can be implemented by those skilled in the art with appropriate design modifications, as long as they contain the spirit of the present invention, are also within the scope of the present invention.

[0087] Within the scope of the present invention, various modifications can be conceived by those skilled in the art, and these modifications also fall within the scope of the present invention. For example, embodiments obtained by adding, deleting, or changing the design of constituent elements appropriately, or by adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention as long as they possess the spirit of the present invention.

[0088] Furthermore, any other effects resulting from the methods described in the above embodiments, as clearly stated in this specification or as readily conceived by those skilled in the art, shall be interpreted as arising from this invention.

Claims

1. A semiconductor device comprising: Insulating substrate; A first insulating layer is disposed above the insulating substrate; A polycrystalline silicon semiconductor is disposed on the first insulating layer; An intermediate insulating layer is disposed on the polycrystalline silicon semiconductor; An oxide semiconductor is disposed on the intermediate insulating layer; A second insulating layer is disposed on the intermediate insulating layer and on the oxide semiconductor; The gate electrode is disposed on the second insulating layer and located directly above the oxide semiconductor; The first conductive layer contacts the polysilicon semiconductor through a first contact hole penetrating the intermediate insulating layer and the second insulating layer, and contacts the oxide semiconductor through a second contact hole penetrating the second insulating layer; as well as A second conductive layer is layered between the first contact hole and the second contact hole, stacked with the first conductive layer. The first conductive layer has an extension extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extension. The thickness of the first conductive layer directly above the second insulating layer is less than the thickness of the second conductive layer above the second insulating layer.

2. The semiconductor device according to claim 1, wherein, The thickness of the second conductive layer directly above the second insulating layer is more than three times the thickness of the first conductive layer above the second insulating layer.

3. The semiconductor device according to claim 1, wherein, The first conductive layer is formed of a different material than the second conductive layer. The density of the first conductive layer is less than the density of the second conductive layer.

4. The semiconductor device according to claim 1, wherein, The first conductive layer comprises at least one of titanium (Ti) and aluminum (Al). The second conductive layer contains at least one of molybdenum (Mo) and tungsten (W).

5. The semiconductor device according to claim 1, wherein, The gate electrode is a stack having a first layer and a second layer, wherein the first layer is formed of the same material as the first conductive layer, and the second layer is formed of the same material as the second conductive layer.

6. The semiconductor device according to claim 1, wherein, The oxide semiconductor has a first region located directly below the gate electrode, a second region located directly below the extension, and a third region located between the first region and the second region. The impurity concentrations in the second region and the third region are higher than those in the first region.

7. The semiconductor device according to claim 1, wherein, The second conductive layer is stacked with the first conductive layer in the second contact hole.

8. The semiconductor device according to claim 1, wherein, The second conductive layer is stacked with the first conductive layer in the first contact hole.

9. The semiconductor device according to claim 8, wherein, The impurity ions contained in the polycrystalline silicon semiconductor are different from those contained in the oxide semiconductor.

10. The semiconductor device according to claim 1, wherein, The second conductive layer is not stacked with the first conductive layer in the first contact hole. The impurity ions contained in the polycrystalline silicon semiconductor are the same as those contained in the oxide semiconductor.

11. The semiconductor device according to claim 1, wherein, The second conductive layer is stacked with the first conductive layer in the first contact hole, but not stacked with the first conductive layer in the second contact hole.

12. The semiconductor device according to claim 1, wherein, The second conductive layer is stacked with the first conductive layer in the first contact hole and the second contact hole.

13. The semiconductor device according to claim 1, wherein, The second conductive layer is not stacked with the first conductive layer in the second contact hole that is covered by the first contact hole.

14. The semiconductor device according to claim 1, wherein, The intermediate insulating layer has a third insulating layer in contact with the oxide semiconductor. The second insulating layer and the third insulating layer are formed of silicon oxide.

15. The semiconductor device according to claim 1, wherein, The second conductive layer is not stacked on the portion of the extension that is in contact with the oxide semiconductor.

16. The semiconductor device according to claim 1, wherein, The second conductive layer is not stacked on top of the first conductive layer above the second contact hole.

17. The semiconductor device according to claim 1, wherein, The thickness of any portion of the second conductive layer is greater than the thickness of the first conductive layer directly below that portion.

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