Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same. The method includes providing a substrate, forming a gate structure and a source / drain plug on the substrate with a sacrificial spacer between the gate structure and the source / drain plug, forming a source / drain contact hole on the source / drain plug, forming a gate contact hole on the gate structure, removing the sacrificial spacer after forming the source / drain contact hole and the gate contact hole to form a cavity between the gate structure and the source / drain plug, and forming a dielectric layer on the gate structure and the source / drain plug with the dielectric layer closing the top of the cavity. The semiconductor structure formed by the method has better performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly realized by continuously reducing the size of integrated circuit devices to improve its speed. At present, due to the demand for high device density, high performance and low cost, the semiconductor industry has progressed to the nanometer technology node, and the preparation of semiconductor devices is limited by various physical limits.

[0003] With the continuous reduction of the size of CMOS devices, challenges from manufacturing and design have promoted the development of three-dimensional designs such as fin field effect transistors (FinFET). Compared with existing planar transistors, FinFET is an advanced semiconductor device for 20nm and below process nodes, which can effectively control the short channel effect caused by the scaling down of devices, and can effectively improve the density of the transistor array formed on the substrate, and at the same time, the gate in the FinFET is arranged around the fin (fin-shaped channel), so it can control static electricity from three sides, and its performance in static electricity control is more prominent.

[0004] However, the performance of the fin field effect transistor formed by the prior art needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate; a gate structure and a source-drain plug located on the substrate, the gate structure and the source-drain plug having a cavity therebetween; a source-drain contact hole located on the source-drain plug; a gate contact hole located on the gate structure; a dielectric layer located on the gate structure and the source-drain plug, and the dielectric layer enclosing the top of the cavity.

[0007] Correspondingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a gate structure and a source-drain plug on the substrate, and the gate structure and the source-drain plug having a sacrificial sidewall therebetween; forming a source-drain contact hole on the source-drain plug; forming a gate contact hole on the gate structure; after forming the source-drain contact hole and the gate contact hole, removing the sacrificial sidewall to form a cavity between the gate structure and the source-drain plug; forming a dielectric layer on the gate structure and the source-drain plug, and the dielectric layer enclosing the top of the cavity.

[0008] Optionally, the method for forming the gate structure, the source / drain plug, and the sacrificial spacer includes: forming a gate structure and a sacrificial material film on the substrate, the sacrificial material film covering the sidewall surface of the gate structure; forming the source / drain plug in the sacrificial material film, and the sacrificial material film between the source / drain plug and the gate structure forming the sacrificial spacer.

[0009] Optionally, the method for forming the gate structure and the sacrificial material film includes: forming a dummy gate structure on the substrate; forming a sacrificial material film on the substrate, and the sacrificial material film covering the sidewall surface of the dummy gate structure; removing the dummy gate structure to form a dummy gate opening in the sacrificial material film; forming the gate structure in the dummy gate opening.

[0010] Optionally, the method further includes: after forming the dummy gate structure and before forming the sacrificial material film, forming a spacer on the sidewall surface of the dummy gate structure; and the sacrificial material film covering the sidewall surface of the spacer.

[0011] Optionally, the method further includes: after forming the spacer and before forming the sacrificial material film, forming a source / drain doped region in the substrate on both sides of the dummy gate structure and the spacer; and after forming the source / drain doped region and before forming the source / drain plug, the bottom of the source / drain plug being in contact with the surface of the source / drain doped region.

[0012] Optionally, the top surface of the source / drain plug is higher than the top surface of the gate structure.

[0013] Optionally, the method further includes: after forming the gate structure and the sacrificial material film and before forming the source / drain plug, forming a first sacrificial layer on the surface of the sacrificial material film and the surface of the gate structure; and forming the source / drain plug in the sacrificial material film and the first sacrificial layer.

[0014] Optionally, the method for forming the source / drain plug includes: forming a plug opening in the sacrificial material film and the first sacrificial layer, the plug opening exposing the surface of the source / drain doped region; forming a source / drain plug material film in the plug opening and on the surface of the first sacrificial layer; and planarizing the source / drain plug material film until the surface of the first sacrificial layer is exposed, the source / drain plug being formed in the plug opening.

[0015] Optionally, the method further includes: after forming the plug opening and before forming the source / drain plug material film, forming a first protective layer on the sidewall surface of the plug opening, and the material of the first protective layer being different from the material of the sacrificial spacer.

[0016] Optionally, the method for forming the source / drain plug material film comprises: forming a plug barrier material film on the bottom and sidewall surface of the plug opening and the surface of the first sacrificial layer; forming a plug conductive material film on the surface of the plug barrier material film, and the plug conductive material film fills the plug opening.

[0017] Optionally, the method further comprises: after forming the source / drain plug, before forming the source / drain contact hole, etching part of the source / drain plug to form a barrier opening in the first sacrificial layer; forming a barrier layer in the barrier opening, the barrier layer is on the top surface of the etched source / drain plug, and the width of the barrier layer is greater than the width of the source / drain plug; after forming the barrier layer, forming the source / drain contact hole, the source / drain contact hole is on the top surface of the etched source / drain plug and penetrates the barrier layer.

[0018] Optionally, the method for forming the barrier opening comprises: forming a mask layer on the surface of the source / drain plug and the surface of the first sacrificial layer, the mask layer exposes the top surface of the source / drain plug and part of the surface of the first sacrificial layer on both sides of the source / drain plug; etching part of the source / drain plug and the first sacrificial layer with the mask layer as a mask to form a barrier opening in the first sacrificial layer, the barrier opening exposes the top surface of the etched source / drain plug.

[0019] Optionally, the method for forming the barrier layer in the barrier opening comprises: forming a barrier material layer in the barrier opening and on the surface of the first sacrificial layer; planarizing the barrier material layer until the surface of the first sacrificial layer is exposed to form the barrier layer in the barrier opening.

[0020] Optionally, the method further comprises: after forming the gate structure and the source / drain plug, before forming the gate contact hole and the source / drain contact hole, forming a second sacrificial layer on the surface of the source / drain plug and the surface of the first sacrificial layer; forming the gate contact hole and the source / drain contact hole in the first sacrificial layer and the second sacrificial layer.

[0021] Optionally, the method for forming the gate contact hole comprises: forming a gate contact opening in the first sacrificial layer and the second sacrificial layer, and the gate contact opening exposes the top surface of the gate structure; forming a gate contact material film in the gate contact opening and on the surface of the second sacrificial layer; planarizing the gate contact material film until the surface of the second sacrificial layer is exposed to form the gate contact hole in the gate contact opening.

[0022] Optionally, after forming the gate contact opening, before forming the gate contact material film, a second protective layer is formed on the sidewall surface of the gate contact opening, and the material of the second protective layer is different from that of the sacrificial sidewall.

[0023] Optionally, the method for forming the gate contact material film includes: forming a gate blocking material film on the bottom and sidewall surface of the gate contact opening and the surface of the second sacrificial layer; and forming a gate conductive material film on the surface of the gate blocking material film, and the gate conductive material film fills the gate contact opening.

[0024] Optionally, the method for forming the source / drain contact hole includes: forming a source / drain contact opening in the first and second sacrificial layers, and the source / drain contact opening exposes the top surface of the source / drain plug; forming a source / drain contact material film in the source / drain contact opening and on the surface of the second sacrificial layer; and planarizing the source / drain contact material film until the surface of the second sacrificial layer is exposed, thereby forming the source / drain contact hole in the source / drain contact opening.

[0025] Optionally, after forming the source / drain contact opening and before forming the source / drain contact material film, a third protective layer is formed on the sidewall surface of the source / drain contact opening, and the material of the third protective layer is different from that of the sacrificial sidewall.

[0026] Optionally, the method for forming the source / drain contact material film includes: forming a source / drain blocking material film on the bottom and sidewall surface of the source / drain contact opening and the surface of the second sacrificial layer; and forming a source / drain conductive material film on the surface of the source / drain blocking material film, and the source / drain conductive material film fills the source / drain contact opening.

[0027] Optionally, the method for forming the dielectric layer includes: forming a lower dielectric layer on the top of the gate structure, the sidewall surface of the source / drain plug, the top and sidewall surface of the gate contact hole, and the top and sidewall surface of the source / drain contact hole, and the lower dielectric layer covers the top of the cavity; and forming an upper dielectric layer on the surface of the lower dielectric layer.

[0028] Optionally, the forming process of the lower dielectric layer is a chemical vapor deposition process, and the chemical vapor deposition process includes an ion-enhanced chemical vapor deposition process or a high-concentration plasma deposition process.

[0029] Optionally, in the process of removing the sacrificial sidewall, the first and second sacrificial layers are also removed, thereby forming a dielectric opening between adjacent source / drain contact holes and gate contact holes, and between part of the source / drain plug and the gate contact hole, and the bottom of the dielectric opening exposes the top surface of the cavity and the top surface of the gate structure.

[0030] Optionally, the substrate includes a substrate and a fin and an isolation layer on the surface of the substrate, and the isolation layer covers part of the sidewall surface of the fin; the gate structure is located on the surface of the isolation layer and spans the fin, and the gate structure is located on the top and sidewall surface of part of the fin.

[0031] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0032] In the semiconductor structure provided by the technical scheme, the source-drain plug and the gate structure have a cavity therebetween, the cavity is an open structure, air is filled in the cavity, the dielectric constant of the cavity is small, which is conducive to reducing the parasitic capacitance between the gate structure and the source-drain plug, thereby improving the performance of the semiconductor structure.

[0033] In the forming method of the semiconductor structure provided by the technical scheme, the gate structure and the source-drain plug are formed on the substrate, and the gate structure and the source-drain plug have a sacrificial sidewall therebetween; after the gate contact hole and the source-drain contact hole are formed, the sacrificial sidewall is removed to form a cavity between the source-drain plug and the gate structure, the cavity is an open structure, air is filled in the cavity, the dielectric constant of the cavity is small, which is conducive to reducing the parasitic capacitance between the gate structure and the source-drain plug, thereby improving the performance of the semiconductor structure.

[0034] Further, the sidewall of the gate structure can protect the gate structure and reduce damage to the sidewall surface of the gate structure in subsequent processes, so that the performance of the gate structure is better.

[0035] Further, after the source-drain plug is formed, part of the source-drain plug is etched; a barrier layer is formed on the top surface of the remaining source-drain plug, and the width of the barrier layer is greater than the width of the source-drain plug. On the one hand, the barrier layer is conducive to the subsequent self-alignment of the source-drain contact hole and will not cause etching damage to the gate structure; on the other hand, the wider barrier layer has a certain barrier buffering effect on the deposited material, so that the deposited material is not easy to enter the cavity during the subsequent deposition process of the dielectric layer, which is conducive to the sealing of the cavity by the dielectric layer, thereby improving the performance of the formed semiconductor structure.

[0036] Further, before the sacrificial sidewall is removed, it further includes: forming a first sacrificial layer and a second sacrificial layer; after the first sacrificial layer and the second sacrificial layer are formed, the gate contact hole and the source-drain contact hole are formed, and then the sacrificial sidewall is removed to form a cavity. In the process of removing the sacrificial sidewall, the first sacrificial layer and the second sacrificial layer are also removed. Not only is the cavity formed between the gate structure and the source-drain plug, but also the cavity is located between part of the gate contact hole and the source-drain plug, and the gate contact hole is located on the top surface of the gate structure. The cavity occupies a larger volume, which is conducive to sufficiently reducing the parasitic capacitance between the gate structure and the source-drain plug, and between part of the gate contact hole and the source-drain plug, thereby improving the performance of the semiconductor structure.

[0037] Further, the semiconductor structure forming method further comprises: after forming the plug opening, and before forming the source-drain plug material film, forming a first protective layer on the sidewall surface of the plug opening, the material of the first protective layer being different from that of the sacrificial sidewall, the first protective layer being capable of protecting the source-drain plug, and reducing etching damage to the sidewall of the source-drain plug in the subsequent process of removing the sacrificial sidewall, so that the source-drain plug has better performance.

[0038] Further, the semiconductor structure forming method further comprises: after forming the gate contact opening, and before forming the gate contact material film, forming a second protective layer on the sidewall surface of the gate contact opening, the material of the second protective layer being different from that of the sacrificial sidewall, the second protective layer being capable of protecting the gate contact hole, and reducing etching damage to the sidewall of the gate contact hole in the subsequent process of removing the sacrificial sidewall, so that the gate contact hole has better performance.

[0039] Further, the semiconductor structure forming method further comprises: after forming the source-drain contact opening, and before forming the source-drain contact material film, forming a third protective layer on the sidewall surface of the source-drain contact opening, the material of the third protective layer being different from that of the sacrificial sidewall, the third protective layer being capable of protecting the source-drain contact hole, and reducing etching damage to the sidewall of the source-drain contact hole in the subsequent process of removing the sacrificial sidewall, so that the source-drain contact hole has better performance. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figures 1 to 4 is a structure schematic diagram of each step of the semiconductor structure forming method in an embodiment.

[0041] Figures 5 to 14 is a structure schematic diagram of each step of the semiconductor structure forming method in an embodiment. DETAILED DESCRIPTION

[0042] It should be noted that the "surface", "upper", in the specification, are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0043] First, the reasons for the poor performance of the existing semiconductor structure are described in detail in combination with the drawings, Figures 1 to 4 is a structure schematic diagram of each step of the semiconductor structure forming method in an embodiment.

[0044] Please refer to Figure 1, a substrate 100 is provided, the substrate has a fin 110 and a dummy gate structure 120, the dummy gate structure 120 crosses the fin 110, and the dummy gate structure 120 is located on part of the top surface and the sidewall surface of the fin 110; a side wall 130 is formed on the sidewall surface of the dummy gate structure 120; a source-drain doped region 140 is formed in the fin 110 on both sides of the dummy gate structure 120 and the side wall 130.

[0045] Please refer to Figure 2 A first dielectric layer 150 is formed on the substrate 100, and the first dielectric layer 150 covers the sidewall surface of the side wall 130.

[0046] Please refer to Figure 3 The dummy gate structure 120 is removed, a dummy gate opening (not shown in the figure) is formed in the first dielectric layer 150; and a gate structure 160 is formed in the dummy gate opening.

[0047] Please refer to Figure 4 After the formation of the gate structure 160, the side wall 130 is removed, a cavity 170 is formed in the first dielectric layer 150; a second dielectric layer 180 is formed on the surface of the first dielectric layer 150, and the second dielectric layer 180 is located on the top of the cavity 170 and seals the top of the cavity 170.

[0048] In the above method, the cavity 170 is formed in the first dielectric layer 150 by removing the side wall 130, specifically, the cavity 170 is an opening structure, and air is filled in the cavity 170. Compared with the material of the side wall 130, the dielectric constant of air is smaller, and the cavity 170 arranged on the sidewall of the gate structure 160 helps to reduce the capacitance between the gate structure 160 and other devices, thereby improving the performance of the formed semiconductor structure.

[0049] However, in the process of removing the side wall 130 to form the cavity 170, the sidewall of the gate structure 160 is exposed and is easily damaged by the etching process, resulting in a decrease in the performance of the gate structure 170 and a poor performance of the semiconductor structure.

[0050] To solve the technical problem, the embodiment of the present application provides a semiconductor structure forming method, which comprises the following steps: forming a gate structure and a source-drain plug on the substrate, and the gate structure and the source-drain plug have a sacrificial sidewall therebetween; forming a source-drain contact hole on the source-drain plug; forming a gate contact hole on the gate structure; and removing the sacrificial sidewall after forming the source-drain contact hole and the gate contact hole, so as to form a cavity between the gate structure and the source-drain plug, and the dielectric constant of the cavity is small, which is beneficial to reduce the parasitic capacitance between the gate structure and the source-drain plug, thereby improving the performance of the semiconductor structure.

[0051] In order to make the above objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0052] Figures 5 to 14 is a structural schematic diagram of each step of the semiconductor structure forming method in the embodiment of the present application.

[0053] Please refer to Figure 5 , a substrate is provided.

[0054] In the embodiment, the substrate comprises a substrate 201 and fin portions 202 and an isolation layer (not shown in the figure) located on the substrate 201, and the isolation layer covers part of the sidewall surface of the fin portions 202.

[0055] In the embodiment, the material of the substrate 201 is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0056] In the embodiment, the material of the fin portions 202 is silicon; in other embodiments, the material of the fin portions can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0057] The isolation layer can play a role of electrically isolating adjacent fin portions 202.

[0058] In the embodiment, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer can also be silicon nitride or silicon oxynitride.

[0059] In other embodiments, the substrate is a planar substrate.

[0060] Then, a gate structure and a source-drain plug are formed on the substrate, and the gate structure and the source-drain plug have a sacrificial sidewall therebetween, and the process of forming the gate structure, the source-drain plug and the sacrificial sidewall will be described below with reference to Figures 6 to 7 .

[0061] Please refer to Figure 6Forming a gate structure 210 and a sacrificial material film 230 on the substrate, the sacrificial material film 230 covering the sidewall surface of the gate structure 210.

[0062] The sacrificial material film 230 functions to provide support for the subsequent formation of source-drain plugs and to occupy space for the subsequent formation of cavities.

[0063] Specifically, the gate structure 210 is located on the surface of the isolation layer and across the fin 202, and the gate structure 210 is located on the top surface and the sidewall surface of the partial fin.

[0064] The forming method of the gate structure 210 and the sacrificial material film 230 includes: forming a dummy gate structure (not shown in the figure) on the substrate; forming a sacrificial material film (not shown in the figure) on the substrate, and the sacrificial material film covering the sidewall surface of the dummy gate structure; removing the dummy gate structure to form a dummy gate opening (not shown in the figure) in the sacrificial material film; and forming the gate structure 210 in the dummy gate opening.

[0065] In the embodiment, the forming method of the semiconductor structure further includes: after forming the dummy gate structure and before forming the sacrificial material film, forming a sidewall 220 on the sidewall surface of the dummy gate structure; and the sacrificial material film covers the sidewall surface of the sidewall 220.

[0066] The sidewall surface of the gate structure 210 has the sidewall 220, which can protect the gate structure 210 and reduce damage to the sidewall surface of the gate structure 210 in subsequent processes, so that the performance of the gate structure 210 is better.

[0067] The material of the sidewall 220 is different from the material of the sacrificial material film 230.

[0068] The material of the sidewall 220 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

[0069] The material of the sacrificial material film 230 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

[0070] In the embodiment, the material of the sidewall 220 is silicon nitride, and the material of the sacrificial material film 230 is silicon oxide.

[0071] The forming method of the semiconductor structure further includes: after forming the sidewall 220 and before forming the sacrificial material film 230, forming a source-drain doped region 204 in the substrate on both sides of the dummy gate structure and the sidewall 220.

[0072] The method for forming the source / drain plug doped region 204 includes: removing part of the substrate on both sides of the dummy gate structure 210 and the sidewall 220 to form a source / drain opening (not shown in the figure) in the substrate; and forming the source / drain doped region 204 in the source / drain opening.

[0073] The method for forming the source / drain doped region 204 in the plug opening includes: forming an epitaxial layer (not shown in the figure) in the plug opening by using an epitaxial growth process; and doping the source / drain ions in the epitaxial layer (not shown in the figure) by using an in-situ doping process during the formation of the epitaxial layer to form the source / drain doped region 204.

[0074] Specifically, in the embodiment, the source / drain doped region 204 is located in the fin 202.

[0075] In the embodiment, the method for forming the semiconductor structure further includes: after forming the source / drain doped region 204, forming a stop layer 205 on the surface of the source / drain doped region 204 before forming the sacrificial material film 230.

[0076] The stop layer 205 is used as a stop layer for etching the plug opening of the source / drain plug.

[0077] In the embodiment, the method for forming the sacrificial material film 230 includes: forming a dielectric material layer (not shown in the figure) covering the dummy gate structure 210 and the sidewall 220 on the substrate, the entire surface of the dielectric material layer being higher than the top surface of the dummy gate structure 210; and removing the dielectric material layer higher than the top surface of the dummy gate structure 210 to form the sacrificial material film 230.

[0078] Please refer to Figure 7 In the embodiment, the method for forming the semiconductor structure further includes: forming a first sacrificial layer 240 on the surface of the sacrificial material film 230 and the surface of the gate structure 210.

[0079] The first sacrificial layer 240 and the sacrificial material film 230 together provide support for the subsequent formation of the source / drain plug.

[0080] The material of the first sacrificial layer 240 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride and titanium dioxide.

[0081] In the embodiment, the material of the first sacrificial layer 240 and the sacrificial material film 230 is the same, and is silicon oxide.

[0082] The first sacrifice layer 240 and the sacrifice material film 230 are of the same material, and part of the sacrifice material film 230 is used to form the sacrifice side wall. In the process of removing the sacrifice side wall to form the cavity, the first sacrifice layer 240 on the surface of the sacrifice material film 230 can be removed by using the same etching process, and then the sacrifice material film 230 is removed, which is beneficial to save the process steps and improve the production efficiency.

[0083] Please continue to refer to Figure 7 The source-drain plug 250 is formed in the sacrifice material film 230, and the sacrifice material film 230 between the source-drain plug 250 and the gate structure 210 forms the sacrifice side wall.

[0084] Specifically, the source-drain plug 250 is formed in the sacrifice material film 230 and the first sacrifice layer 240.

[0085] In this embodiment, the bottom of the source-drain plug 250 is in contact with the surface of the source-drain doped region 205.

[0086] The method for forming the source-drain plug 250 includes: forming a plug opening (not shown in the figure) in the sacrifice material film 230 and the first sacrifice layer 240, the plug opening exposes the surface of the source-drain doped region 204; forming a source-drain plug material film (not shown in the figure) in the plug opening and on the surface of the first sacrifice layer; and planarizing the source-drain plug material film until the surface of the first sacrifice layer 240 is exposed, thereby forming the source-drain plug 250 in the plug opening.

[0087] The method for forming the source-drain plug material film includes: forming a plug barrier material film (not shown in the figure) on the surface of the plug opening, the sidewall of the plug opening, and the surface of the first sacrifice layer 240; and forming a plug conductive material film (not shown in the figure) on the surface of the plug barrier material film, and the plug conductive material film fills the plug opening.

[0088] In this embodiment, the top surface of the source-drain plug 250 is higher than the top surface of the gate structure 240.

[0089] The process of planarizing the source-drain plug material film includes a chemical mechanical polishing process.

[0090] In this embodiment, the method for forming the semiconductor structure further includes: after forming the plug opening and before forming the source-drain plug material film, forming a first protective layer (not shown in the figure) on the sidewall of the plug opening, and the first protective layer and the sacrifice side wall are of different materials.

[0091] Specifically, the first protective layer and the sacrifice material film 230 are of different materials.

[0092] The material of the first protective layer is different from the material of the sacrificial material film 230, and the material of the first protective layer is different from the material of the first sacrificial layer 240.

[0093] The material of the first protective layer comprises one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide. In this embodiment, the material of the first protective layer is silicon nitride.

[0094] By forming the first protective layer on the sidewall surface of the plug opening, the material of the first protective layer is different from that of the sacrificial sidewall, and the first protective layer can protect the source-drain plug 250, reducing etching damage to the sidewall of the source-drain plug 250 in the subsequent process of removing the sacrificial sidewall, so that the performance of the source-drain plug 250 is better.

[0095] Please refer to Figure 8 After forming the source-drain plug 250, a portion of the source-drain plug 250 is etched to form a blocking opening (not shown in the figure) in the first sacrificial layer 240; a blocking layer 260 is formed in the blocking opening, the blocking layer 260 is located on the top surface of the source-drain plug 250 after etching, and the width of the blocking layer 260 is greater than the width of the source-drain plug 250.

[0096] The method for forming the blocking opening comprises: forming a mask layer (not shown in the figure) on the surface of the source-drain plug 250 and the surface of the first sacrificial layer 240, the mask layer exposes the top surface of the source-drain plug 260 and the surface of the first sacrificial layer 240 on both sides of the source-drain plug 260; etching a portion of the source-drain plug 250 and the first sacrificial layer 240 with the mask layer as a mask to form a blocking opening in the first sacrificial layer 240, the blocking opening exposes the top surface of the source-drain plug 250 after etching.

[0097] The method for forming the blocking layer 260 in the blocking opening comprises: forming a blocking material layer (not shown in the figure) in the blocking opening and on the surface of the first sacrificial layer 240; planarizing the blocking material layer until the surface of the first sacrificial layer is exposed to form the blocking layer 260 in the blocking opening.

[0098] The material of the blocking layer 260 is different from that of the first sacrificial layer 240, and the material of the blocking layer 260 comprises one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide. In this embodiment, the material of the blocking layer 260 is silicon nitride.

[0099] The source-drain plug 250 is etched, and the barrier layer 260 is formed in the first sacrificial layer 240. The barrier layer 260 is located on the top surface of the source-drain plug 250 after etching, and the width of the barrier layer 260 is greater than the width of the source-drain plug 250. In one aspect, the barrier layer 260 is beneficial for subsequent self-aligned formation of source-drain contact holes and does not cause etching damage to the gate structure 210. In another aspect, the barrier layer 260 with a greater width has a certain barrier buffering effect on the deposited material, so that the deposited material is not easy to enter the cavity during subsequent deposition of the dielectric layer, which is beneficial for the dielectric layer to seal the top of the cavity, thereby improving the performance of the formed semiconductor structure.

[0100] In other embodiments, the barrier layer can also not be formed.

[0101] After the gate structure 210, the source-drain plug 250, and the sacrificial sidewall are formed, a source-drain contact hole is formed on the source-drain plug 250, and a gate contact hole is formed on the gate structure 210. For details of the process of forming the source-drain contact hole and the gate contact hole, please refer to Figures 9 to 12 .

[0102] Please refer to Figure 9 , a second sacrificial layer 270 is formed on the surface of the source-drain plug 250 and the surface of the first sacrificial layer 240.

[0103] The second sacrificial layer 270 provides support for subsequent formation of source-drain contact holes and gate contact holes.

[0104] The material of the second sacrificial layer 270 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and titanium dioxide.

[0105] In this embodiment, the second sacrificial layer 270 and the first sacrificial layer 240 and the sacrificial material film 230 are made of the same material, which is silicon oxide. Part of the sacrificial material film 230 forms a sacrificial sidewall, which is beneficial for the subsequent process of removing the sacrificial sidewall to form a cavity. The same etching process is used to first remove the second sacrificial layer 270 to expose the surface of the first sacrificial layer 240, and then remove the first sacrificial layer 240 to expose the sacrificial material film 230, and then remove the sacrificial material film 230, which is beneficial for saving process steps and improving production efficiency.

[0106] Specifically, in this embodiment, the second sacrificial layer 270 is formed on the surface of the barrier layer 260 and the surface of the first sacrificial layer 240.

[0107] Please refer to Figure 10A gate contact opening 280 is formed in the first and second sacrificial layers 240 and 270, and exposes a top surface of the gate structure 210.

[0108] In this embodiment, the method further includes, after forming the gate contact opening 280 and before forming a gate contact material film, forming a second protective layer 281 on a sidewall surface of the gate contact opening 280, and the material of the second protective layer 281 is different from that of the sacrificial sidewall.

[0109] By forming the second protective layer 281 on the sidewall surface of the gate contact opening 280, and the material of the second protective layer 281 being different from that of the sacrificial sidewall, the gate contact hole formed later can be protected, and etching damage to the sidewall of the gate contact hole can be reduced during the subsequent removal of the sacrificial sidewall, so that the performance of the gate contact hole is better.

[0110] Please refer to Figure 10 A source / drain contact opening 290 is formed in the first and second sacrificial layers 240 and 270, and exposes a top surface of the source / drain plug 291.

[0111] In this embodiment, the method further includes, after forming the source / drain contact opening 290 and before forming a source / drain contact material film, forming a third protective layer 291 on a sidewall surface of the source / drain contact opening 290, and the material of the third protective layer 291 is different from that of the sacrificial sidewall.

[0112] By forming the third protective layer 291 on the sidewall surface of the source / drain contact opening 290, and the material of the third protective layer 291 being different from that of the sacrificial sidewall, the source / drain contact hole formed later can be protected, and etching damage to the sidewall of the source / drain contact hole can be reduced during the subsequent removal of the sacrificial sidewall, so that the performance of the source / drain contact hole is better.

[0113] In this embodiment, the gate contact opening 280 is formed before the source / drain contact opening 290 is formed; in other embodiments, the source / drain contact opening is formed before the gate contact opening is formed.

[0114] Please refer to Figure 11 A gate contact material film (not shown in the figure) is formed in the gate contact opening 280 and on the surface of the second sacrificial layer 270.

[0115] The gate contact material film provides a material layer for the subsequent formation of a gate contact hole.

[0116] The method for forming the gate contact material film includes: forming a gate blocking material film (not shown in the figure) on the bottom and sidewall surface of the gate contact opening 280 and the surface of the second sacrificial layer 270; forming a gate conductive material film (not shown in the figure) on the surface of the gate blocking material film, and the gate conductive material film fills the gate contact opening 280.

[0117] Specifically, the gate contact material film is located on the surface of the second protective layer 281.

[0118] Please continue to refer to Figure 11 , forming a source-drain contact material film (not shown in the figure) in the source-drain contact opening 290 and on the surface of the second sacrificial layer 270.

[0119] The method for forming the source-drain contact material film includes: forming a source-drain blocking material film (not shown in the figure) on the bottom and sidewall surface of the source-drain contact opening 290 and the surface of the second sacrificial layer 270; forming a source-drain conductive material film (not shown in the figure) on the surface of the source-drain blocking material film, and the source-drain conductive material film fills the source-drain contact opening 290.

[0120] Specifically, the source-drain contact material film is located on the surface of the third protective layer 291.

[0121] It should be noted that the gate contact material film and the source-drain contact material film are formed by the same deposition process, thereby facilitating the saving of process steps and improving production efficiency.

[0122] Please refer to Figure 12 , planarizing the gate contact material film until the surface of the second sacrificial layer 270 is exposed, and forming the gate contact hole 282 in the gate contact opening 280.

[0123] Please continue to refer to Figure 12, planarizing the source-drain contact material film until the surface of the second sacrificial layer 280 is exposed, and forming the source-drain contact hole 292 in the source-drain contact opening 290.

[0124] Specifically, the source-drain contact hole 292 is located on the top surface of the source-drain plug 250 after etching and penetrates the blocking layer 260.

[0125] Specifically, the planarization of the gate contact material film and the planarization of the source-drain contact material film adopt the same planarization process, thereby facilitating the saving of process steps and improving production efficiency.

[0126] Please refer to Figure 13 , after forming the source-drain contact hole 292 and the gate contact hole 282, removing the sacrificial sidewall to form a cavity 295 between the gate structure 210 and the source-drain plug 250.

[0127] In the embodiment, the sacrificial material film 230 between the source-drain plug 250 and the gate structure 210 forms the sacrificial sidewall, and the first sacrificial layer 240 and the second sacrificial layer 270 are made of the same material as the sacrificial material film 230, so that in the process of removing the sacrificial sidewall, the sacrificial material film 230, the first sacrificial layer 240 and the second sacrificial layer 270 can be removed by the same etching process, thereby saving the process steps and saving the process time.

[0128] Specifically, in the process of removing the sacrificial sidewall, the first sacrificial layer 240 and the second sacrificial layer 270 are also removed, forming a dielectric opening 296 between the adjacent source-drain contact hole 292 and the gate contact hole 282, and between part of the source-drain plug 250 and the gate contact hole 282, and the dielectric opening 296 exposes the top surface of the cavity 295 and the top surface of the gate structure 210 at the bottom.

[0129] The size of the cavity 295 in the direction perpendicular to the sidewall of the cavity 295 ranges from 5 nanometers to 10 nanometers.

[0130] The depth of the cavity 295 ranges from 10 nanometers to 40 nanometers.

[0131] The depth refers to the size in the direction perpendicular to the substrate surface.

[0132] Before removing the sacrificial sidewall, it also includes forming the first sacrificial layer 240 and the second sacrificial layer 270; after forming the first sacrificial layer 240 and the second sacrificial layer 270, and after forming the gate contact hole 282 and the source-drain contact hole 292, in the process of removing the sacrificial sidewall, the first sacrificial layer 240 and the second sacrificial layer 290 are also removed, not only forming the cavity 295 between the gate structure 210 and the source-drain plug 250, but also between part of the gate contact hole 282 and the source-drain plug 250, and the gate contact hole 282 is located on the top surface of the gate structure 210, and the cavity 290 occupies a larger volume, which is beneficial to sufficiently reduce the parasitic capacitance between the gate structure 210 and the source-drain plug 250, and between part of the gate contact hole 282 and the source-drain plug 250, thereby improving the performance of the semiconductor structure.

[0133] At this point, by forming the gate structure 210 and the source-drain plug 250 on the substrate, and the sacrificial sidewall between the gate structure 210 and the source-drain plug 250; forming the gate contact hole 282 and the source-drain contact hole 292, and then removing the sacrificial sidewall to form the cavity 295 between the source-drain plug 250 and the gate structure 210, since the cavity 295 is an open structure, air is filled in the cavity 295, and the dielectric constant of the cavity 295 is small, which is beneficial to reduce the parasitic capacitance between the gate structure 210 and the source-drain plug 250, thereby improving the performance of the semiconductor structure.

[0134] Please refer to Figure 14 The dielectric layer 310 is formed on the gate structure 210 and the source-drain plug 250, and the dielectric layer 310 seals the top of the cavity 295.

[0135] The forming method of the dielectric layer 310 includes: forming a lower dielectric layer 311 on the top of the gate structure 210, the partial sidewall surface of the source-drain plug 250, the top surface and the sidewall surface of the gate contact hole 282, and the top surface and the sidewall surface of the source-drain contact hole 292, and the lower dielectric layer 311 seals the top of the cavity 295; forming an upper dielectric layer 312 on the surface of the lower dielectric layer 311.

[0136] The forming process of the lower dielectric layer 311 is a chemical vapor deposition process, which includes an ion-enhanced chemical vapor deposition process or a high-concentration plasma deposition process.

[0137] In this embodiment, the ion-enhanced chemical vapor deposition process is used to form the lower dielectric layer 311, and the process has poor filling property, which is beneficial to form a film layer on the top of the cavity 295 to seal the top of the cavity 295.

[0138] Correspondingly, the embodiment of the present application also provides a semiconductor structure formed by the above method, which includes: a substrate; a gate structure 210 and a source-drain plug 250 formed on the substrate, and a cavity 295 between the gate structure 210 and the source-drain plug 250; a source-drain contact hole 292 on the source-drain plug 250; a gate contact hole 282 on the gate structure 210; and a dielectric layer 310 on the gate structure 210 and the source-drain plug 250, and the dielectric layer 310 seals the top of the cavity 295.

[0139] The cavity 295 is between the source-drain plug 250 and the gate structure 210, since the cavity 295 is an open structure, air is filled in the cavity 295, and the dielectric constant of the cavity 295 is small, which is beneficial to reduce the parasitic capacitance between the gate structure 210 and the source-drain plug 250, thereby improving the performance of the semiconductor structure.

[0140] Although the present application has been disclosed with reference to the above examples, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The method comprises: providing a substrate; forming a gate structure and a source-drain plug on the substrate, and the gate structure and the source-drain plug have a cavity therebetween; forming a source-drain contact hole on the source-drain plug; forming a gate contact hole on the gate structure; after forming the source-drain contact hole and the gate contact hole, removing the sacrificial sidewall to form a cavity between the gate structure and the source-drain plug; forming a dielectric layer on the gate structure and the source-drain plug, and the dielectric layer closes the top of the cavity; after forming the gate structure and the sacrificial material film, forming a first sacrificial layer on the surface of the sacrificial material film and the surface of the gate structure before forming the source-drain plug; the sacrificial material film between the source-drain plug and the gate structure forms the sacrificial sidewall; etching part of the source-drain plug and the first sacrificial layer to form a barrier opening in the first sacrificial layer, and forming a barrier layer in the barrier opening, the barrier layer is located on the top surface of the source-drain plug after etching, and the width of the barrier layer is greater than the width of the source-drain plug.

2. A method of forming a semiconductor structure, characterized by, The method for forming the gate structure, the source-drain plug, and the sacrificial sidewall comprises: forming a gate structure and a sacrificial material film on the substrate, and the sacrificial material film covers the sidewall surface of the gate structure; forming the source-drain plug in the sacrificial material film, and the sacrificial material film between the source-drain plug and the gate structure forms the sacrificial sidewall. The method for forming the gate structure and the sacrificial material film comprises: forming a pseudo gate structure on the substrate; forming a sacrificial material film on the substrate, and the sacrificial material film covers the sidewall surface of the pseudo gate structure; removing the pseudo gate structure to form a pseudo gate opening in the sacrificial material film; forming the gate structure in the pseudo gate opening. Further comprising: ​ ​ ​ ​ ​ ​ 3. The method of forming a semiconductor structure of claim 2, wherein, ​ 4. The method of forming a semiconductor structure of claim 3, wherein, ​ 5. The method of forming a semiconductor structure of claim 4, wherein ​ After the dummy gate structure is formed and before the sacrificial material film is formed, a sidewall is formed on the sidewall surface of the dummy gate structure. The sacrificial material membrane covers the sidewall surface.

6. The method of forming a semiconductor structure of claim 5, wherein, Also includes: After the sidewalls are formed and before the sacrificial material film is formed, source and drain doped regions are formed in the substrate on both sides of the dummy gate structure and the sidewalls. After the source / drain doped region is formed, the source / drain plug is formed, and the bottom of the source / drain plug is in contact with the surface of the source / drain doped region.

7. The method of forming a semiconductor structure of claim 6, wherein, The top surface of the source / drain plug is higher than the top surface of the gate structure.

8. The method of forming a semiconductor structure of claim 7, wherein, Also includes: After forming the gate structure and the sacrificial material film and before forming the source / drain plugs, a first sacrificial layer is formed on the surface of the sacrificial material film and the surface of the gate structure; The source / drain plug is formed within the sacrificial material film and the first sacrificial layer.

9. The method of forming a semiconductor structure of claim 8, wherein, The method for forming the source / drain plug includes: forming a plug opening in the sacrificial material film and the first sacrificial layer, the plug opening exposing the surface of the source / drain doped region; forming a source / drain plug material film in the plug opening and on the surface of the first sacrificial layer; planarizing the source / drain plug material film until the surface of the first sacrificial layer is exposed, and forming the source / drain plug in the plug opening.

10. The method of forming a semiconductor structure of claim 9, wherein Also includes: After the plug opening is formed and before the source / drain plug material film is formed, a first protective layer is formed on the sidewall surface of the plug opening, and the first protective layer is made of a different material than the sacrificial sidewall.

11. The method of forming a semiconductor structure of claim 9, wherein, The method for forming the source / drain plug material film includes: forming a plug blocking material film on the bottom and sidewall surfaces of the plug opening and on the surface of the first sacrificial layer; forming a plug conductive material film on the surface of the plug blocking material film, wherein the plug conductive material film fills the plug opening.

12. The method of forming a semiconductor structure of claim 8, wherein, After the barrier layer is formed, the source / drain contact hole is formed. The source / drain contact hole is located on the top surface of the etched source / drain plug and extends through the barrier layer.

13. The method of forming a semiconductor structure of claim 12, wherein, The method for forming the blocking opening includes: forming a mask layer on the surface of the source / drain plug and the surface of the first sacrificial layer, the mask layer exposing the top surface of the source / drain plug and the surface of the first sacrificial layer on both sides of the source / drain plug; using the mask layer as a mask, etching a portion of the source / drain plug and the first sacrificial layer to form a blocking opening in the first sacrificial layer, the blocking opening exposing the top surface of the source / drain plug after etching.

14. The method of forming a semiconductor structure of claim 13, wherein, The method of forming a barrier layer within the barrier opening includes: forming a barrier material layer within the barrier opening and on the surface of a first sacrificial layer; planarizing the barrier material layer until the surface of the first sacrificial layer is exposed, thereby forming the barrier layer within the barrier opening.

15. The method of forming a semiconductor structure of claim 8, wherein, Also includes: After forming the gate structure and the source / drain plug, and before forming the gate contact hole and the source / drain contact hole, a second sacrificial layer is formed on the surface of the source / drain plug and the surface of the first sacrificial layer; The gate contact and source / drain contact are formed within the first and second sacrificial layers.

16. The method of forming a semiconductor structure of claim 15, wherein, The method for forming the gate contact hole includes: forming a gate contact opening in the first sacrificial layer and the second sacrificial layer, wherein the gate contact opening exposes the top surface of the gate structure; forming a gate contact material film in the gate contact opening and on the surface of the second sacrificial layer; planarizing the gate contact material film until the surface of the second sacrificial layer is exposed, and forming the gate contact hole in the gate contact opening.

17. The method of forming a semiconductor structure of claim 16, wherein, After the gate contact opening is formed but before the gate contact material film is formed, a second protective layer is formed on the sidewall surface of the gate contact opening, and the material of the second protective layer is different from that of the sacrificial sidewall.

18. The method of forming a semiconductor structure of claim 16, wherein, The method for forming the gate contact material film includes: forming a gate blocking material film on the bottom and sidewall surfaces of the gate contact opening and on the surface of the second sacrificial layer; forming a gate conductive material film on the surface of the gate blocking material film, wherein the gate conductive material film fills the gate contact opening.

19. The method of forming a semiconductor structure of claim 15, wherein, The method for forming the source / drain contact hole includes: forming a source / drain contact opening in the first sacrificial layer and the second sacrificial layer, wherein the source / drain contact opening exposes the top surface of the source / drain plug; forming a source / drain contact material film in the source / drain contact opening and on the surface of the second sacrificial layer; planarizing the source / drain contact material film until the surface of the second sacrificial layer is exposed, thereby forming the source / drain contact hole in the source / drain contact opening.

20. The method of forming a semiconductor structure of claim 19, wherein, After the source / drain contact opening is formed, and before the source / drain contact material film is formed, a third protective layer is formed on the sidewall surface of the source / drain contact opening, and the material of the third protective layer is different from that of the sacrificial sidewall.

21. The method of forming a semiconductor structure of claim 19, wherein, The method for forming the source / drain contact material film includes: forming a source / drain blocking material film on the bottom and sidewall surfaces of the source / drain contact opening and on the surface of the second sacrificial layer; forming a source / drain conductive material film on the surface of the source / drain blocking material film, wherein the source / drain conductive material film fills the source / drain contact opening.

22. The method of forming a semiconductor structure of claim 2, wherein, The method for forming the dielectric layer includes: forming a lower dielectric layer on the top of the gate structure, the sidewall surface of the source / drain plug portion, the top surface and sidewall surface of the gate contact hole, and the top surface and sidewall surface of the source / drain contact hole, wherein the lower dielectric layer seals the top of the cavity; and forming an upper dielectric layer on the surface of the lower dielectric layer.

23. The method of forming a semiconductor structure of claim 22, wherein, The formation process of the lower dielectric layer is a chemical vapor deposition process, which includes ion-enhanced chemical vapor deposition or high-concentration plasma deposition.

24. The method of forming a semiconductor structure of claim 15, wherein, During the removal of the sacrificial sidewall, the first sacrificial layer and the second sacrificial layer are also removed, forming a dielectric opening between adjacent source / drain contact holes and gate contact holes, and between a portion of the source / drain plug and the gate contact hole, with the bottom of the dielectric opening exposing the top surface of the cavity and the top surface of the gate structure.

25. The method of forming a semiconductor structure of claim 2, wherein, The substrate includes: a substrate and a fin and an isolation layer located on the surface of the substrate, wherein the isolation layer covers a portion of the sidewall surface of the fin; the gate structure is located on the surface of the isolation layer and spans the fin, wherein the gate structure is located on the top surface and sidewall surface of a portion of the fin.

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