Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, a first fin being disposed on the first region and a second fin being disposed on the second region; forming an initial isolation layer on the substrate; forming a barrier layer on the initial isolation layer, on the first fin and on the second fin; forming a first well region within the first fin and a second well region within the second fin; forming a buffer layer within the barrier layer on the second region; etching the barrier layer, the buffer layer and a part of the initial isolation layer to form an isolation layer, the top surface of the isolation layer on the first region being flush with the top surface of the isolation layer on the second region. The etching rate can be adjusted by the buffer layer, so that the top surface of the isolation layer finally located on the first region is flush with the top surface of the isolation layer located on the second region, thereby reducing the difference in the electrical performance of the transistor structures formed on the first well region and the second well region and improving the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the ability of traditional planar MOS transistors to control channel current becomes weaker, resulting in serious leakage current. A fin field effect transistor (FinFET) is a new type of multi-gate device.

[0003] A fin field effect transistor includes: a fin portion located on a substrate; a gate straddling the fin portion; a source and a drain located in the fin portions on both sides of the gate, with the source and the gate, and the drain and the gate being separated from each other. Compared with CMOS transistors, the fin field effect transistor is a similar three-dimensional structure located on the substrate, with smaller feature sizes and better meeting the requirements of high integration. Moreover, the gate of the fin field effect transistor is opposite to the upper surface of the fin portion, and the gate is also opposite to the two opposite sidewall surfaces of the fin portion. When working, the upper surface and the two opposite sidewall surfaces of the fin portion in contact with the gate can both form channel regions, which improves the carrier mobility.

[0004] However, the performance of fin field effect transistors formed by the prior art still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region arranged along a first direction, the first region having a first fin portion, and the second region having a second fin portion; forming an initial isolation layer on the substrate, the initial isolation layer covering the first fin portion and the second fin portion; forming a barrier layer on the initial isolation layer, on the first fin portion, and on the second fin portion; forming a first well region located in the first fin portion and a second well region located in the second fin portion; after forming the first well region and the second well region, forming a buffer layer in the barrier layer on the second region; etching the barrier layer, the buffer layer, and a part of the initial isolation layer to form an isolation layer, the top surface of the isolation layer being lower than the top surfaces of the first fin portion and the second fin portion, and the top surface of the isolation layer on the first region being flush with the top surface of the isolation layer on the second region.

[0007] Optionally, when etching the barrier layer and the buffer layer, the etching rate of the buffer layer is less than or greater than the etching rate of the barrier layer.

[0008] Optionally, the first well region is formed before the second well region.

[0009] Optionally, the method for forming the first well region and the second well region includes: forming a first patterned layer on the barrier layer, the first patterned layer covering the barrier layer located on the second region; performing an implantation process of a first ion on the first region to form the first well region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the barrier layer, the second patterned layer covering the barrier layer located on the first region; performing an implantation process of a second ion on the second region to form the second well region.

[0010] Optionally, the method for forming the buffer layer includes: using the second patterned layer as a mask, performing an implantation process of a third ion on the barrier layer located on the second region to form the buffer layer.

[0011] Optionally, the third ion includes: carbon ion, silicon ion or argon ion.

[0012] Optionally, the implantation process parameters of the third ion include: the implantation dose is 1E15 atom / cm 3 ~2E16 atom / cm 3 ; the implantation energy is 0.5 Kev~5 Kev.

[0013] Optionally, after forming the buffer layer, the second patterned layer is removed.

[0014] Optionally, the thickness of the buffer layer is less than or equal to the thickness of the barrier layer.

[0015] Optionally, the thickness of the barrier layer is 120 Å~180 Å.

[0016] Optionally, the thickness of the buffer layer is 80 Å~120 Å.

[0017] Optionally, the conduction types of the first ion and the second ion are opposite.

[0018] Optionally, when the first ion is an N-type ion and the second ion is a P-type ion, the etching rate of the buffer layer is less than the etching rate of the barrier layer.

[0019] Optionally, when the first ion is a P-type ion and the second ion is an N-type ion, the etching rate of the buffer layer is greater than the etching rate of the barrier layer.

[0020] Optionally, the material of the barrier layer includes silicon oxide.

[0021] Optionally, the formation process of the blocking layer includes a high-density plasma chemical vapor deposition process.

[0022] Optionally, the process of forming the initial isolation layer includes a chemical vapor deposition process.

[0023] Optionally, the top surface of the initial isolation layer is higher than or flush with the top surfaces of the first fin and the second fin.

[0024] Optionally, the thickness of the initial isolation layer is 100 nanometers to 200 nanometers.

[0025] Optionally, the thickness of the isolation layer is 60 nanometers to 100 nanometers.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the formation method of the technical solution of the present invention, a buffer layer is formed in the blocking layer on the second region, and the etching rate of the buffer layer is less than or greater than that of the blocking layer. During the back-etching of the initial isolation layer, the buffer layer can adjust the etching rate, so that the top surface of the isolation layer finally located on the first region is flush with the top surface of the isolation layer located on the second region, thereby reducing the difference in the electrical performance of the transistor structures formed on the first well region and the second well region, and improving the performance of the finally formed semiconductor structure.

[0028] Furthermore, the formation method of the buffer layer includes: using the second patterned layer as a mask, performing an implantation process of a third ion on the blocking layer located on the second region to form the buffer layer. By using the second patterned layer as a mask for forming the buffer layer, no additional patterned layer needs to be added, effectively reducing the manufacturing cost and improving the production efficiency at the same time. Description of the Drawings

[0029] Figures 1 to 2 is a schematic structural diagram of a semiconductor structure;

[0030] Figures 3 to 9 is a schematic structural diagram of each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Embodiments

[0031] As in the background art, the performance of the fin field effect transistor formed by the prior art still needs to be improved. The following will be specifically described with reference to the drawings.

[0032] Please refer to Figure 1, a substrate 100 is provided. The substrate 100 includes a first region I and a second region II arranged along a first direction X. A first fin 101 is provided on the first region I, and a second fin 102 is provided on the second region II. An initial isolation layer 103 is formed on the substrate 100, and the initial isolation layer 103 covers the first fin 101 and the second fin 102. A first well region 104 located in the first fin 101 and a second well region 105 located in the second fin 102 are formed. A first ion is provided in the first well region 104, and a second ion is provided in the second well region 105. The electrical types of the first ion and the second ion are different.

[0033] Please refer to Figure 2 , the initial isolation layer 103 is etched back to form an isolation layer 106. The isolation layer 106 covers partial sidewalls of the first fin 101 and the second fin 102, and the top surface of the isolation layer 106 is lower than the top surfaces of the first fin 101 and the second fin 102.

[0034] In this embodiment, due to the different types and concentrations of ions implanted in the first well region 104 and the second well region 105, the types and concentrations of residual ions in the initial isolation layer 103 on the first well region 104 and the second well region 105 are also different. Furthermore, the physical properties of the initial isolation layer 103 on the first well region 104 and the second well region 105 are different. When the initial isolation layer 103 is etched back subsequently, the heights of the isolation layer 106 remaining on the first well region 104 and the second well region 105 are different.

[0035] Since the rate of electron migration is related to the sidewall height of the exposed first fin 101 or second fin 102, when the sidewall height of the exposed first fin 101 or second fin 102 is higher, the corresponding electron migration rate formed is higher. In this embodiment, when the heights of the isolation layer 106 on the first well region 104 and the second well region 105 are different, the sidewall heights of the exposed first fin 101 or second fin 102 are also different, resulting in significant differences in the electrical performance of the final transistor structure, and further affecting the performance of the finally formed semiconductor structure.

[0036] On this basis, the present invention provides a method for forming a semiconductor structure. A buffer layer is formed in a barrier layer on the second region, and the etching rate of the buffer layer is less than or greater than that of the barrier layer. During the back-etching of the initial isolation layer, the buffer layer can adjust the etching rate so that the top surface of the isolation layer finally located on the first region is flush with the top surface of the isolation layer located on the second region, thereby reducing the difference in electrical performance of the transistor structures formed on the first well region and the second well region and improving the performance of the finally formed semiconductor structure.

[0037] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0038] Figures 3 to 9 It is a schematic structural diagram of a process for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 3 , a substrate 200 is provided. The substrate 200 includes a first region I and a second region I arranged along a first direction X. A first fin 201 is provided on the first region I, and a second fin 202 is provided on the second region II.

[0040] In this embodiment, the methods for forming the substrate 200, the first fin 201, and the second fin 202 include: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a part of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200, the first fin 201, and the second fin 202; after forming the substrate 200, the first fin 201, and the second fin 202, removing the patterned layer.

[0041] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0042] In this embodiment, the materials of the first fin 201 and the second fin 202 are silicon; in other embodiments, the materials of the first fin and the second fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0043] Please refer to Figure 4 , an initial isolation layer 203 is formed on the substrate 200, and the initial isolation layer 203 covers the first fin 201 and the second fin 202.

[0044] In this embodiment, the process for forming the initial isolation layer 203 uses a chemical vapor deposition process.

[0045] In this embodiment, the top surface of the initial isolation layer 203 is flush with the top of the first fin 201 and the top surface of the second fin 202. In other embodiments, the top surface of the initial isolation layer may also be higher than the top of the first fin and the top of the second fin.

[0046] In this embodiment, the method for forming the initial isolation layer 203 includes: forming an isolation material film (not shown) on the substrate 200; after planarizing the isolation material film until the top surfaces of the first fin 201 and the second fin 202 are exposed, forming the initial isolation layer 203.

[0047] In this embodiment, the thickness of the initial isolation layer 203 is 100 nanometers to 200 nanometers.

[0048] In this embodiment, the material of the initial isolation layer 203 is silicon oxide.

[0049] Please refer to Figure 5 , a barrier layer 204 is formed on the initial isolation layer 203, on the first fin 201, and on the second fin 202.

[0050] In this embodiment, the function of the barrier layer 204 is that during the subsequent process of forming the first well region and the second well region by ion implantation, the barrier layer 204 can effectively reduce the damage to the first fin 201 and the second fin 202 caused by excessive ion implantation energy.

[0051] In this embodiment, the thickness of the barrier layer 204 is 120 angstroms to 180 angstroms.

[0052] In this embodiment, the material of the barrier layer 204 is silicon oxide.

[0053] In this embodiment, the formation process of the barrier layer 204 uses a high-density plasma chemical vapor deposition process.

[0054] After forming the barrier layer 204, it further includes: forming a first well region in the first fin 201 and a second well region in the second fin 202. For the specific process, please refer to Figures 6 to 7 .

[0055] Please refer to Figure 6 , a first patterned layer 205 is formed on the barrier layer 204, and the first patterned layer 205 covers the barrier layer 204 located on the second region II; the first region I is subjected to an ion implantation process of the first ions to form the first well region 206.

[0056] In this embodiment, the first well region 206 is formed before the second well region is formed.

[0057] In this embodiment, the first ion is an N-type ion, and phosphorus is used for the N-type ion. In other embodiments, the first ion can also be a P-type ion.

[0058] Please refer to Figure 7 , after the first well region 206 is formed, the first patterned layer 205 is removed; a second patterned layer 207 is formed on the barrier layer 204, and the second patterned layer 207 covers the barrier layer 204 located on the first region I; the second region II is subjected to an implantation process of a second ion to form the second well region 208.

[0059] In this embodiment, the conduction types of the first ion and the second ion are opposite.

[0060] In this embodiment, the second ion is a P-type ion, and boron is used for the P-type ion. In other embodiments, the second ion can also be an N-type ion.

[0061] Please refer to Figure 8 , after the first well region 206 and the second well region 208 are formed, a buffer layer 209 is formed in the barrier layer 204 on the second region II.

[0062] In this embodiment, the method for forming the buffer layer 209 includes: using the second patterned layer 207 as a mask, performing an implantation process of a third ion on the barrier layer 204 located on the second region II to form the buffer layer 209.

[0063] Using the second patterned layer 207 as a mask, performing an implantation process of a third ion on the barrier layer 204 located on the second region II to form the buffer layer 209. By using the second patterned layer 204 as a mask for forming the buffer layer 209, no additional patterned layer needs to be added, effectively reducing the manufacturing cost and also improving the production efficiency.

[0064] The third ion includes: carbon ion, silicon ion or argon ion. In this embodiment, the third ion uses carbon ion.

[0065] In this embodiment, the implantation process parameters of the third ion include: implantation dose is 1E15 atom / cm 3 ~2E16 atom / cm 3 ; implantation energy is 0.5 Kev~5 Kev.

[0066] In this embodiment, the thickness of the buffer layer 209 is less than or equal to the thickness of the barrier layer 204, and the thickness of the buffer layer 209 is 80 angstroms to 120 angstroms.

[0067] Please continue to refer to Figure 8 , after forming the buffer layer 209, remove the second patterning layer 207.

[0068] Please refer to Figure 9 , etch the barrier layer 204, the buffer layer 209, and a part of the initial isolation layer 203 to form an isolation layer 210. The top surface of the isolation layer 210 is lower than the top surfaces of the first fin 201 and the second fin 202, and the top surface of the isolation layer 210 located in the first region I is flush with the top surface of the isolation layer 210 located in the second region II.

[0069] In this embodiment, when etching the barrier layer 204 and the buffer layer 209, the etching rate of the buffer layer 209 is less than or greater than the etching rate of the barrier layer 204.

[0070] In this embodiment, when the first ion is an N-type ion and the second ion is a P-type ion, the etching rate of the buffer layer 209 is less than the etching rate of the barrier layer 204. During the process of etching back the initial isolation layer 203 to form the isolation layer 210, the etching rate can be adjusted through the buffer layer 209, so that the top surface of the isolation layer 210 located in the first region I is flush with the top surface of the isolation layer 210 located in the second region II, thereby reducing the difference in the electrical performance of the transistor structures formed on the first well region 206 and the second well region 208 and improving the performance of the finally formed semiconductor structure.

[0071] In other embodiments, when the first ion is a P-type ion and the second ion is an N-type ion, the etching rate of the buffer layer 209 is greater than the etching rate of the barrier layer 204.

[0072] In this embodiment, the thickness of the isolation layer 210 is 60 nanometers to 100 nanometers.

[0073] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a first region and a second region arranged in a first direction, a first fin being on the first region and a second fin being on the second region; Forming an initial isolation layer on the substrate, the initial isolation layer covering the first fin and the second fin; Forming a barrier layer on the initial isolation layer, on the first fin, and on the second fin; After forming the barrier layer, forming a first well region within the first fin and a second well region within the second fin; After forming the first well region and the second well region, forming a buffer layer within the barrier layer on the second region; Etching the barrier layer, the buffer layer, and a part of the initial isolation layer to form an isolation layer, a top surface of the isolation layer being lower than top surfaces of the first fin and the second fin, and a top surface of the isolation layer on the first region being flush with a top surface of the isolation layer on the second region; wherein, when etching the barrier layer and the buffer layer, an etching rate of the buffer layer is less than or greater than an etching rate of the barrier layer.

2. The method for forming a semiconductor structure according to claim 1, wherein, The first well region is formed before the second well region.

3. The method for forming a semiconductor structure according to claim 2, wherein Methods for forming the first well region and the second well region include: forming a first patterned layer on the barrier layer, the first patterned layer covering the barrier layer on the second region; performing an implantation process of a first ion on the first region to form the first well region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the barrier layer, the second patterned layer covering the barrier layer on the first region; performing an implantation process of a second ion on the second region to form the second well region.

4. The method for forming a semiconductor structure as described in claim 3, wherein A method for forming the buffer layer includes: using the second patterned layer as a mask, performing an implantation process of a third ion on the barrier layer on the second region to form the buffer layer.

5. The method for forming a semiconductor structure as claimed in claim 4, wherein, The third ion includes: a carbon ion, a silicon ion, or an argon ion.

6. The method for forming a semiconductor structure according to claim 4, wherein, The implantation processing parameters of the third ion include: the implantation dose is 1E15 atom / cm 3 ~2E16 atom / cm 3 ; the implantation energy is 0.5 Kev~5 Kev.

7. The method for forming the semiconductor structure according to claim 4, wherein, After forming the buffer layer, removing the second patterned layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, A thickness of the buffer layer is less than or equal to a thickness of the barrier layer.

9. The method for forming a semiconductor structure as claimed in claim 8, wherein The thickness of the barrier layer is 120 Å to 180 Å.

10. The method for forming a semiconductor structure as described in claim 8, wherein, The thickness of the buffer layer is 80 Å to 120 Å.

11. The method for forming the semiconductor structure according to claim 3, wherein The first ion and the second ion have opposite conduction types.

12. The method for forming a semiconductor structure as claimed in claim 11, wherein When the first ion is an N-type ion and the second ion is a P-type ion, the etching rate of the buffer layer is less than the etching rate of the barrier layer.

13. The method for forming a semiconductor structure according to claim 11, wherein, When the first ion is a P-type ion and the second ion is an N-type ion, the etching rate of the buffer layer is greater than the etching rate of the barrier layer.

14. The method for forming a semiconductor structure according to claim 1, wherein The material of the barrier layer includes silicon oxide.

15. The method for forming a semiconductor structure according to claim 1, wherein The forming process of the barrier layer includes a high-density plasma chemical vapor deposition process.

16. The method for forming the semiconductor structure according to claim 1, wherein, The process for forming the initial isolation layer includes a chemical vapor deposition process.

17. The method for forming a semiconductor structure as claimed in claim 1, wherein, A top surface of the initial isolation layer is higher than or flush with top surfaces of the first fin and the second fin.

18. The method for forming a semiconductor structure according to claim 17, wherein, The thickness of the initial isolation layer is 100 nm to 200 nm.

19. The method for forming a semiconductor structure as claimed in claim 1, wherein, The thickness of the isolation layer is 60 nm to 100 nm.

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