Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate, the substrate including a first region and a second region, the first region having a first fin and the second region having a second fin; a first gate structure, a second gate structure, a first source / drain doped layer, a second source / drain doped layer, and a first dielectric layer, wherein the top surface of the first dielectric layer in the first region is lower than the top surface of the first dielectric layer in the second region; a first barrier layer located on the first dielectric layer in the first region; a first opening and a second opening, the first opening being located within the first barrier layer and the first dielectric layer in the first region, and the second opening being located within the first dielectric layer in the second region. Because the etching rate of the first barrier layer is lower than that of the first dielectric layer, a certain amount of etching time is consumed by the first barrier layer during the formation of the first opening, thereby reducing the time required to etch the first source / drain doped layer, preventing etching from penetrating the first source / drain doped layer, and improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As semiconductor device integration increases, the critical dimensions of transistors continue to shrink. This reduction in critical dimensions allows for more transistors to be placed on a chip, thereby improving device performance. However, as device area continues to shrink, problems arise. With the rapid reduction in transistor size, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress short-channel effects, resulting in increased channel leakage current in transistors.

[0003] As MOS transistors shrink, the gate becomes shorter, shortening the current channel beneath the gate. When the MOS transistor channel shortens to a certain extent, the short channel effect occurs. Theoretically, the channel length is the distance from the source extension to the drain extension. However, the effective channel length varies due to the influence of the junction voids formed by the source and drain electrodes and the substrate. When the channel length is equal to or shorter than the depth of the junction voids, the junction voids significantly cut into the current channel, causing a decrease in the gate threshold voltage. This is the short channel effect.

[0004] In order to reduce the short channel effect of semiconductor devices, a long channel gate structure is introduced in the prior art, that is, the width of the gate structure along the extension direction of the fin is increased.

[0005] However, in the prior art, when a long channel gate structure and a short channel gate structure coexist in a semiconductor structure, other problems may arise, resulting in reduced performance of the resulting semiconductor structure. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; a plurality of first gate structures, a plurality of second gate structures, a plurality of first source-drain doped layers, a plurality of second source-drain doped layers and a first dielectric layer, the first gate structure spanning the first fins, adjacent first gate structures having a first dimension along the first direction, the second gate structure spanning the second fins, adjacent second gate structures having a second dimension along the first direction, the second dimension being smaller than the first dimension, the first source-drain doped layers being located at the first gate junctions, The first fins on both sides of the second gate structure, the second source-drain doped layers are located in the second fins on both sides of the second gate structure, the thickness of the second source-drain doped layers is greater than the thickness of the first source-drain doped layers, the first dielectric layer covers the sidewalls of the first gate structure and the second gate structure, and the top surface of the first dielectric layer located on the first region is lower than the top surface of the first dielectric layer located on the second region; a first barrier layer, the first barrier layer is located on the first dielectric layer on the first region; a first opening and a second opening, the first opening is located in the first barrier layer and the first dielectric layer on the first region, the first opening exposes the first source-drain doped layers, the second opening is located in the first dielectric layer on the second region, and the second opening exposes the second source-drain doped layers.

[0008] Optionally, it also includes: a second barrier layer located on the first gate structure, the second gate structure, the first dielectric layer and the first barrier layer; a second dielectric layer located on the second barrier layer; and the first opening and the second opening are also located in the second barrier layer and the second dielectric layer.

[0009] Optionally, the material of the first barrier layer includes silicon nitride; the material of the second barrier layer includes silicon nitride.

[0010] Optionally, the first gate structure has a third size along the first direction, and the second gate structure has a fourth size along the first direction, and the fourth size is smaller than the third size.

[0011] Optionally, it further includes: a conductive layer located in the first opening and the second opening.

[0012] Optionally, the material of the conductive layer includes metal, and the metal includes: cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; forming a plurality of first gate structures, a plurality of second gate structures, a plurality of first source-drain doped layers, a plurality of second source-drain doped layers and a first dielectric layer, the first gate structure spanning the first fins, adjacent first gate structures having a first size along the first direction, the second gate structure spanning the second fins, adjacent second gate structures having a second size along the first direction, the second size being smaller than the first size, the first source-drain doped layers being located in the first fins on both sides of the first gate structure, The second source-drain doped layer is located in the second fins on both sides of the second gate structure, the thickness of the second source-drain doped layer is greater than the thickness of the first source-drain doped layer, the first dielectric layer covers the sidewalls of the first gate structure and the second gate structure, and the top surface of the first dielectric layer located on the first region is lower than the top surface of the first dielectric layer located on the second region; a first barrier layer is formed on the surface of the first dielectric layer on the first region; the first dielectric layer and the first barrier layer are partially etched away, and a first opening is formed in the first barrier layer and the first dielectric layer on the first region, the first opening exposing the first source-drain doped layer, and a second opening is formed in the first dielectric layer located on the second region, the second opening exposing the second source-drain doped layer, and the etching rate of the first barrier layer is lower than the etching rate of the first dielectric layer.

[0014] Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a plurality of first dummy gate structures on the first region, the first dummy gate structures spanning the first fin; forming a plurality of second dummy gate structures on the second region, the second dummy gate structures spanning the second fin; the first dielectric layer covers the side walls of the first dummy gate structure and the second dummy gate structure.

[0015] Optionally, the method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first pseudo gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the second pseudo gate structure as a mask to form a plurality of second source-drain openings in the second fin; using an epitaxial growth process to simultaneously form an epitaxial layer in the first source-drain opening and the second source-drain opening until the epitaxial layer fills the second source-drain opening; in-situ doping the epitaxial layer during the epitaxial growth process to introduce source-drain ions into the epitaxial layer to form the first source-drain doped layer and the second source-drain doped layer.

[0016] Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure to form a first gate opening in the first dielectric layer; removing the second dummy gate structure to form a second gate opening in the first dielectric layer; forming the first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

[0017] Optionally, the method of forming the first gate structure in the first gate opening and forming the second gate structure in the second gate opening includes: forming a gate material layer in the first gate opening, in the second gate opening, and on the surface of the first dielectric layer; and flattening the gate material layer and the first dielectric layer to form the first gate structure and the second gate structure.

[0018] Optionally, the planarization process includes: a chemical mechanical polishing process.

[0019] Optionally, the chemical mechanical polishing process includes: performing a first chemical mechanical polishing treatment on the gate material layer until the top surface of the first dielectric layer is exposed, and the polishing rate of the gate material layer in the first chemical mechanical polishing treatment is greater than the polishing rate of the first dielectric layer; after the first chemical mechanical polishing treatment, performing a second chemical mechanical polishing treatment on the gate material layer and the first dielectric layer until the first gate structure and the second gate structure are polished to a preset height, and the polishing rate of the first dielectric layer in the second chemical mechanical polishing treatment is greater than the polishing rate of the gate material layer.

[0020] Optionally, the ratio of the polishing rate of the gate material layer by the first chemical mechanical polishing process to the polishing rate of the first dielectric layer by the first chemical mechanical polishing process is greater than 10:1; the ratio of the polishing rate of the first dielectric layer by the second chemical mechanical polishing process to the polishing rate of the gate material layer by the second chemical mechanical polishing process is greater than 1:1 and less than or equal to 10:1.

[0021] Optionally, the process of forming the first barrier layer on the surface of the first dielectric layer on the first region further includes: forming the first barrier layer on the surface of the first dielectric layer on the second region, and the thickness of the first barrier layer located on the first region is greater than the thickness of the first barrier layer located on the second region.

[0022] Optionally, after forming the first barrier layer, the method further includes: forming a second barrier layer on the first gate structure, the second gate structure, the first dielectric layer and the first barrier layer; forming a second dielectric layer on the second barrier layer; and the first opening and the second opening are also located in the second barrier layer and the second dielectric layer.

[0023] Optionally, the material of the first barrier layer includes silicon nitride; the material of the second barrier layer includes silicon nitride.

[0024] Optionally, the first gate structure has a third size along the first direction, and the second gate structure has a fourth size along the first direction, and the fourth size is smaller than the third size.

[0025] Optionally, after forming the first source-drain doped layer and the second source-drain doped layer, the method further includes: forming a conductive layer in the first opening and the second opening.

[0026] Optionally, the material of the conductive layer includes metal, and the metal includes: cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the structure of the technical solution of the present invention, a first barrier layer is formed, and the first barrier layer is located on the first dielectric layer above the first region. Because the etching rate of the first barrier layer is lower than the etching rate of the first dielectric layer, a certain amount of etching time is consumed by the first barrier layer during the formation of the first opening, thereby reducing the time required to finally etch the first source / drain doped layer. This prevents etching through the first source / drain doped layer, which would increase the contact resistance between the subsequently formed conductive layer and the first source / drain doped layer, thereby improving the performance of the ultimately formed semiconductor structure.

[0029] In the formation method of the technical solution of the present invention, a first barrier layer is formed on the surface of the first dielectric layer on the first region. Because the etching rate of the first barrier layer is lower than the etching rate of the first dielectric layer, a certain amount of etching time is consumed by the first barrier layer during the formation of the first opening, thereby reducing the time required to finally etch the first source / drain doped layer. This prevents etching through the first source / drain doped layer, which would increase the contact resistance between the subsequently formed conductive layer and the first source / drain doped layer, thereby improving the performance of the ultimately formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 2 It is a structural diagram of a semiconductor structure;

[0031] Figures 3 to 12It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, when long channel gate structures and short channel gate structures coexist in a semiconductor structure, other problems may arise, resulting in reduced performance of the resulting semiconductor structure.

[0033] Please refer to Figure 1 , providing a substrate 100, the substrate 100 including a first region I and a second region II, the first region I having a plurality of mutually separate first fins 101, the second region II having a plurality of mutually separate second fins 102, the first fins 101 and the second fins 102 respectively extending along a first direction X; forming a plurality of first gate structures 103, a plurality of second gate structures 104, a plurality of first source-drain doped layers 105, a plurality of second source-drain doped layers 110 and a first dielectric layer 106, the first gate structure 103 spanning the first fin 101, adjacent first gate structures 103 having a first dimension d1 along the first direction X, and the first gate structure 103 having a third dimension d3 along the first direction X; the second gate structure 104 spans the second fin 102, and adjacent second gate structures 104 have a second dimension d2 along the first direction X, and the second gate structure 104 has a fourth dimension d4 along the first direction X, the first dimension d1 is greater than the second dimension d2, and the third dimension d3 is greater than the fourth dimension d4; the first source-drain doped layer 105 is located in the first fin 101 on both sides of the first gate structure 103, and the second source-drain doped layer 110 is located in the second fin 102 on both sides of the second gate structure 104, and the thickness of the second source-drain doped layer 110 is greater than the thickness of the first source-drain doped layer 105; the first dielectric layer 106 covers the sidewalls of the first gate structure 103 and the second gate structure 104.

[0034] Please refer to Figure 2 A first barrier layer 107 is formed on the first dielectric layer 106; a portion of the first dielectric layer 106 and the first barrier layer 107 is removed by etching, and a first opening is formed in the first barrier layer 107 and the first dielectric layer 106 on the first region I, wherein the first opening exposes the source-drain doped layer 105 on the first region I; a second opening is formed in the first dielectric layer 106 located on the second region II, wherein the second opening exposes the second source-drain doped layer 110; a first conductive structure 108 is formed in the first opening; and a second conductive structure 109 is formed in the second opening.

[0035] In this embodiment, the third dimension d3 of the first gate structure 103 is increased in the first direction X, and the third dimension d3 is greater than 50 nm, thereby increasing the length of the channel.

[0036] However, when the third dimension d3 of the first gate structure 103 and the first dimension d1 between adjacent first gate structures 103 along the first direction X increase, the size of the first fins 101 exposed on both sides of the first gate structure junction 103 also increases. When the size of the exposed first fins 101 increases, the size of the subsequently formed first source / drain opening (not shown) also increases along the first direction X. Because the first source / drain doped layer 105 is formed by epitaxial growth on the first fins 101 exposed on the surface of the first source / drain opening, when the size of the first source / drain opening along the first direction X is large, when the second source / drain doped layer 110 fully grows within the second source / drain opening, the volume of the first source / drain doped layer 105 within the first source / drain opening in the second direction Y is smaller. The second direction Y is perpendicular to the first direction X, resulting in a depression in the center of the source / drain doped layer 105 within the first source / drain opening, thereby making the thickness of the second source / drain doped layer 110 greater than the thickness of the first source / drain doped layer 105.

[0037] When the source-drain doped layer 105 located at the first source-drain opening is recessed in the middle, the first source-drain doped layer 105 is easily etched through during the formation of the first conductive structure 108, thereby causing the bottom surface of the finally formed first conductive structure 108 to contact the first fin 101, thereby increasing the contact resistance between the first conductive structure 108 and the first source-drain doped layer 105, thereby affecting the performance of the finally formed semiconductor structure; if the etching time is reduced to avoid etching through the first source-drain doped layer 105, it is easy for the second opening to be etched insufficiently, and the second source-drain doped layer 110 cannot be exposed, thereby causing the second conductive structure 109 to be unable to contact the second source-drain doped layer 110, thereby affecting the performance of the finally formed semiconductor structure.

[0038] On this basis, the present invention provides a semiconductor structure and a method for forming the same, in which a first barrier layer is formed on the surface of a first dielectric layer on the first region. Because the etching rate of the first barrier layer is lower than the etching rate of the first dielectric layer, a certain amount of etching time is consumed by the first barrier layer during the formation of the first opening, thereby reducing the time required to finally etch the first source / drain doped layer. This prevents etching through the first source / drain doped layer, which would increase the contact resistance between the subsequently formed conductive layer and the first source / drain doped layer, thereby improving the performance of the ultimately formed semiconductor structure.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 3 to 12 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0041] Please refer to Figure 3 A substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II, wherein the first region I has a plurality of mutually separate first fins 201, and the second region II has a plurality of mutually separate second fins 202, and the first fins 201 and the second fins 202 extend along a first direction X respectively.

[0042] In this embodiment, the method for forming the substrate 200, the first fin 201 and the second fin 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, wherein the patterned layer exposes a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate 200, the first fin 201 and the second fin 202.

[0043] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0044] In this embodiment, the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] Please refer to Figure 4 , an isolation layer 203 is formed on the substrate 200 , wherein the isolation layer 203 covers part of the sidewalls of the first fin 201 and the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202 .

[0046] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing a portion of the initial isolation layer to form the isolation layer 203, wherein the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202.

[0047] The isolation layer 203 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 203 is made of silicon oxide.

[0048] After forming the isolation layer 203, it also includes: forming a plurality of first gate structures, a plurality of second gate structures, a plurality of first source-drain doped layers, a plurality of second source-drain doped layers and a first dielectric layer, wherein the first gate structure spans the first fin 201, and adjacent first gate structures have a first size along the first direction X, the second gate structure spans the second fin 202, and adjacent second gate structures have a second size along the first direction X, the second size is smaller than the first size, the first source-drain doped layer is located in the first fin 201 on both sides of the first gate structure, the second source-drain doped layer is located in the second fin 202 on both sides of the second gate structure, the thickness of the second source-drain doped layer is greater than the thickness of the first source-drain doped layer, the first dielectric layer covers the sidewalls of the first gate structure and the second gate structure, and the top surface of the first dielectric layer located on the first region I is lower than the top surface of the first dielectric layer located on the second region II. For the specific formation process, please refer to Figures 5 to 8 .

[0049] Please refer to Figure 5 , a plurality of first dummy gate structures 204 are formed on the first region I, and the first dummy gate structures 204 span the first fin 201; a plurality of second dummy gate structures 205 are formed on the second region II, and the second dummy gate structures 205 span the second fin 202.

[0050] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously using the same photomask. The first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0051] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 respectively include: a dummy gate dielectric layer and a dummy gate layer (not labeled) located on the dummy gate dielectric layer.

[0052] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0053] In this embodiment, the material of the dummy gate layer is polysilicon.

[0054] In this embodiment, please continue to refer to Figure 5 After forming the first dummy gate structure 204 and the second dummy gate structure 205 , it also includes: forming a first sidewall (not marked) on the sidewall of the first dummy gate structure 204 ; forming a second sidewall (not marked) on the sidewall of the second dummy gate structure 205 .

[0055] In this embodiment, the method for forming the first side wall and the second side wall includes: forming a side wall material layer (not shown) on the side walls and top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205, and the top surface of the isolation layer 203; and etching back the side wall material layer until the first dummy gate structure 204, the second dummy gate structure 205 and the top surface of the isolation layer 203 are exposed, thereby forming the first side wall and the second side wall.

[0056] In this embodiment, the spacer material layer is formed by an atomic layer deposition process.

[0057] In this embodiment, the first sidewall spacer and the second sidewall spacer are made of silicon nitride.

[0058] Please refer to Figure 6 The first fin 201 and the second fin 202 are etched using the first dummy gate structure 204 and the second dummy gate structure 205 as masks to form a plurality of first source-drain openings (not marked) in the first fin 201; a plurality of second source-drain openings (not marked) are formed in the second fin 202; the first source-drain doped layer 206 is formed in the first source-drain openings; and the second source-drain doped layer 207 is formed in the second source-drain openings.

[0059] In this embodiment, the method for forming the first source-drain doped layer 206 and the second source-drain doped layer 207 includes: using an epitaxial growth process to simultaneously form an epitaxial layer (not shown) in the first source-drain opening and the second source-drain opening until the epitaxial layer fills the second source-drain opening; in-situ doping the epitaxial layer during the epitaxial growth process, and introducing source and drain ions into the epitaxial layer to form the first source-drain doped layer 206 and the second source-drain doped layer 207.

[0060] In this embodiment, the first region I is used to form a long-channel transistor structure, and the second region II is used to form a short-channel transistor structure. The size of the first source and drain openings in the long-channel transistor structure is larger than the size of the second source and drain openings in the short-channel transistor structure. Because the first source and drain doping layer 206 and the second source and drain doping layer 207 are formed simultaneously using an epitaxial growth process, and the epitaxial layer is grown until the second source and drain openings are completely filled, the thickness of the finally formed second source and drain doping layer 207 is greater than the thickness of the first source and drain doping layer 206, and the thickness direction is perpendicular to the substrate surface.

[0061] Please refer to Figure 7, a first dielectric layer 208 is formed on the substrate 200 , and the first dielectric layer 208 covers the sidewalls of the first dummy gate structure 204 and the second dummy gate structure 205 .

[0062] In this embodiment, the method for forming the first dielectric layer 208 includes: forming an initial dielectric layer (not shown) on the substrate 200, the initial dielectric layer covering the first source-drain doped layer 206, the second source-drain doped layer 207, the first dummy gate structure 204 and the second dummy gate structure 205; and planarizing the initial dielectric layer until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, thereby forming the first dielectric layer 208.

[0063] In this embodiment, the material of the first dielectric layer 208 is silicon oxide; in other embodiments, the material of the first dielectric layer may also be a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0064] Please refer to Figure 8 , remove the first dummy gate structure 204, and form a first gate opening (not labeled) in the first dielectric layer 208; remove the second dummy gate structure 205, and form a second gate opening (not labeled) in the first dielectric layer 208; form the first gate structure 209 in the first gate opening; and form the second gate structure 210 in the second gate opening.

[0065] In this embodiment, since the first region I is used to form a long channel transistor structure and the second region II is used to form a short channel transistor structure, the first gate structure 209 has a third dimension d3 along the first direction X, and the second gate structure 205 has a fourth dimension d4 along the first direction X, and the fourth dimension d4 is smaller than the third dimension d3; adjacent first gate structures 209 have a first dimension d1 along the first direction X, and adjacent second gate structures 210 have a second dimension d2 along the first direction X, and the second dimension d2 is smaller than the first dimension d1.

[0066] In this embodiment, the method of forming the first gate structure 209 in the first gate opening and the method of forming the second gate structure 210 in the second gate opening include: forming a gate material layer (not shown) in the first gate opening, in the second gate opening, and on the surface of the first dielectric layer 208; and planarizing the gate material layer and the first dielectric layer 208 to form the first gate structure 209 and the second gate structure 210.

[0067] In this embodiment, the planarization process adopts a chemical mechanical polishing process; the method of the chemical mechanical polishing process includes: performing a first chemical mechanical polishing process on the gate material layer until the top surface of the first dielectric layer 208 is exposed, and the polishing rate of the gate material layer in the first chemical mechanical polishing process is greater than the polishing rate of the first dielectric layer 208; after the first chemical mechanical polishing process, performing a second chemical mechanical polishing process on the gate material layer and the first dielectric layer 208 until the first gate structure 209 and the second gate structure 210 are polished to a preset height, and the polishing rate of the first dielectric layer 208 in the second chemical mechanical polishing process is greater than the polishing rate of the gate material layer.

[0068] In this embodiment, the ratio of the polishing rate of the gate material layer by the first chemical mechanical polishing process to the polishing rate of the first dielectric layer by the first chemical mechanical polishing process is greater than 10:1; the ratio of the polishing rate of the first dielectric layer by the second chemical mechanical polishing process to the polishing rate of the gate material layer by the second chemical mechanical polishing process is greater than 1:1 and less than or equal to 10:1.

[0069] Because the second dimension d2 is smaller than the first dimension d1, the size of the first dielectric layer 208 deposited between adjacent first gate structures 209 is larger than the size of the first dielectric layer 208 deposited between adjacent second gate structures 210 in the first direction X. Accordingly, the chemical mechanical polishing process results in a larger contact surface with the first dielectric layer 208 located in the first region I, and thus, the chemical mechanical polishing process produces a more pronounced deformation effect on the first dielectric layer 208 in the first region I. Therefore, during the chemical mechanical polishing process, the polishing rates of the first dielectric layer 208 and the gate material layer are specifically adjusted, so that the top surface of the first dielectric layer 208 located in the first region I is ultimately lower than the top surface of the first dielectric layer 208 located in the second region II.

[0070] Please refer to Figure 9 , a first blocking layer 211 is formed on the surface of the first dielectric layer 208 on the first region I.

[0071] In this embodiment, the first barrier layer 211 is formed only on the surface of the first dielectric layer 208 in the first region I, and is not formed on the surface of the first dielectric layer 208 in the second region II. In other embodiments, during the process of forming the first barrier layer on the surface of the first dielectric layer in the first region, the first barrier layer may also be formed on the surface of the first dielectric layer in the second region, and the thickness of the first barrier layer in the first region is greater than the thickness of the first barrier layer in the second region.

[0072] In this embodiment, the method for forming the first blocking layer 211 includes: forming a blocking material layer (not shown) on the first dielectric layer 208, the first gate structure 209 and the second gate structure 210; and planarizing the blocking material layer until the top surfaces of the first gate structure 209 and the second gate structure 210 are exposed to form the first blocking layer 211.

[0073] In this embodiment, the first barrier layer 211 is made of silicon nitride.

[0074] Please refer to Figure 10 After forming the first barrier layer 211 , a second barrier layer 212 is formed on the first gate structure 209 , the second gate structure 210 , the first dielectric layer 208 and the first barrier layer 211 ; and a second dielectric layer 213 is formed on the second barrier layer 212 .

[0075] In this embodiment, the second barrier layer 212 is made of silicon nitride.

[0076] In this embodiment, the material of the second dielectric layer 213 is silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0077] Please refer to Figure 11 , partially etching away the first dielectric layer 208 and the first barrier layer 211, forming a first opening 214 in the first dielectric layer 208 on the first barrier layer 211 and the first region I, the first opening 214 exposing the first source-drain doped layer 206, and forming a second opening 215 in the first dielectric layer 208 located on the second region II, the second opening 215 exposing the second source-drain doped layer 207, the etching rate of the first barrier layer 211 being lower than the etching rate of the first dielectric layer 208.

[0078] In this embodiment, a first barrier layer 211 is formed on the surface of the first dielectric layer 208 on the first region I. Since the etching rate of the first barrier layer 211 is lower than that of the first dielectric layer 208, a certain etching time is consumed by the first barrier layer 211 during the formation of the first opening 214, thereby reducing the time required for the final etching of the first source / drain doped layer 206. This prevents the etching from penetrating the first source / drain doped layer 206, which would increase the contact resistance between the subsequently formed conductive layer and the first source / drain doped layer 206, thereby improving the performance of the final semiconductor structure.

[0079] In this embodiment, the first opening 214 and the second opening 215 are also located in the second barrier layer 212 and the second dielectric layer 213 .

[0080] Please refer to Figure 12 A conductive layer 216 is formed in the first opening 214 and the second opening 215 .

[0081] In this embodiment, the method for forming the conductive layer 216 includes: forming a conductive material layer (not shown) within the first opening 214, within the second opening 215, and on the surface of the second dielectric layer 213; and planarizing the conductive material layer until the top surface of the second dielectric layer 213 is exposed, thereby forming the conductive layer 216.

[0082] The conductive layer 216 is made of metal, including cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the conductive layer 216 is made of cobalt.

[0083] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please refer to Figure 12, comprising: a substrate 200, the substrate 200 comprising a first region I and a second region II, the first region I having a plurality of mutually separate first fins 201, the second region II having a plurality of mutually separate second fins 202, the first fins 201 and the second fins 202 respectively extending along a first direction X; a plurality of first gate structures 209, a plurality of second gate structures 210, a plurality of first source-drain doped layers 206, a plurality of second source-drain doped layers 207 and a first dielectric layer 208, the first gate structure 209 spanning the first fins 201, a first dimension d1 being defined between adjacent first gate structures 209 along the first direction X, the second gate structure 210 spanning the second fins 202, a second dimension d2 being defined between adjacent second gate structures 210 along the first direction X, the second dimension d2 being smaller than the first dimension d1, the first source-drain doped layers 206 being located in the first fins 201 on both sides of the first gate structure 209, Second source-drain doped layers 207 are located within the second fins 202 on both sides of the second gate structure 210. The thickness h1 of the second source-drain doped layers 207 is greater than the thickness h1 of the first source-drain doped layers 206. The first dielectric layer 208 covers the sidewalls of the first gate structure 209 and the second gate structure 210, and the top surface of the first dielectric layer 208 located on the first region I is lower than the top surface of the first dielectric layer 208 located on the second region II. A first barrier layer 211 is located on the first dielectric layer 208 located on the first region I. A first opening 214 and a second opening 215 are provided. The first opening 214 is located within the first barrier layer 211 and the first dielectric layer 208 located on the first region I, exposing the first source-drain doped layer 206. The second opening 215 is located within the first dielectric layer 208 located on the second region II, exposing the second source-drain doped layer 207.

[0084] In this embodiment, a first barrier layer 211 is formed, and the first barrier layer 211 is located on the first dielectric layer 208 on the first region I. Since the etching rate of the first barrier layer 211 is lower than the etching rate of the first dielectric layer 208, during the process of forming the first opening 214, a certain etching time is consumed by the first barrier layer 211, so that the time for finally etching the first source-drain doped layer 206 is reduced, thereby preventing the etching from penetrating the first source-drain doped layer 206 and increasing the contact resistance between the subsequently formed conductive layer 216 and the first source-drain doped layer 206, thereby improving the performance of the finally formed semiconductor structure.

[0085] In this embodiment, it also includes: a second barrier layer 212 located on the first gate structure 209, the second gate structure 210, the first dielectric layer 208 and the first barrier layer 211; a second dielectric layer 213 located on the second barrier layer 212; and the first opening 214 and the second opening 215 are also located in the second barrier layer 212 and the second dielectric layer 213.

[0086] In this embodiment, the first barrier layer 211 is made of silicon nitride.

[0087] In this embodiment, the second barrier layer 212 is made of silicon nitride.

[0088] In this embodiment, the first gate structure 209 has a third dimension d3 along the first direction X, and the second gate structure 210 has a fourth dimension d4 along the first direction X. The fourth dimension d4 is smaller than the third dimension d3.

[0089] In this embodiment, the present invention further includes a conductive layer 216 located in the first opening 214 and the second opening 215 .

[0090] The conductive layer 216 is made of metal, including cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the conductive layer 216 is made of cobalt.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region and a second region, wherein the first region has a plurality of mutually separate first fins, and the second region has a plurality of mutually separate second fins, wherein the first fins and the second fins extend along a first direction respectively; a plurality of first gate structures, a plurality of second gate structures, a plurality of first source-drain doped layers, a plurality of second source-drain doped layers, and a first dielectric layer, wherein the first gate structure spans the first fin, and adjacent first gate structures have a first dimension along the first direction; the second gate structure spans the second fin, and adjacent second gate structures have a second dimension along the first direction, the second dimension being smaller than the first dimension; the first source-drain doped layers are located in the first fins on both sides of the first gate structure; the second source-drain doped layers are located in the second fins on both sides of the second gate structure; the thickness of the second source-drain doped layers is greater than the thickness of the first source-drain doped layers; the first dielectric layer covers sidewalls of the first gate structure and the second gate structure, and a top surface of the first dielectric layer located on the first region is lower than a top surface of the first dielectric layer located on the second region; a first barrier layer, the first barrier layer being located on the first dielectric layer on the first region; A first opening and a second opening, wherein the first opening is located in the first dielectric layer on the first barrier layer and the first region, and the first opening exposes the first source-drain doped layer; and the second opening is located in the first dielectric layer on the second region, and the second opening exposes the second source-drain doped layer; wherein The first opening is formed by etching away a portion of the first dielectric layer and the first barrier layer, and the second opening is formed by etching away a portion of the first dielectric layer. The etching rate of the first barrier layer is lower than the etching rate of the first dielectric layer.

2. The semiconductor structure according to claim 1, wherein Also includes: a second barrier layer located on the first gate structure, the second gate structure, the first dielectric layer and the first barrier layer; a second dielectric layer located on the second barrier layer; The first opening and the second opening are also located in the second barrier layer and the second dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The material of the first barrier layer includes silicon nitride; the material of the second barrier layer includes silicon nitride.

4. The semiconductor structure according to claim 1, wherein: The first gate structure has a third size along the first direction, and the second gate structure has a fourth size along the first direction, wherein the fourth size is smaller than the third size.

5. The semiconductor structure according to claim 1, wherein Also includes: A conductive layer is located in the first opening and the second opening.

6. The semiconductor structure according to claim 5, wherein: The conductive layer is made of metal, including cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; forming a plurality of first gate structures, a plurality of second gate structures, a plurality of first source-drain doped layers, a plurality of second source-drain doped layers, and a first dielectric layer, wherein the first gate structure spans the first fin, and adjacent first gate structures have a first dimension along the first direction; the second gate structure spans the second fin, and adjacent second gate structures have a second dimension along the first direction, the second dimension being smaller than the first dimension; the first source-drain doped layers are located in the first fins on both sides of the first gate structure; the second source-drain doped layers are located in the second fins on both sides of the second gate structure; the thickness of the second source-drain doped layers is greater than the thickness of the first source-drain doped layers; the first dielectric layer covers sidewalls of the first gate structure and the second gate structure, and a top surface of the first dielectric layer located on the first region is lower than a top surface of the first dielectric layer located on the second region; forming a first barrier layer on the surface of the first dielectric layer on the first region; Part of the first dielectric layer and the first barrier layer is etched away to form a first opening in the first dielectric layer above the first barrier layer and the first region, wherein the first opening exposes the first source / drain doped layer; a second opening is formed in the first dielectric layer above the second region, wherein the second opening exposes the second source / drain doped layer, wherein the etching rate of the first barrier layer is less than the etching rate of the first dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the first gate structure and the second gate structure, the method further includes: forming a plurality of first dummy gate structures on the first region, wherein the first dummy gate structures span the first fin; forming a plurality of second dummy gate structures on the second region, wherein the second dummy gate structures span the second fin; and the first dielectric layer covers the sidewalls of the first dummy gate structure and the second dummy gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first pseudo gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the second pseudo gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming an epitaxial layer in the first source-drain opening and the second source-drain opening simultaneously using an epitaxial growth process until the epitaxial layer fills the second source-drain opening; in-situ doping the epitaxial layer during the epitaxial growth process to dope source-drain ions into the epitaxial layer to form the first source-drain doped layer and the second source-drain doped layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure to form a first gate opening in the first dielectric layer; removing the second dummy gate structure to form a second gate opening in the first dielectric layer; forming the first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method of forming the first gate structure in the first gate opening and forming the second gate structure in the second gate opening includes: forming a gate material layer in the first gate opening, in the second gate opening, and on the surface of the first dielectric layer; and flattening the gate material layer and the first dielectric layer to form the first gate structure and the second gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The planarization process includes a chemical mechanical polishing process.

13. The method for forming a semiconductor structure according to claim 12, wherein: The chemical mechanical polishing process method includes: performing a first chemical mechanical polishing treatment on the gate material layer until the top surface of the first dielectric layer is exposed, and the polishing rate of the gate material layer in the first chemical mechanical polishing treatment is greater than the polishing rate of the first dielectric layer; after the first chemical mechanical polishing treatment, performing a second chemical mechanical polishing treatment on the gate material layer and the first dielectric layer until the first gate structure and the second gate structure are polished to a preset height, and the polishing rate of the first dielectric layer in the second chemical mechanical polishing treatment is greater than the polishing rate of the gate material layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: A ratio of a polishing rate of the gate material layer by the first chemical mechanical polishing process to a polishing rate of the first dielectric layer by the first chemical mechanical polishing process is greater than 10:1; A ratio of a polishing rate of the first dielectric layer by the second chemical mechanical polishing process to a polishing rate of the gate material layer by the second chemical mechanical polishing process is greater than 1:1 and less than or equal to 10:

1.

15. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the first barrier layer on the surface of the first dielectric layer on the first region also includes: forming the first barrier layer on the surface of the first dielectric layer on the second region, wherein the thickness of the first barrier layer on the first region is greater than the thickness of the first barrier layer on the second region.

16. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first barrier layer, the method further includes: forming a second barrier layer on the first gate structure, the second gate structure, the first dielectric layer and the first barrier layer; forming a second dielectric layer on the second barrier layer; and the first opening and the second opening are also located in the second barrier layer and the second dielectric layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the first barrier layer includes silicon nitride; the material of the second barrier layer includes silicon nitride.

18. The method for forming a semiconductor structure according to claim 7, wherein: The first gate structure has a third size along the first direction, and the second gate structure has a fourth size along the first direction, wherein the fourth size is smaller than the third size.

19. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first source-drain doped layer and the second source-drain doped layer, the method further includes: forming a conductive layer in the first opening and the second opening.

20. The method for forming a semiconductor structure according to claim 19, wherein: The conductive layer is made of metal, including cobalt, rubidium, tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

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