Data migration technology

Abstract

The present application relates to data migration techniques. A memory system may receive a command associated with a write operation from a host device. The memory system may determine whether to write data to the memory device using a data migration technique based on receiving the command. In some cases, the memory system may select a tertiary write format instead of a quaternary write format to write the data, and write the data using the tertiary write format. The memory system may convert the data from the tertiary write format to the quaternary write format based on writing the data using the tertiary write format.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 139,418, filed on January 20, 2021 by Tanpairoj et al., entitled “DATA MIGRATION TECHNIQUES,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to data migration technology. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states that often correspond to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, and the memory cell can store any of the more than two possible states. In order to access information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) can lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include a memory device and a control circuit coupled to the memory device. The control circuit may be configured to cause the apparatus to perform the following operations: receive a command associated with a write operation from a host device; determine whether to write data to the memory device using a data migration technique based at least in part on receiving the command; select a tertiary write format instead of a quaternary write format to write the data based at least in part on determining to use the data migration technique; write the data to the memory device using the tertiary write format based at least in part on selecting the tertiary write format; and convert the data from the tertiary write format to the quaternary write format based at least in part on writing the data.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a command associated with a write operation from a host device; determine whether to write data to a memory device using a data migration technique based at least in part on receiving the command; select a tertiary write format over a quaternary write format to write the data based at least in part on determining to use the data migration technique; write the data to the memory device using the tertiary write format based at least in part on selecting the tertiary write format; and convert the data from the tertiary write format to the quaternary write format based at least in part on writing the data.

[0008] A method is described. The method may include receiving a command associated with a write operation from a host device; determining whether to write data to a memory device using a data migration technique based at least in part on receiving the command; selecting a tertiary write format over a quaternary write format to write the data based at least in part on determining to use the data migration technique; writing the data to the memory device using the tertiary write format based at least in part on selecting the tertiary write format; and converting the data from the tertiary write format to the quaternary write format based at least in part on writing the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting data migration techniques according to examples disclosed herein is shown.

[0010] Figure 2 A process of supporting data migration technology according to examples disclosed herein is shown.

[0011] Figure 3 A process of supporting data migration technology according to examples disclosed herein is shown.

[0012] Figure 4 A block diagram illustrating a memory system supporting data migration techniques according to examples disclosed herein.

[0013] Figure 5 A flow chart illustrating one or more methods of supporting data migration techniques according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some memory systems may be used or may need to perform a relatively large data transfer from a first memory system (which may include a first memory device) to a second memory system (which may include a second memory device). For example, the first memory system (which may include a first memory device) may include existing data that may need to be transferred to the second memory system (which may include a second memory device). The relatively large data transfer may be an example of an initial data transfer, such as transferring existing data from a first device (e.g., an older electronic device that may include the first memory system, such as a smartphone) to a second device (e.g., a newer electronic device that may include the second memory system, such as a smartphone). In some examples, the amount of space available in the cache of the second memory system may be less than the amount (e.g., size) of data to be transferred. In such cases, use of the cache during the data transfer may be unavailable or ineffective because the cache cannot store all of the data to be transferred.

[0015] In some instances, writing directly to transfer data using some more complex data migration techniques (e.g., quad-level cell (QLC) data migration techniques) may be slower than other less complex data migration techniques (e.g., triple-level cell (TLC) data migration techniques). In such cases, using more complex data migration techniques (e.g., QLC) may cause the memory device to experience disadvantages such as longer programming times, longer transfer times, and longer processing times. In addition, such techniques may cause the memory system to experience performance losses when performing memory device operations, such as performing relatively large data transfers from a first memory system to a second memory system, which may increase latency for other operations. By using more complex data migration techniques, such as QLC data migration techniques, the amount of power used by the memory system may also increase, thereby reducing the overall performance of the memory system. The present disclosure describes alternative techniques for migrating data without compromising memory device performance and avoiding some of the disadvantages that may exist when using more complex data migration techniques.

[0016] Aspects of the present disclosure address the above and other deficiencies by having a memory system that performs efficient and effective data migration techniques. The memory system may receive a command from a host system, such as a command associated with a write operation. In some instances, the memory system may determine whether to write data to a memory system, such as a memory device (e.g., a memory device included as part of the memory system) using a data migration technique. For example, the memory system may detect a data transfer request based on a command, and determine that the data transfer may be a single data transfer from a first memory system to a second memory system based on the size of the data, the continuity of the data, the space available for writing in the memory device, or the completion of a production operation, one or more other factors, or any combination thereof. In some instances, the second memory system may select a first write format, such as a tertiary write format (e.g., a TLC write format) for writing data, and the second memory system may write data to a second memory device of the second memory system using the tertiary write format. For example, the tertiary write format may be used as a transition format to move existing data (e.g., from a first memory device) to a second memory system (e.g., a second memory device of the second memory system). Then, after writing the data to the tertiary write format in a second memory system (e.g., a second memory device), the memory system may migrate (e.g., convert) the data from one format to another, for example, from the tertiary write format to a quaternary write format (e.g., a QLC write format).

[0017] By using the data migration techniques described herein, data migration performance can be improved by using data transfers that implement solutions related to writing in different write formats, thereby improving the overall performance of the memory system, thereby improving the user experience of the second memory system (e.g., including the second memory device). For example, the data migration techniques can improve the memory system performance during initial data transfers and the overall efficiency of the memory system without allocating a large dedicated cache to support data migration. In such cases, the memory system can reduce the delay between the transmission of one or more commands and writing to one or more memory devices, can increase read, write, and erase speeds, and can improve processing time, among other advantages.

[0018] The features of the present disclosure are initially described in reference Figure 1 The features of the present disclosure are described in the context of the system described. Figure 2-3 These and other features of the present disclosure are further described by reference to Figure 4-5 The described equipment diagrams and flow charts related to the data migration technology are illustrated and described with reference to these diagrams.

[0019] Figure 1An example of a system 100 that supports data migration techniques according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0021] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0022] The system 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, such coupling may include a connection to a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown, but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130 (e.g., memory device 130-a, memory device 130-b). The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 1, two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, where the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface), and may be an example of a control component configured to cause the memory system 110 to perform various operations according to examples as described herein. The memory system controller 115 may also be coupled and communicated with the memory devices 130 to perform operations that may generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or updating data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. And in some cases, the memory system controller 115 may exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses (eg, data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105 .

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when reading from or writing to the memory device 130, and may be available within the local memory 120 for subsequent retrieval or manipulation (update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in FIG. 1 has been shown as including a memory system controller 115, but in some cases the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 (e.g., local controller 135-a, local controller 135-b), which may be respectively internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations separately on one or more memory cells of memory device 130. Local controller 135 (e.g., local controller 135-a, local controller 135-b) may operate in conjunction with memory system controller 115 or may perform one or more functions attributed to memory system controller 115 herein.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a TLC if configured to store three bits of information each, a QLC if configured to store four bits of information each, or more generally a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as the same operation being performed on memory cells within different pages 175 having the same page address within a respective plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but may be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that may be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that may be independently erased (e.g., erased simultaneously as part of a single erasing operation). Additionally, in some cases, a NAND memory cell may be erased before it may be overwritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0037] The system 100 may include any number of non-transitory computer-readable media that support data migration techniques. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0038] Each memory cell of the NAND memory device 130 is programmable to store one or more logical values ​​representing one or more bits of information. In some cases, a single memory cell (e.g., an SLC memory cell) is programmable to one of two supported states and can therefore store one bit of information (e.g., a logical 0 or a logical 1) at a time. In other cases, a single memory cell (e.g., an MLC, TLC, QLC, or other type of multi-level memory cell) is programmable to one of more than two supported states and can therefore store more than one bit of information. In some examples, a single MLC memory cell is programmable to one of four supported states and can therefore store two bits of information corresponding to one of four logical values ​​(e.g., logical 00, logical 01, logical 10, or logical 11) at a time. In some examples, a single TLC memory cell is programmable to one of eight supported states and can therefore store three bits of information corresponding to one of eight logical values ​​(e.g., 000, 001, 010, 011, 100, 101, 110, or 111) at a time. In some examples, a single QLC memory cell is programmable to one of sixteen supported states and can therefore store four bits of information corresponding to one of sixteen logical values ​​(eg, 0000, 0001, ..., 1111) at a time.

[0039] In some cases, a multi-level memory cell (e.g., an MLC memory cell, a TLC memory cell, or a QLC memory cell) may be physically different from an SLC cell. For example, the multi-level memory cell may be manufactured using a different cell geometry or may be manufactured using different materials. In some cases, the multi-level memory cell may be physically the same or similar to an SLC cell, and other circuitry in the memory block (e.g., a controller, a sense amplifier, a driver) may be configured to operate (e.g., read and program) the memory cell as an SLC cell, or an MLC cell, or a TLC cell, or a QLC, etc.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] In some examples, the memory system 110 may receive a command, such as a write command, from the host system 105. The memory system 110 may determine whether to write data to the memory device 130 using a data migration technique. In some cases, the memory system 110 may select a TLC write format to write the data. For example, the memory system 110 may select a TLC write format instead of selecting a QLC write format. The memory system 110 may write the data to the memory device 130 using a TLC write format based on the selection. In some examples, the memory device 130 may be configured to write data in a TLC write format and a QLC write format. The memory device 130 may be an example of a wireless device such as a tablet computer, a cellular phone, a notebook computer, or other similar devices or a spatially distributed memory device network that is configured to receive a signal and transfer data (e.g., a relatively large data block, such as 64 gigabytes of data) from a first memory device (e.g., an old device) to a second memory device (e.g., a new device). After writing the data in the TLC write format, the memory system 110 may migrate (e.g., convert) the data written in the TLC write format to the QLC write format.

[0042] The memory system 110 may determine whether to use a data migration technique (e.g., from a possibly different option of a data writing format technique) by determining whether the production operation is complete and / or determining whether the amount of space available for writing exceeds a threshold. In some instances, the memory system 110 may determine whether to use a data migration technique by determining whether the data is sequential data and / or determining whether the size of the data exceeds a threshold. In some cases, the memory system 110 may determine to use a data migration technique if the memory system 110 determines that the production operation is complete, the amount of space available in the second memory system (e.g., the second memory device) is equal to or greater than a threshold, the data is sequential data, and / or the size of the data exceeds a threshold.

[0043] Figure 2A process 200 is shown for supporting data migration techniques according to examples disclosed herein. Aspects of process 200 may be implemented by a controller and other example components. Additionally or alternatively, aspects of process 200 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform operations of process 200.

[0044] In some cases, a user of a first memory system (or a memory device itself that operates autonomously based on a program or instruction) may request that data be transferred from the first memory system to a second memory system. However, the amount of data to be transferred to the second memory system (e.g., to the second memory device) may exceed a threshold, thereby increasing programming time and increasing power consumption of the second memory system (e.g., the second memory device), among other disadvantages. In other instances, the cache of the second memory system may not be able to store the transferred data due to size limitations (e.g., the available space in the cache may be less than the amount of data to be transferred). In other instances, the data may be able to be written directly to one memory device, such as a TLC main storage area or a single main storage area of ​​the second memory device, in a TLC write format, and may require a technique to write the data to another memory device (e.g., a QLC main storage area) or to the same memory device but using a QLC write format. However, the process of writing to a QLC main storage area or writing in a QLC write format may perform write operations with a longer duration (relative to writing in other non-QLC write formats) because the QLCs each include four levels. In such cases, the placement of electrons within the four levels may be performed with greater precision to obtain the four levels, thereby increasing programming time to ensure precise placement and increased control.

[0045] Instead of writing directly to the QLC main storage area, or instead of writing directly using the QLC write format, the memory system may use a data migration technique (e.g., a first data migration technique) that writes data using a tertiary (e.g., TLC) write format and converts the tertiary write format to a quaternary (e.g., QLC) write format after writing the data using the tertiary write format. The memory system may determine when to use this data migration technique, as described with reference to process 200, among other things. The data migration technique may allow the memory system to detect a data migration request and transfer a large amount of data from a first memory device to a second memory device.

[0046] At 205, a host command may be received. For example, a memory system (e.g., memory system 110) may receive a command associated with a write operation from a host system (e.g., host system 105) and / or another memory system. In such cases, memory system 110 may determine whether to write data to a memory device (e.g., memory device 130-a, memory device 130-b) using a data migration technique based on receiving the command. Determining whether to write data to a memory device using a data migration technique based on receiving the command may be based on one or more factors, conditions, determinations, other aspects, or any combination thereof.

[0047] At 210, it may be determined whether a production status awareness (PSA) operation is complete. For example, the memory system may determine whether a production operation (also referred to as a PSA operation) is complete based on receiving a command, based on one or more flags, based on an amount of space used in performing the PSA operation, or based on an amount of space available for writing in a memory device, or any combination thereof, as well as other factors. In such cases, determining whether to use a data migration technique may be based on determining whether the production operation is complete.

[0048] A production operation may be an instance of an operation in which a host system may write one or more operating system (OS) parameters to a memory device (e.g., memory device 130), among other aspects. For example, the host system may set a flag to indicate that the operation is a production operation, and the memory system may detect the production operation and / or determine the completion of the production operation based on the set flag. After the production operation, a related reflow operation may occur, and the memory device may be refreshed (e.g., power off / on). In some instances, the data written to the memory device for the production operation may be relatively smaller than the data written to the memory device outside of the production operation (e.g., during data migration). In some cases, the production operation may include a high temperature distribution. In such cases, the data may be routed to the SLC cache area before the production operation, and / or the data may be rerouted back to the memory device after the production operation is completed.

[0049] If it is determined at 210 that the production operation is not completed or in progress, process 200 may proceed to 230. For example, the memory system may determine that the production operation is not completed. The memory system may prevent interruption of the production operation for performing data migration by continuing to 230 instead of using the data migration technique. At 230, the memory system may write data to the memory device using a second data migration technique based on determining that the production operation is not completed. For example, the memory system may avoid using a data migration technique (e.g., using a first write format such as TLC and then migrating the data to a second write format such as QLC) to write data to the memory device based on determining that the production operation is not completed. The second data migration technique may be, for example, an implementation of a cache algorithm.

[0050] In some cases, if it is determined at 210 that the production operation is not completed or in progress, the memory system may write data to the memory device using a third data migration technique based on determining that the production operation is not completed. The third data migration technique may include, for example, an implementation of an SLC mode using a fine-tuning setting. The SLC mode may be an instance of using an SLC write format. In such an instance, the SLC mode may be an instance of programming a single memory cell (e.g., an SLC memory cell) to one of a plurality of support states (e.g., two support states) and storing one information bit (e.g., a logical 0 or a logical 1) at a time. In such a case, the memory system may avoid using a data migration technique (e.g., using a first write format such as TLC and then migrating the data to a second write format such as QLC) to write data to the memory device based on using the third data migration technique. In some instances, the fine-tuning setting may relate to data retention during a reflow operation associated with the production operation and the high temperature profile.

[0051] If it is determined at 210 that the production operation is not completed or in progress, the memory system may write data to the memory device using a fourth data migration technique based on determining that the production operation is not completed. For example, the fourth data migration technique may include, for example, an implementation of an SLC mode using a fine-tuning setting different from the fine-tuning setting associated with the third data migration technique. The fine-tuning setting may be related to high performance (e.g., improvement in performance) of the memory device. For example, the third data migration technique may improve memory system performance during initial data transfer and the overall efficiency of the memory system without allocating a larger dedicated cache to support data migration. If the memory device includes NAND, the fine-tuning setting may be an example of a NAND fine-tuning setting. When this fine-tuning setting is used as part of writing data, the setting tolerances (e.g., thresholds) between different levels (e.g., different SLC levels) may be more relaxed to allow for increased speed and efficiency relative to other write operations (including operations that may also be performed when writing data without the fine-tuning setting).

[0052] If it is determined at 210 that the production operation is complete, process 200 may proceed to 215. For example, the memory system may determine that the production operation is complete based on receiving a command, based on one or more flags, based on an amount of space used in performing a PSA operation, or based on an amount of space available for writing in a memory device, or any combination thereof, among other factors. The memory system may determine to use a data migration technique based at least in part on determining that the production operation is complete.

[0053] At 215, it may be determined whether there is space available for writing. For example, the memory system may determine whether an amount of space available (e.g., in a memory device) is equal to or greater than (e.g., exceeds) a threshold value based on determining that the production operation is complete. In such cases, when determining whether the amount of space available is equal to or greater than the threshold value, the memory system may check the logical availability of the memory system (including but not limited to the memory device). In some cases, determining whether to use the data migration technique is based on determining whether the amount of space available for writing is equal to or exceeds the threshold value. In some cases, the amount of space available for writing may include space available for writing 64 gigabytes of data.

[0054] If the amount of space available for writing is less than the threshold, process 200 may proceed to 230. For example, the memory system may determine that the amount of space available for writing (e.g., for data to be transferred) is below a threshold. In some cases, the memory system may determine that there is no amount of space available for writing or very little amount of space available for writing (e.g., the memory device is full or nearly full). At 230, the memory system may write data to the memory device using a second data migration technique (rather than using the first data migration technique) based on determining that the amount of space available is below the threshold. For example, the memory system may avoid using a first data migration technique (e.g., using a first write format such as TLC and then migrating the data to a second write format such as QLC) to write data to the memory device based on determining that the amount of space available is below the threshold.

[0055] In one example, the threshold may be approximately 30-40% of unavailable space. For example, if the memory system determines that more than 30-40% of the memory device is full or in use (e.g., unavailable space) due to previously written information, the memory system may use the second data migration technique (rather than using the first data migration technique) to write data to the memory device. In such a case, the memory system may determine that the memory device contains less than 60-70% of space available for writing.

[0056] In some cases, based on the conversion of QLC space to TLC space, the amount of QLC space may be less than the amount of TLC space (e.g., because writing data in the QLC format may require relatively less space than writing data in the TLC format, since the QLC format includes a maximum of four bits per cell, while the TLC format includes a maximum of three bits per cell). In such cases, the memory system may determine the amount of space available to write to the memory device before writing the data using the data migration technique. For example, the memory system may determine that the amount of space available for writing on the second memory device (e.g., memory device 130-b) may be less than the amount of space available for writing on the first memory device (e.g., memory device 130-a). The memory system may avoid writing the data to the second memory device using the data migration technique, and instead write the data to the second memory device using the second data migration technique.

[0057] If the amount of space available for writing is equal to or greater than the threshold, process 200 may proceed to 220. For example, the memory system may determine that the amount of space available for writing is equal to or greater than the threshold. In some examples, the memory system may determine that the memory device is empty or that a portion of the memory device (e.g., sufficient to write data) is empty. In such cases, the memory system may determine to use a data migration technique based on determining that the amount of space available is equal to or greater than the threshold.

[0058] For example, if the memory system determines that less than 30-40% of the memory device is full or in use (e.g., unavailable space), the memory system may use data migration techniques to write data to the memory device. In such cases, the memory system may determine that the memory device contains more than 60-70% of the space available for writing. In other instances, the memory system may determine that the amount of space available for writing on the second memory device is equal to the amount of space written on the first memory device. In such cases, the memory system may use data migration techniques to write data to the second memory device. In some cases, a full QLC cache may reduce the performance of the memory system due to a lack of available space, which may cause the memory device to experience longer programming times and longer processing times. In such cases, the memory system may use data migration techniques to write data to the second memory device (rather than a full QLC cache), thereby improving the performance of the memory system.

[0059] At 220, it may be determined whether the data is continuous. For example, the memory system may determine whether the data is continuous (e.g., whether the data is sequential). Continuous data may be an instance of data located at equally spaced time increments, where each data segment is received one after the other, and in some cases, each data segment is received at equally spaced time increments. Each data segment may be associated with a timestamp such that a first segment of continuous data may be received before a second segment of continuous data, and the second segment of continuous data may be received before a third segment of continuous data. In some cases, continuous data may be read one segment (e.g., a subset) of data at a time, and each segment of data may be processed based on information gathered from previous data segments.

[0060] If it is determined at 220 that the data is non-sequential, process 200 may proceed to 230. For example, the memory system may determine that the data is non-sequential data based on determining that the amount of space available for writing is equal to or above a threshold. In some instances, the memory system may determine that the size of the data is below a threshold based on determining that the amount of space available for writing is equal to or above a threshold. In such cases, the memory system may determine whether to use a data migration technique based on determining that the data is non-sequential data and determining that the size of the data is below a threshold. For example, the memory system may determine to use a second migration technique based on determining that the data is non-sequential and determining that the size of the data is below a threshold.

[0061] At 230, the memory system may write the data to the memory device using a second data migration technique based on determining that the data is non-sequential data and determining that the size of the data is below a threshold. For example, the memory system may avoid using a data migration technique to write the data to the memory device based on determining that the data is non-sequential data and determining that the size of the data is below a threshold.

[0062] If it is determined at 220 that the data is sequential, process 200 may proceed to 225. For example, the memory system may determine that the data is sequential data based on determining that the amount of space available for writing is equal to or greater than a threshold. In some examples, the memory system may determine that the size of the data exceeds a threshold based on determining that the amount of space available for writing is equal to or greater than a threshold. For example, the data may include a maximum size of data, such as 512 kilobytes, where the data may be sequential. In such cases, the memory system may determine to use a data migration technique based on determining that the data is sequential data and determining that the size of the data exceeds a threshold.

[0063] At 225, as a result of one or more of the various determinations performed at 210, 215, 220, or any combination thereof, it may be determined to use a first migration technique (e.g., a data migration technique), which may include using a first write format (e.g., TLC) and then migrating the data to a second write format (e.g., QLC). For example, the memory system may determine to use the data migration technique based on determining that the PSA operation is complete, determining that space is available, and determining that the data is contiguous. The various operations, determinations, comparisons, etc. described with reference to process 200 may be performed by one or more components, such as components of a memory system (e.g., memory system 110). In some instances, various components, processors, circuit systems, elements, or modules (or any combination thereof) may be configured to perform these various operations. In other instances, the various operations, determinations, comparisons, etc. described with reference to process 200 may be performed by one or more of a memory system controller (e.g., memory system controller 115), a local memory (e.g., local memory 120), or a memory device (e.g., memory device 130-a or 130-b), other options, or any combination thereof.

[0064] Figure 3 A process 300 is shown that supports data migration techniques according to examples disclosed herein. Aspects of the process 300 may be implemented by a controller and other components. Additionally or alternatively, aspects of the process 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to the memory system 110). For example, the instructions, when executed by a controller (e.g., the memory system controller 115), may cause the controller to perform the operations of the process 300.

[0065] Process 300 may support implementation of data migration techniques, such as those described in reference processes 200 and Figure 2 At 305, it may be determined to use a first migration technique (eg, a data migration technique). For example, a memory system (eg, memory system 110) may determine to use a data migration technique to write data to a memory device (eg, memory device 130).

[0066] At 310, a selection between a first format (e.g., a three-level write format) and a second format (e.g., a four-level write format) can be completed. For example, the memory system can select between writing data to the memory device using the first format and the second format based on determining to use the first migration technology and based on the memory system and / or some of its components being configured to be able to write data in multiple formats (e.g., able to write data in one of multiple formats based on one or more conditions, calculations, determinations, and / or measurements). In some cases, the memory system may determine to use the first format or the second format to write data based on one or more operations (e.g., operations performed at 210, 215, and / or 220). For example, the memory system may select the first format instead of the second format to write data. The memory device may be configured to write data in the first format and the second format based on a write command received from a host system (e.g., host system 105).

[0067] The data may be written using the first format at 315. For example, the memory system may write the data to the memory device using the first format (which may be a TLC format) based on selecting the first format.

[0068] In some cases, the memory system may write data to a primary storage area of ​​a memory device. The primary storage area of ​​the memory device may be an instance of a TLC cache. The TLC cache may include an increased amount of storage space compared to other caches. For example, the size of the TLC cache may be dynamic and may be adjusted based on the size of the incoming data, thereby allowing data to be written to the TLC cache in a first format (as opposed to the data being intended to be written to another storage location, such as another cache, that may not be large enough to accommodate such a write). In other systems, the size of the other cache may be static, thereby preventing an increase in the amount of incoming data written to the other cache in the first format.

[0069] In some examples, the memory system may use a trim setting (e.g., if the memory device includes NAND, then a NAND trim setting is used) and a page mapping for writing data using a first format. In some cases, the trim setting may be related to data retention, and if a relatively fast TLC write process is implemented using the trim setting (e.g., the write process may be a special TLC write operation, such as a write operation based on the trim setting, which may be relatively faster and more efficient than other TLC write operations), and the data is migrated relatively quickly from one format (e.g., TLC format) to a second format (e.g., QLC format), then data retention of such data written using the trim setting of the first format (e.g., TLC format) may be relaxed compared to other write processes (e.g., other write processes and / or other examples using the first format (e.g., TLC format)). In some cases, the memory system may set a spacing between at least two memory states of the memory device relative to a threshold. In such cases, writing data using the first format based on the fine-tuning setting can be based on determining that a spacing between at least two memory states satisfies a threshold, which can be relatively low (e.g., a lower threshold between different states when writing using the fine-tuning setting and the enhancement techniques described herein than alternative write operations using the same write format and / or a different write format). In other words, when using this fine-tuning setting as part of writing data in the first format, setting tolerances (e.g., thresholds) between different tiers (e.g., different TLC tiers) can be more relaxed to allow for increased speed and efficiency relative to other write operations (including operations that may also be performed when writing data in the first format without the fine-tuning setting).

[0070] A memory device (e.g., memory device 130), which may be a NAND device, may receive a command indicating that data may be written using a first format (e.g., the command indicating a TLC write). In such cases, the memory device may be configured to set the cell level to TLC, and a block (e.g., block 170) of the memory device may be treated as TLC, for example, based on the command sequence. TLC writes may operate with reduced processing and write times (relative to other techniques, such as QLC writes), thereby improving the overall efficiency and operation of the memory system. Writing data to the memory device using the first format may be an example of an intermediate step that reduces processing time and improves the efficiency of memory system operation (relative to other techniques, such as writing data to the memory device using another format (e.g., a QLC write format)).

[0071] At 320, the writing can be verified to be completed using the first format. For example, the memory system can verify that the writing is completed using the first format, for example, based on determining the type of writing format after writing the data to the memory device or based on receiving a command indicating that the data was written using the first format, among other factors. In such cases, the memory system can verify that the writing is successful (e.g., completed) in the first format.

[0072] At 325, after verifying that the write is completed using the first format, the data can be migrated (e.g., converted, rewritten) from the first format to the second format. For example, the memory system can migrate data from a first format (which can be a TLC format) to a second format (which can be a QLC format). In such cases, the memory system can convert the data from the first format to the second format based on the write data. The memory system can determine and / or select the time to migrate from the first format to the second format. For example, the memory system can identify an idle period based on the write data (e.g., after writing the data). The idle period can be an instance of a background operation time or a time that is not otherwise specified to perform one or more other commands and / or operations. In such cases, after writing the data in the first format, the memory system can determine the idle time to convert the data from the first format to the second format (e.g., by analyzing the time to perform other commands and / or other operations and selecting one from a plurality of idle times). During the idle time, the memory system can migrate data in the first format (e.g., including TLC data, such as data written in the TLC format) to the second format (e.g., including QLC data, such as data written in the QLC format).

[0073] In some instances, data can be transferred at a higher speed, for example, based on a cache strategy (e.g., one or more TLC cache strategies). In such cases, data migration techniques can be enhanced based on large data transfer as a single event (e.g., a special TLC write operation, such as a write operation based on fine-tuning, which can be relatively faster and more efficient than other TLC write operations). For example, the data transfer after the large data transfer may include a data size that is smaller than the initial data transfer size. The speed of data transfer may be limited by reliability constraints such as temperature and data retention. The TLC cache strategy can use memory device tolerance to increase the write time during the data migration technique (e.g., write data using a first format). In such cases, data retention can be enhanced while maintaining data integrity. Device tolerance (e.g., the interval between at least two memory states of a memory device) can be reduced, thereby increasing the performance time of the memory system, simplifying data transfer, and improving the efficiency of data transfer.

[0074] Figure 4A block diagram 400 is shown of a memory system 405 that supports data migration techniques according to examples disclosed herein. The memory system 405 may be as described in reference Figures 1 to 3 Memory system 405 may include command receiver 410, write component 415, data converter 420, select component 425, data migration component 430, and data component 435. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0075] The command receiver 410 may receive commands associated with a write operation from a host device. The command receiver 410 may be an instance of a memory system controller, a processor, or any other component configured to receive commands (eg, commands associated with a write operation).

[0076] The write component 415 may write the data to the memory device using the tertiary write format based on selecting the tertiary write format. In some examples, the write component 415 may write the data to the memory device using the second data migration technique based on determining that the amount of available space is below a threshold. In some examples, the write component 415 may write the data to the memory device using the second data migration technique based on determining that the production operation is not completed.

[0077] In some examples, the write component 415 can determine that a separation between at least two memory states of the memory device is below a threshold, wherein writing the data is based on determining that a separation between the at least two memory states is below the threshold.

[0078] The write component 415 may be an instance of a central processing unit (CPU), a processor, or any other component configured to write data using a selected format and / or data migration technique (eg, a tertiary write format and / or a second data migration technique).

[0079] The data converter 420 may convert the data from the tertiary write format to the quaternary write format based on the write data. In some examples, the data converter 420 may identify an idle period based on the write data, wherein data conversion is performed during the idle period.

[0080] Data converter 420 may be an example of a CPU, a processor, or any other component configured to convert data from a first format to a second format (eg, migrate data from a tertiary write format to a quaternary write format).

[0081] The selection component 425 can select the tertiary write format over the quaternary write format to write the data based at least in part on determining to use the data migration technique. In some examples, the selection component 425 can determine that the memory device can write data in the tertiary write format and the quaternary write format, wherein selecting the tertiary write format over the quaternary write format is based on the determination.

[0082] The selection component 425 can be an example of a selector, a switch, a transistor, a processor, or any other component configured to select between two or more write formats and / or determine that the memory device can write data in a tertiary write format and a quadruple write format.

[0083] The data migration component 430 can determine whether to use the data migration technology to write the data to the memory device based on receiving the command. In some examples, the data migration component 430 can determine whether the amount of space available for writing exceeds a threshold based on determining that the production operation is complete, wherein determining whether to use the data migration technology is based on determining whether the amount of space available for writing exceeds the threshold.

[0084] In some instances, data migration component 430 can determine that the amount of space available for writing is below a threshold. In some instances, data migration component 430 can determine that the amount of space available for writing is equal to or above a threshold, wherein determining to use a data migration technique is based on determining that the amount of space available for writing is equal to or above the threshold.

[0085] In some instances, data migration component 430 can determine whether the production operation is complete based on receiving the command, wherein determining whether to use the data migration technique is based on determining whether the production operation is complete. In some instances, data migration component 430 can determine that the production operation is not complete. In some instances, data migration component 430 can determine that the production operation is complete, wherein determining to use the data migration technique is based on determining that the production operation is complete.

[0086] The data migration component 430 can be an instance of a comparator, a processor, or any other component configured to determine whether to write data to a memory device using a data migration technique (e.g., determining whether a production operation is complete, determining whether space is available, and / or determining whether data is contiguous).

[0087] The data component 435 can determine that the data is sequential data based on determining that the amount of space available for writing is above a threshold. In some examples, the data component 435 can determine that the size of the data exceeds a threshold based on determining that the amount of space available for writing is above a threshold, wherein determining to use the data migration technique is based on determining that the data is sequential data and determining that the size of the data exceeds the threshold.

[0088] In some examples, data component 435 can determine that the data is non-sequential data based on determining that the amount of space available for writing is above a threshold. In some examples, data component 435 can determine that the size of the data is below a threshold based on determining that the amount of space available for writing is above a threshold, wherein determining whether to use a data migration technique is based on determining that the data is non-sequential data and determining that the size of the data is below the threshold.

[0089] Data component 435 may be an example of a comparator, a processor, or any other component configured to determine the type of data (eg, determine whether the data is sequential data or non-sequential data and / or determine the size of the data).

[0090] Figure 5 A flowchart of one or more methods 500 for supporting data migration techniques according to an example disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figure 4 The memory system described herein may be used to perform the described functions. In some examples, the memory system may execute instruction sets to control functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0091] Aspects of method 500 may be implemented by a controller and other components. Additionally or alternatively, aspects of method 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operations of method 500.

[0092] At 505, a command may be received. For example, the memory system may receive a command associated with a write operation from a host device. The operations of 505 may be performed according to the methods described herein. In some examples, aspects of the operations of 505 may be described with reference to Figure 4 Describes the commands that the receiver executes.

[0093] At 510, it may be determined whether to use data migration techniques. For example, the memory system may determine whether to use data migration techniques to write data to the memory device based on receiving a command. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described by reference to Figure 4 Describes the data migration components to perform.

[0094] At 515, a tertiary write format may be selected. For example, the memory system may select a tertiary write format rather than a quadruple write format to write data based at least in part on determining to use a data migration technique. The operations of 515 may be performed according to the methods described herein. In some examples, aspects of the operations of 515 may be described with reference to Figure 4 Describes the selected component to execute.

[0095] At 520, data may be written. For example, the memory system may write data to the memory device using a tertiary write format based on selecting the tertiary write format. The operations of 520 may be performed according to the methods described herein. In some examples, aspects of the operations of 520 may be described with reference to Figure 4 Describes the writing component to perform.

[0096] At 525, the data may be converted. For example, the memory system may convert the data from a three-level write format to a four-level write format based on the write data. The operation of 525 may be performed according to the methods described herein. In some examples, aspects of the operation of 525 may be described by reference to Figure 4 The data converter described is implemented.

[0097] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command associated with a write operation from a host device; determining whether to write data to a memory device using a data migration technique based on receiving the command; selecting a tertiary write format over a quaternary write format to write the data based at least in part on determining to use the data migration technique; writing the data to the memory device using the tertiary write format based on selecting the tertiary write format; and converting the data from the tertiary write format to the quaternary write format based on writing the data.

[0098] Some examples of method 500 and apparatus described herein may further include operations, features, means, or instructions for determining that a memory device can write data in a tertiary write format and a quaternary write format, wherein selecting the tertiary write format over the quaternary write format may be based on the determination.

[0099] Some instances of method 500 and the devices described herein may further include operations, features, components, or instructions for performing the following: determining whether the amount of space available for writing exceeds a threshold based on determining that a production operation may be completed, wherein determining whether to use data migration technology may be based on determining whether the amount of space available for writing exceeds the threshold.

[0100] In some instances of method 500 and the apparatus described herein, determining whether the amount of available space exceeds a threshold may further include operations, features, components, or instructions for determining that the amount of space available for writing may be below a threshold, and method 500 and the apparatus described herein may further include operations, features, components, or instructions for performing the following items: writing data to the memory device using a second data migration technique based on determining that the amount of available space is below the threshold.

[0101] In some instances of method 500 and the devices described herein, determining whether the amount of available space exceeds a threshold may further include operations, features, components, or instructions for performing the following: determining that the amount of space available for writing is likely equal to or above a threshold, wherein determining to use a data migration technique may be based on determining that the amount of available space is likely equal to or above the threshold.

[0102] Some instances of method 500 and the devices described herein may further include operations, features, components, or instructions for performing the following: determining that the data may be sequential data based on determining that the amount of space available for writing may be above a threshold; and determining that the size of the data exceeds a threshold based on determining that the amount of space available for writing may be above a threshold, wherein determining to use data migration technology may be based on determining that the data may be sequential data and determining that the size of the data exceeds the threshold.

[0103] Some instances of method 500 and the devices described herein may further include operations, features, components, or instructions for performing the following: determining that the data is likely non-sequential data based on determining that the amount of space available for writing is likely above a threshold; and determining that the size of the data is likely below a threshold based on determining that the amount of space available for writing is likely above a threshold, wherein determining whether to use data migration technology may be based on determining that the data is likely non-sequential data and determining that the size of the data is likely below the threshold.

[0104] Some examples of method 500 and apparatus described herein may further include operations, features, components, or instructions for determining whether the production operation may be completed based on receiving the command, wherein determining whether to use the data migration technique may be based on determining whether the production operation may be completed.

[0105] In some instances of method 500 and the apparatus described herein, determining whether a production operation is likely to be completed may further include operations, features, components, or instructions for determining that the production operation is likely not to be completed, and method 500 and the apparatus described herein may further include operations, features, components, or instructions for performing the following items: writing data to a memory device using a second data migration technique based on determining that the production operation is not completed.

[0106] In some examples of method 500 and apparatus described herein, determining whether the production operation is likely to be completed may further include operations, features, components, or instructions for determining that the production operation is likely to be completed, wherein determining to use the data migration technique may be based on determining that the production operation is likely to be completed.

[0107] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for identifying an idle period based on the write data, wherein converting the data may be performed during the idle period.

[0108] Some examples of method 500 and apparatus described herein may further include operations, features, components, or instructions for determining that a spacing between at least two memory states of a memory device may be below a threshold, wherein writing data may be based on determining that a spacing between at least two memory states may be below the threshold.

[0109] It should be noted that the methods described herein are possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. In addition, parts from two or more of the methods may be combined.

[0110] An apparatus is described. The apparatus may include a memory device and a control circuit coupled to the memory device and configured to cause the apparatus to: receive a command associated with a write operation from a host device; determine whether to write data to the memory device using a data migration technique based on receiving the command; select a tertiary write format instead of a quaternary write format to write the data based at least in part on determining to use the data migration technique; write the data to the memory device using the tertiary write format based on selecting the tertiary write format; and convert the data from the tertiary write format to the quaternary write format based on writing the data.

[0111] Some examples may further include determining that the memory device can write data in a tertiary write format and a quaternary write format, wherein selecting the tertiary write format over the quaternary write format may be based on the determination.

[0112] Some examples may further include determining whether an amount of space available for writing exceeds a threshold based on determining that the production operation may be completed, wherein determining whether to use the data migration technique may be based on determining whether the amount of space available for writing exceeds the threshold.

[0113] Some examples may further include determining that the amount of space available for writing may be below a threshold, the control circuit being coupled to the memory device and configured to cause the apparatus to write data to the memory device using a second data migration technique based on determining that the amount of space available is below the threshold.

[0114] Some examples may further include determining that an amount of space available for writing may be equal to or above a threshold, wherein determining to use the data migration technique may be based on determining that the amount of space available may be equal to or above the threshold.

[0115] Some instances may further include determining that the data may be sequential data based on determining that the amount of space available for writing may be above a threshold; and determining that the size of the data exceeds a threshold based on determining that the amount of space available for writing may be above a threshold, wherein determining to use the data migration technique may be based on determining that the data may be sequential data and determining that the size of the data exceeds the threshold.

[0116] Some instances may further include determining that the data is likely non-sequential data based on determining that the amount of space available for writing is likely above a threshold; and determining that the size of the data is likely below a threshold based on determining that the amount of space available for writing is likely above a threshold, wherein determining whether to use data migration technology may be based on determining that the data is likely non-sequential data and determining that the size of the data is likely below a threshold.

[0117] Some examples may further include determining whether the production operation is likely to complete based on receiving the command, wherein determining whether to use the data migration technique may be based on determining whether the production operation is likely to complete.

[0118] Some examples may further include determining that the production operation may not be completed, the control circuit coupled to the memory device and configured to cause the apparatus to write data to the memory device using a second data migration technique based at least in part on determining that the production operation is not completed.

[0119] Some examples may further include determining that the production operation is likely to be completed, wherein determining to use the data migration technique may be based on determining that the production operation is likely to be completed.

[0120] Some examples may further include identifying idle periods based on the write data, wherein converting the data may be performed during the idle periods.

[0121] Some examples may further include determining that a separation between at least two memory states of the memory device may be below a threshold, wherein writing the data may be based on determining that a separation between at least two memory states may be below the threshold.

[0122] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a bus of signals, where the bus may have various bit widths.

[0123] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0124] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0125] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0126] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferably" or "better than other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid confusing the concepts of the described examples.

[0127] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0128] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0129] For example, the various illustrative blocks and modules described in conjunction with the present disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0130] As used herein, "or," as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), as included in the claims, indicates a list that includes endpoints, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0131] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs use lasers to reproduce data optically. Combinations of these are also included within the scope of computer-readable media.

[0132] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a first memory device; as well as a control circuit coupled to the first memory device and configured to cause the apparatus to: receiving a command associated with a write operation from a host device; determining whether to transfer data from a second memory device to the first memory device in a tertiary write format or a quadruple write format using a data migration technique based at least in part on receiving the command; selecting the three-level write format over the four-level write format to transfer the data from the second memory device to the first memory device based at least in part on a completion time of transferring the data from the second memory device to the first memory device in the four-level write format and a determination to use the data migration technique; transferring the data from the second memory device to the first memory device in the tertiary write format based at least in part on selecting the tertiary write format; writing the data to the first memory device using the tertiary write format based at least in part on selecting the tertiary write format; as well as The data is converted from the tertiary writing format to the quaternary writing format based at least in part on writing the data.

2. The device of claim 1, wherein the control circuit is further configured to cause the device to: Determining that the first memory device can write the data in the tertiary write format and the quaternary write format, wherein selecting the tertiary write format instead of the quaternary write format is based at least in part on determining that the first memory device can write the data in the tertiary write format and the quaternary write format.

3. The device of claim 1 , wherein the control circuit is further configured to cause the device to: A determination is made based at least in part on whether an amount of space available for writing exceeds a threshold value, based at least in part on determining that a production operation is complete, wherein determining whether to use the data migration technique is based at least in part on determining whether the amount of space available for writing exceeds the threshold value.

4. The device of claim 3, wherein in order to determine whether the amount of space available exceeds the threshold, the control circuit is configured to cause the device to perform the following operations: determining that the amount of space available for writing is below the threshold, wherein the control circuit is further configured to cause the device to: The data is written to the first memory device using a second data migration technique based at least in part on a determination that the amount of space available is below the threshold.

5. The device of claim 3, wherein to determine whether the amount of space available exceeds the threshold, the control circuit is configured to cause the device to: A determination is made that the amount of space available for writing is equal to or above the threshold, wherein determining to use the data migration technique is based at least in part on determining that the amount of space available is equal to or above the threshold.

6. The device of claim 5, wherein the control circuit is further configured to cause the device to: determining that the data is sequential data based at least in part on determining that the amount of space available for writing is above the threshold; and A determination that the size of the data exceeds a threshold is based at least in part on a determination that the amount of space available for writing is above the threshold, wherein a determination to use the data migration technique is based at least in part on a determination that the data is sequential data and a determination that the size of the data exceeds the threshold.

7. The device of claim 5, wherein the control circuit is further configured to cause the device to: determining that the data is non-sequential data based at least in part on determining that the amount of space available for writing is above the threshold; and A determination that the size of the data is below a threshold is determined at least in part based on a determination that the amount of space available for writing is above the threshold, wherein determining whether to use the data migration technique is based at least in part on a determination that the data is non-sequential data and a determination that the size of the data is below the threshold.

8. The device of claim 1, wherein the control circuit is further configured to cause the device to: A determination is made whether a production operation is complete based at least in part on receiving the command, wherein determining whether to use the data migration technique is based at least in part on determining whether the production operation is complete.

9. The apparatus of claim 8, wherein in order to determine whether the production operation is completed, the control circuit is configured to cause the apparatus to perform the following operations: determining that the production operation is not completed, wherein the control circuit is further configured to cause the device to perform the following operations: The data is written to the first memory device using a second data migration technique based at least in part on determining that the production operation is not complete.

10. The apparatus of claim 8, wherein in order to determine whether the production operation is completed, the control circuit is configured to cause the apparatus to perform the following operations: A determination is made that the production operation is complete, wherein the determination to use the data migration technique is based at least in part on the determination that the production operation is complete.

11. The device of claim 1 , wherein the control circuit is further configured to cause the device to: An idle period is identified based at least in part on writing the data, wherein converting the data is performed during the idle period.

12. The device of claim 1, wherein the control circuit is further configured to cause the device to: A determination is made that a separation between at least two memory states of the first memory device is below a threshold, wherein writing the data is based at least in part on determining that the separation between the at least two memory states is below the threshold.

13. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a command associated with a write operation from a host device; determining whether to transfer data from the first memory device to the second memory device in a tertiary write format or a quadruple write format using a data migration technique based at least in part on receiving the command; selecting the three-level write format over the four-level write format to transfer the data from the first memory device to the second memory device based at least in part on a completion time of transferring the data from the first memory device to the second memory device in the four-level write format and a determination to use the data migration technique; transferring the data from the first memory device to the second memory device in the tertiary write format based at least in part on selecting the tertiary write format; writing the data to the second memory device using the tertiary write format based at least in part on selecting the tertiary write format and transferring the data from the first memory device to the second memory device; as well as The data is converted from the tertiary writing format to the quaternary writing format based at least in part on writing the data.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Determining that the second memory device can write the data in the tertiary write format and the quaternary write format, wherein selecting the tertiary write format instead of the quaternary write format is based at least in part on determining that the second memory device can write the data in the tertiary write format and the quaternary write format.

15. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A determination is made based at least in part on whether an amount of space available for writing exceeds a threshold value, based at least in part on determining that a production operation is complete, wherein determining whether to use the data migration technique is based at least in part on determining whether the amount of space available for writing exceeds the threshold value.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions that, when executed by the processor of the electronic device, cause the electronic device to determine whether the amount of space available exceeds the threshold value include instructions that, when executed by the processor of the electronic device, cause the electronic device to: determining that the amount of space available for writing is below the threshold, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The data is written to the second memory device using a second data migration technique based at least in part on determining that the amount of space available is below the threshold.

17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A determination is made that the amount of space available for writing is equal to or above the threshold, wherein determining to use the data migration technique is based at least in part on determining that the amount of space available is equal to or above the threshold.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determining that the data is sequential data based at least in part on determining that the amount of space available for writing is above the threshold; and A determination that the size of the data exceeds a threshold is based at least in part on a determination that the amount of space available for writing is above the threshold, wherein a determination to use the data migration technique is based at least in part on a determination that the data is sequential data and a determination that the size of the data exceeds the threshold.

19. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determining that the data is non-sequential data based at least in part on determining that the amount of space available for writing is above the threshold; and A determination that the size of the data is below a threshold is determined at least in part based on a determination that the amount of space available for writing is above the threshold, wherein determining whether to use the data migration technique is based at least in part on a determination that the data is non-sequential data and a determination that the size of the data is below the threshold.

20. A method comprising: receiving a command associated with a write operation from a host device; determining whether to transfer data from the first memory device to the second memory device in a tertiary write format or a quadruple write format using a data migration technique based at least in part on receiving the command; selecting the three-level write format over the four-level write format to transfer the data from the first memory device to the second memory device based at least in part on a completion time of transferring the data from the first memory device to the second memory device in the four-level write format and a determination to use the data migration technique; transferring the data from the first memory device to the second memory device in the tertiary write format based at least in part on selecting the tertiary write format; writing the data to the second memory device using the tertiary write format based at least in part on selecting the tertiary write format and transferring the data from the first memory device to the second memory device; as well as The data is converted from the tertiary writing format to the quaternary writing format based at least in part on writing the data.

21. The method according to claim 20, further comprising: Determining that the second memory device can write the data in the tertiary write format and the quaternary write format, wherein selecting the tertiary write format instead of the quaternary write format is based at least in part on determining that the second memory device can write the data in the tertiary write format and the quaternary write format.

22. The method of claim 20, further comprising: A determination is made based at least in part on whether an amount of space available for writing exceeds a threshold value, based at least in part on determining that a production operation is complete, wherein determining whether to use the data migration technique is based at least in part on determining whether the amount of space available for writing exceeds the threshold value.

23. The method of claim 22, wherein determining whether the amount of space available exceeds the threshold further comprises: Determining that the amount of space available for writing is below the threshold, the method further comprising: The data is written to the second memory device using a second data migration technique based at least in part on determining that the amount of space available is below the threshold.

24. The method of claim 22, wherein determining whether the amount of space available exceeds the threshold further comprises: A determination is made that the amount of space available for writing is equal to or above the threshold, wherein determining to use the data migration technique is based at least in part on determining that the amount of space available is equal to or above the threshold.

25. The method of claim 24, further comprising: determining that the data is sequential data based at least in part on determining that the amount of space available for writing is above the threshold; as well as A determination that the size of the data exceeds a threshold is based at least in part on determining that the amount of space available for writing is above the threshold, wherein a determination to use the data migration technique is based at least in part on determining that the data is sequential data and determining that the size of the data exceeds the threshold.

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