Method for implementing serial interface chip testing

Abstract

The present invention relates to a method for implementing the test of a serial interface chip, which includes inputting a specific communication protocol through the serial communication pins of the I2C control module, and the chip enters the test mode; selecting to enter various secondary test modes through the instruction code and its parsing format, performing serial or parallel conversion of data with the test decoding circuit through the serial communication pins of the I2C control module, and performing data reading and writing; ending the instruction or an instruction decoding error instruction, and the chip exits the test mode. By adopting the method for implementing the test of the serial interface chip of the present invention, the I2C pins are reused as test pins, eliminating the need for dedicated test pins that the chip needs to be additionally packaged, saving the packaging cost. Relying on the advantages of the I2C hardware communication protocol, the present invention undertakes a large part of the software program overhead, simplifies the chip test program, and once problems are found during the test, it is easier to troubleshoot, greatly improving the work efficiency of testers, further reducing costs, and improving the chip test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of hardware circuits, and more particularly to the field of chip testing, and specifically refers to a method for implementing the testing of serial interface chips. Background Art

[0002] Existing chip testing methods generally require independent test pins to be encapsulated outside the chip. Through this pin, various test modes are selected, and then a test program is written and converted into a binary test code, which is input from the test pin to complete the testing and evaluation of various circuit performances.

[0003] This method requires the encapsulation of additional dedicated test pins, which will increase the additional packaging cost for some mid - to - low - end chips that follow a low - cost route. At the same time, this traditional testing method requires writing relatively complex software test programs, which require relatively high software programming capabilities for testers, and it is also relatively difficult to troubleshoot from the complex programs once testing problems are found. Therefore, the overall testing efficiency is relatively low. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above - mentioned disadvantages of the prior art, and provide a method for implementing the testing of serial interface chips that features high testing efficiency, low cost, and a relatively wide range of applications.

[0005] In order to achieve the above purpose, the method for implementing the testing of serial interface chips of the present invention is as follows:

[0006] The method for implementing the testing of serial interface chips is mainly characterized in that the method includes the following steps:

[0007] Input the first communication protocol through the serial communication pin of the I2C control module, and the chip enters the test mode;

[0008] Select to enter each secondary test mode through the instruction code and its parsing format, perform data serial - to - parallel or parallel - to - serial conversion with the test decoding circuit through the serial communication pin of the I2C control module, and perform data reading and writing;

[0009] Receive the test end instruction or the instruction decoding error instruction, and the chip exits the test mode.

[0010] Preferably, the step of the chip entering the test mode specifically includes the following processing procedures:

[0011] When the chip is in the idle state, if it detects that I2C_RSTN goes high, the chip enters the waiting state;

[0012] Pull down and hold the serial data line SDA, and the chip enters the response stage;

[0013] After waiting for the preset time, release the serial clock line SCL to restore the serial clock line SCL to its default value of high level.

[0014] When the chip detects that the serial clock line SCL goes high, it automatically releases the serial data line SDA to restore the serial data line SDA to its default value of high level. The chip exits the acknowledgment phase and enters the release state.

[0015] Pull up the TEST_EN signal to enter the test mode for address matching, and the chip waits for the input of the mode selection code for the receive mode.

[0016] Preferably, when the chip is in the idle state, the reset signal LONG_RSTN is 0 and the serial clock line SCL is forced to be pulled low.

[0017] Preferably, the preset time is greater than 80 microseconds.

[0018] Preferably, the steps for the chip to enter each secondary test mode specifically include the following processing procedures:

[0019] Select the secondary test mode through the first byte of data input by the I2C control module and enter the corresponding test. Each secondary mode corresponds to a group of 5-bit mode selection codes.

[0020] When the secondary test process ends, input the corresponding instruction to exit the secondary mode; if re-entering other secondary test modes.

[0021] Preferably, the steps for entering the secondary test mode further include the following processing procedures:

[0022] If the input secondary test mode code value is not within the secondary test modes included in the chip, generate an i2c_test_quit signal for one clock cycle to the I2C control module, and the I2C control module pulls down the test_en signal to exit the test mode.

[0023] Preferably, the steps for the chip to exit the test mode specifically include the following processing procedures:

[0024] Judge whether to receive the test end instruction or the instruction decoding error instruction. If so, the chip exits the test mode and the TEST_EN signal is pulled down; otherwise, continue to maintain the test state.

[0025] The chip enters the QUIT state and judges whether it detects that LONG_RSTN is pulled high. If so, it switches to the NORM state, and the I2C control module exits the test mode and restores the normal communication mode; otherwise, continue to maintain the QUIT state.

[0026] Preferably, the secondary test mode includes five modes, namely scan chain test, RAM test, OTP test, register test, and clock test.

[0027] Preferably, the scan chain test mode is specifically as follows:

[0028] After the TEST_EN signal goes high, input the SCAN TEST mode code MODE_CODE1 through the I2C interface to enter the scan chain test mode, complete the chip scan chain test, and exit the SCAN TEST mode when powering off;

[0029] The RAM test mode is specifically as follows:

[0030] After TEST_EN goes high, input the RAM BIST mode code MODE_CODE2 through the I2C interface to enter the RAM BIST mode, complete the read and write tests of the RAM, and exit the RAM test mode through the RAM BIST test exit instruction code.

[0031] Preferably, the OTP test mode is specifically as follows:

[0032] After TEST_EN goes high, input the OTP TEST mode code MODE_CODE3 through the I2C interface to enter the OTP TEST mode, complete the tests of erasing, programming, and reading the OTP. After the tests are completed, exit the OTP test mode through the OTP TEST test exit instruction code;

[0033] The register test mode is specifically as follows:

[0034] After TEST_EN goes high, input the REG TEST mode code MODE_CODE4 through the I2C interface to enter the register test mode, access the TRIM register and SFR register through different instruction codes; complete various performance parameter tests by setting the TRIM and SFR registers, and exit the register test mode through the REG TEST test exit instruction code;

[0035] The clock test mode is specifically as follows:

[0036] After TEST_EN goes high, input the CLK TEST mode code MODE_CODE5 through the I2C interface to enter the CLK TEST mode, complete the test of the chip clock network, and exit the clock test mode through the CLK TEST test exit instruction code.

[0037] By adopting the method for testing a serial interface chip according to the present invention, the I2C pins are reused as test pins, eliminating the need for dedicated test pins that need to be additionally packaged for the chip, and saving the packaging cost. Relying on the advantages of the I2C hardware communication protocol, the present invention undertakes a large part of the software program overhead, simplifies the chip test program, makes it easier to troubleshoot problems once they are found during testing, greatly improves the work efficiency of testers, further reduces costs, and improves the chip test efficiency. Description of the Drawings

[0038] Figure 1 It is a system block diagram of the method for testing a serial interface chip according to the present invention.

[0039] Figure 2 It is a specific protocol timing diagram for entering the test mode of the method for testing a serial interface chip in an embodiment.

[0040] Figure 3 It is a schematic diagram of the I2C communication format in the secondary test mode of the method for testing a serial interface chip in an embodiment.

[0041] Figure 4 It is a timing diagram of the secondary test mode of the method for testing a serial interface chip in an embodiment. Detailed Embodiments

[0042] In order to more clearly describe the technical content of the present invention, the following will be further described in conjunction with specific embodiments.

[0043] The present invention independently innovates a set of systematic methods for entering the test mode, selecting the secondary test mode, and exiting the test mode. First, the specific protocol for entering the test mode can ensure the reliability and stability of entering the test mode; secondly, through the independently innovated instruction codes and their parsing formats, various secondary test modes can be flexibly selected, data can be read and written, and a perfect test exit mechanism can be established. Relying on the advantages of the I2C hardware communication protocol, the present invention undertakes a large part of the software program overhead, simplifies the chip test program, makes it easier to troubleshoot problems once they are found during testing, greatly improves the work efficiency of testers, further reduces costs, and improves the overall chip test efficiency.

[0044] The present invention provides a method for testing a chip through the asynchronous half-duplex serial communication protocol I2C.

[0045] The working principle of the method described in the present invention is as follows:

[0046] During the reset of the chip system reset signal LONG_RSTN, a first communication protocol is input through the I2C interface to put the chip into the test mode, so as to perform various tests. After entering the test mode, the I2C is responsible for performing data serial / parallel conversion with the instruction decoding module to realize the reading and writing of test data. The overall system block diagram is as Figure 1 shown.

[0047] The present invention discloses a method for testing a chip using the asynchronous half-duplex serial communication protocol I2C, provides a specific protocol for the test mode, and also provides a method, instruction code and its parsing format for the secondary test mode.

[0048] The method for implementing the serial interface chip test of the present invention includes the following steps:

[0049] Input a specific communication protocol through the serial communication pin of the I2C control module, and the chip enters the test mode;

[0050] Select to enter each secondary test mode through the instruction code and its parsing format, perform data serial or parallel conversion with the test decoding circuit through the serial communication pin of the I2C control module, and perform data reading and writing;

[0051] Receive a test end instruction or an instruction decoding error instruction, and the chip exits the test mode.

[0052] The method described in this invention is divided into two parts. The first part is the design of the specific protocol for the I2C to enter the test mode. The timing diagram of the specific protocol for entering the test mode is as Figure 2 shown.

[0053] (1.1) LONG_RSTN = 0 and SCL is forced to be pulled low. At this time, the chip is in the idle state IDLE. This is the first stage;

[0054] (1.2) If it is detected at this time that I2C_RSTN becomes high, the chip will enter the waiting state WAIT. This is the second stage;

[0055] (1.3) Then the chip will enter the response stage. At this time, the chip automatically pulls SDA low and holds it. This is the third stage;

[0056] (1.4) After the tester observes that SDA is pulled low, wait for at least 80 us and then release SCL to make SCL return to the default value of high level. When the chip internally detects that SCL becomes high, it automatically releases SDA, so that SDA also returns to the default value of high level. The chip exits the response stage and enters the release state RELEASE. This is the fourth stage;

[0057] (1.5) At this time, TEST_EN is pulled high, indicating successful entry into the test mode. First, address matching is performed. In the test mode, the I2C slave device address is hardware-fixed; after the master device sends the correct address match, the chip starts to wait for the input of the mode selection code in the receive mode. After testing for a period of time, when the test end instruction QUIT or the instruction decoding error instruction is received, the chip exits the test mode, and TEST_EN is immediately pulled low, and the chip enters the QUIT state. This is the fifth stage;

[0058] (1.6) In the QUIT mode, once it is detected that LONG_RSTN is pulled high, the chip switches to the NORM state, and I2C immediately exits the test mode and returns to the normal communication mode.

[0059] The second part is the design of the secondary test mode. The timing diagram of the secondary test mode is as Figure 4 shown.

[0060] After TEST_EN goes high and enters the test mode, 1-byte data is input through I2C to select the secondary test mode and perform relevant tests. In the test mode, the I2C slave address is fixed, and the read or write operation is determined by the read / write (R / W) bit sent by the master device. '0' indicates that the master device sends data (write), and '1' indicates that the master device receives data (read). The specific method is as follows:

[0061] (2.1) The first byte of data input through I2C is for secondary test mode selection. The secondary test mode includes a total of 5 modes: scan chain test (SCAN TEST), RAM test (RAM BIST), OTP test (OTP TEST), register test (REG TEST), and clock test (CLK TEST). At the same time, each secondary mode corresponds to a group of 5-bit mode selection codes. The 5 secondary test modes and their corresponding codes are shown in Table 1 below.

[0062] Secondary test mode SCAN TEST RAM BIST OTP TEST REG TEST CLK TEST Mode selection code MODE_CODE1 MODE_CODE2 MODE_CODE3 MODE_CODE4 MODE_CODE5

[0063] The communication format for entering the secondary test mode is: 1-bit start bit START + 8-bit I2C slave device address + 1-bit write operation bit + 5-bit mode selection code + 1-bit stop bit STOP, as specifically Figure 3 shown.

[0064] (2.2) If the input secondary test mode encoding value is outside these 5 types, a 1-clock-cycle i2c_test_quit signal is generated to the I2C control module, and the I2C control module then pulls test_en low to exit the test mode.

[0065] (2.3) After selecting any mode, the corresponding test can be entered. After the secondary test process ends, an instruction can be input to exit the secondary mode. There are different exit instructions according to different secondary modes.

[0066] (2.4) After exiting the secondary test mode, if you need to re-enter another secondary test mode, you can repeat the operation in step 1.

[0067] The following are the various secondary test modes:

[0068] Scan chain test mode:

[0069] After TEST_EN goes high, input the SCAN TEST mode code MODE_CODE1 through the I2C interface to enter the scan chain test mode. After entering this mode, complete the chip scan chain test. Only by powering off can the SCAN TEST mode be exited.

[0070]

[0071] RAM test mode:

[0072] After TEST_EN goes high, input the RAM BIST mode code MODE_CODE2 through the I2C interface to enter the RAM BIST mode. After entering this mode, complete tests such as reading and writing of the RAM. After the test is completed, exit this test mode through the RAM BIST test exit instruction code.

[0073]

[0074] OTP test mode:

[0075] After TEST_EN goes high, input the OTP TEST mode code MODE_CODE3 through the I2C interface to enter the OTP TEST mode. After entering this mode, complete tests such as erasing, programming, and reading of the OTP. After the test is completed, exit this test mode through the OTP TEST test exit instruction code.

[0076]

[0077]

[0078] Register test mode:

[0079] After TEST_EN becomes high, the REG TEST mode code MODE_CODE4 is input through the I2C interface to enter the register test mode. After entering this mode, the TRIM register (register solidified in the OTP area) and SFR register (general register accessible to the CPU) can be accessed through different instruction codes. By setting the TRIM and SFR registers, various performance parameter tests of analog circuits such as high-speed oscillators, low-speed oscillators, LDO, power-on reset, low-voltage reset, bandgap reference, IO ports, and digital circuit modules can be completed. After completing the test, exit the test mode through the REG TEST test exit instruction code.

[0080]

[0081] Clock test mode:

[0082] After TEST_EN becomes high, input CLK TEST mode code MODE_CODE5 through the I2C interface to enter CLK TEST mode. After entering this mode, complete the test of the chip clock network. After the test is completed, exit the test mode through the CLK TEST test exit instruction code.

[0083]

[0084] The above test method, in the test mode, reuses the serial communication pins of I2C as chip test pins, thereby eliminating the need for special test pins that the chip needs to be additionally packaged, thereby saving packaging costs.

[0085] At the same time, during the test process, based on the I2C communication protocol, we independently innovated a set of systematic methods for entering the test mode, selecting the secondary test mode, and exiting the test mode. First, the specific protocol for entering the test mode can ensure the reliability and stability of entering the test mode; second, through the independently innovated instruction code and its parsing format, we can flexibly choose to enter various secondary test modes, read and write data, and improve the test exit mechanism. Relying on the advantages of the I2C hardware communication protocol, it bears a large part of the software program overhead, which simplifies the chip test program. Once a problem is found during the test, it is easier to troubleshoot, which greatly improves the work efficiency of testers, further reduces costs, and improves chip testing efficiency.

[0086] The method for implementing serial interface chip testing of the present invention is adopted, where I2C pins are reused as test pins, eliminating the need for dedicated test pins that the chip needs to be additionally packaged, saving packaging costs. Relying on the advantages of the I2C hardware communication protocol, the present invention undertakes a large part of the software program overhead, simplifying the chip test program. Once problems are found during testing, it is easier to troubleshoot, greatly improving the work efficiency of testers, further reducing costs, and improving chip test efficiency.

[0087] In this specification, the present invention has been described with reference to its specific embodiments. However, it is obvious that various modifications and variations can still be made without departing from the spirit and scope of the present invention. Therefore, the specification and the drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for implementing the test of a serial interface chip, characterized in that, The method described above includes the following steps: Input the first communication protocol through the serial communication pin of the I2C control module, and the chip enters the test mode; Select to enter each secondary test mode through the instruction code and its parsing format, perform data serial or parallel conversion with the test decoding circuit through the serial communication pin of the I2C control module, and perform data reading and writing; Receive the test end instruction or instruction decoding error instruction, and the chip exits the test mode; The steps for the chip to enter the test mode specifically include the following processing procedures: When the chip is in the idle state, if it detects that I2C_RSTN goes high, the chip enters the waiting state; Pull down and hold the serial data line SDA, and the chip enters the acknowledgment stage; Release the serial clock line SCL after waiting for a preset time, and make the serial clock line SCL restore to the default value of high level; When the chip detects that the serial clock line SCL goes high, it automatically releases the serial data line SDA, makes the serial data line SDA restore to the default value of high level, the chip exits the acknowledgment stage, and enters the release state; Pull up the TEST_EN signal, enter the test mode, perform address matching, and the chip waits to receive the input of the mode selection code.

2. The method for implementing the test of the serial interface chip according to claim 1, wherein When the chip is in the idle state, the reset signal LONG_RSTN is 0 and the serial clock line SCL is forced to be pulled low.

3. The method for implementing the test of the serial interface chip according to claim 1, wherein The preset time is greater than 80 microseconds.

4. The method for implementing the test of the serial interface chip according to claim 1, wherein The steps for the chip to enter each secondary test mode specifically include the following processing procedures: Select the secondary test mode through the first byte of data input by the I2C control module, enter the corresponding test, and each secondary mode corresponds to a group of 5-bit mode selection codes; After the secondary test process ends, input the corresponding instruction to exit the secondary test mode; If re-entering other secondary test modes, repeat the steps for the chip to enter the test mode.

5. The method for implementing the test of the serial interface chip according to claim 4, wherein The steps for the chip to enter each secondary test mode further include the following processing procedures: If the input secondary test mode code value is not within the secondary test modes included in the chip, generate an I2C_TEST_QUIT signal for one clock cycle to the I2C control module, and the I2C control module pulls down the TEST_EN signal to exit the test mode.

6. The method for implementing the test of the serial interface chip according to claim 1, wherein The steps for the chip to exit the test mode specifically include the following processing procedures: Judge whether to receive the test end instruction or instruction decoding error instruction. If so, the chip exits the test mode and the TEST_EN signal is pulled down; otherwise, continue to maintain the test state; The chip enters the QUIT state, and judges whether it detects that the reset signal LONG_RSTN is pulled high. If so, it switches to the NORM state, the I2C control module exits the test mode, and resumes the normal communication mode; otherwise, continue to maintain the QUIT state.

7. The method for implementing the test of the serial interface chip according to claim 4, characterized in that, The secondary test mode includes 5 modes, namely scan chain test, RAM test, OTP test, register test, and clock test.

8. The method for implementing the test of the serial interface chip according to claim 7, wherein The scan chain test mode is specifically as follows: After the TEST_EN signal goes high, input the SCAN TEST mode code MODE_CODE1 through the I2C interface to enter the scan chain test mode, complete the chip scan chain test, and exit the SCAN TEST mode when powering down; The described RAM test mode is specifically as follows: After TEST_EN goes high, input the RAM BIST mode code MODE_CODE2 through the I2C interface to enter the RAM BIST mode, complete the read and write tests of the RAM, and exit the RAM test mode through the RAM BIST test exit instruction code.

9. The method for implementing the test of the serial interface chip according to claim 7 or 8, characterized in that The described OTP test mode is specifically as follows: After TEST_EN goes high, input the OTP TEST mode code MODE_CODE3 through the I2C interface to enter the OTP TEST mode, complete the tests of erasing, programming, and reading the OTP. After the test is completed, exit the OTP test mode through the OTP TEST test exit instruction code; The described register test mode is specifically as follows: After TEST_EN goes high, input the REG TEST mode code MODE_CODE4 through the I2C interface to enter the register test mode, access the TRIM register and the SFR register through different instruction codes; complete various performance parameter tests by setting the TRIM and SFR registers, and exit the register test mode through the REG TEST test exit instruction code; The described clock test mode is specifically as follows: After TEST_EN goes high, input the CLK TEST mode code MODE_CODE5 through the I2C interface to enter the CLK TEST mode, complete the test of the chip clock network, and exit the clock test mode through the CLK TEST test exit instruction code.

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