A processing method and system

Abstract

An embodiment of the present application provides a processing method and system, which includes: a first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, wherein the first target indicator parameter is used to indicate the target performance of the target processing unit in a computing state; a second logic and computing unit calculates a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; and a regulator is controlled based on the target result to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains a change in the first target indicator parameter.

Description

Technical Field

[0001] The present application relates to the field of processor power supply technology, and in particular to a processing method and system. Background Art

[0002] In processor power supply technology, different scenarios place varying demands on the processor's power supply modules and the processor itself. Furthermore, the heat dissipation capabilities of these modules and the processor itself change in real time. Consequently, heat dissipation issues can arise between these modules and the processor, preventing the processor from operating at optimal power consumption. Summary of the Invention

[0003] The embodiments of the present application hope to provide a processing method and system.

[0004] In a first aspect, an embodiment of the present application provides a processing method, the method comprising:

[0005] The first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to the target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0006] The second logic and calculation unit calculates a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; and controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains the change of the first target indicator parameter.

[0007] In a second aspect, an embodiment of the present application provides a processing system, the system comprising:

[0008] a first logic unit, configured to obtain a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, wherein the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0009] a second logic and calculation unit for calculating a target result based on monitoring a second target parameter and / or by monitoring the first target parameter provided to the target processing unit; and controlling the regulator based on the target result;

[0010] the regulator is configured to adjust the first target parameter provided to the target processing unit in response to control of the second logic and calculation unit;

[0011] the first logic unit is configured to obtain a change in the first target indicator parameter in response to the regulator adjusting the first target parameter provided to the target processing unit;

[0012] The target processing unit is configured to adjust its own indicator parameters in response to a change in the first target indicator parameter.

[0013] In an embodiment of the present application, the target result can be calculated by the second logic and calculation unit based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit, and then the regulator is controlled based on the target result to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter. The target processing unit can further adjust its own indicator parameters in response to the change of the first target indicator parameter, so that the target processor unit operates at a suitable target indicator parameter, thereby making the target processor operate at a suitable power consumption, thereby improving the performance of the system.

[0014] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0016] Figure 1 A schematic diagram of the composition structure of a GPU system in related technology;

[0017] Figure 2 A schematic diagram of the structure of the central processing unit (CPU) system in the relevant system;

[0018] Figure 3 A schematic diagram of an implementation flow of a processing method provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0020] Figure 5 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0023] Figure 8 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0024] Figure 9 A schematic diagram of an implementation flow of another processing method provided in an embodiment of the present application;

[0025] Figure 10 A schematic diagram of the structure of a GPU system provided in an embodiment of the present application;

[0026] Figure 11 A schematic diagram of the structure of a CPU processing system provided in an embodiment of the present application;

[0027] Figure 12 A schematic diagram of the structure of a processing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are merely intended to explain the present application and are not intended to limit the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions described in the embodiments of the present application may be implemented in any combination.

[0029] It should be noted that, in the embodiments of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or apparatus comprising a series of elements includes not only the elements explicitly stated, but also other elements not explicitly listed, or also includes elements inherent to the implementation of the method or apparatus. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other related elements (such as steps in the method or units in the apparatus, for example, a unit may be a portion of a circuit, a portion of a processor, a portion of a program or software, etc.) in the method or apparatus comprising the element.

[0030] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three possible relationships exist. For example, "U and / or W" can represent three situations: the existence of U alone, the existence of both U and W, and the existence of W alone. Furthermore, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of items. For example, "at least one of U, W, and V" can represent any one or more elements selected from the set consisting of U, W, and V.

[0031] Figure 1 It is a schematic diagram of the composition structure of the GPU system in the related technology, such as Figure 1As shown, the graphics processing system includes: a power source 100, a core power module 101, a video memory power module (Vram Power) 102, a GPU 103, a first resistor R1, a second resistor R2, and a power consumption acquisition chip 104;

[0032] Among them, R2 is connected in series between the core power module 101 and the power supply 100; R1 is connected in series between the common node of the core power module 101 and R2 and the video memory power module 102, R1 is used to sense the current entering the video memory power module 102; R2 is used to sense the total current entering the GPU 103; the power supply 100 is used to supply power to the core power module 101 and the video memory power module 102; the output ends of the core power module 101 and the video memory power module 102 are respectively connected to the first input end and the second input end of the GPU 103; the first input end of the power consumption acquisition chip 104 is connected to the common node of R1 and the video memory power module 102; the second input end and the third input end of the power consumption acquisition chip 104 are both connected to the common node of the core power module 101 and R2; the fourth input end of the power consumption acquisition chip 104 is connected to the common node of R2 and the core power module 101; the fifth input end and the sixth input end of the power consumption acquisition chip 104 are both connected to the common node of the core power module 100 and R2; the output end of the power consumption acquisition chip 104 is connected to the GPU The third input terminal of 103; the power consumption collection chip 104 is used to output the collected power consumption data to the GPU 103.

[0033] The core power supply module 101 and the memory power supply module 103 are used to power the GPU 103; the power consumption acquisition chip 104 is used to provide the collected power consumption data to the GPU 103, and does not perform logic and data processing; the data acquisition algorithm adopted by the power consumption acquisition chip 104 is to sample the voltage across the resistor and then calculate the power consumption data based on the sampled voltage; that is, the power consumption acquisition chip 104 can determine the current entering the core power supply module 101 based on the voltages P1 and N1 across R1, and then calculate the power consumption of the core power supply module 101 based on the sampled voltage V1; and determine the total current entering the GPU 103 based on the voltages P2 and N2 across R2, and then calculate the total power consumption of the GPU 103 based on the sampled voltage V2.

[0034] Figure 2 It is a schematic diagram of the composition structure of the CPU system in the related art, such as Figure 2 As shown, the CPU system includes: a power supply 200, a voltage regulator (Voltage Regulation, VR) 201, a central processing unit (Central Processing Unit, CPU) 202, a third resistor R3 and a fourth resistor R4;

[0035] R3 is connected in series between the power supply 200 and the power input terminal of VR 201; R4 is connected in series between the Imon signal terminal and the ground terminal of VR 201; the power output terminal of VR 201 is connected to the first input terminal of the CPU; the power signal output terminal of VR 201 is connected to the second input terminal of CPU 202;

[0036] VR 201 is used to provide power to CPU 202; CPU 202 reads VR information through the SVID communication protocol, which includes voltage, current, power consumption, etc.; Imon is used to set the maximum power consumption of the CPU system and achieve different power consumption settings by changing the voltage.

[0037] In the related art, the core power module and the memory power module are used differently in different scenarios. In some scenarios, the core power module is overused and the memory power module is underused; in other scenarios, the memory power module is overused and the core power module is underused. This will cause the core power module or the memory power module to overheat, causing the temperature of system components to be too high, causing great damage to the system.

[0038] At the same time, when the heat dissipation capabilities of the GPU or CPU are different, the GPU or CPU cannot run at the power consumption that is most suitable for it.

[0039] Based on the above technical problems, the embodiment of the present application provides a processing method that can be applied to a graphics processor system, such as Figure 3 As shown, the method includes:

[0040] Step S301: a first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0041] Here, the form of the first logic unit is not specifically limited. The first logic unit may be a chip with a simple logic calculation function, or may be a partial circuit on a certain chip.

[0042] In some possible implementations, the target processing unit may be a GPU, and the first logic unit may be a power consumption acquisition chip; the first target parameter may be the voltage and current provided to the GPU in real time by the power supply monitored by the first logic unit; the first target parameter may refer to the power consumption of the GPU monitored by the first logic unit.

[0043] In one embodiment, the first logic unit obtains the first target indicator parameter by monitoring the first target parameter provided to the target processing unit. The first logic unit may monitor the first target parameter provided to the target processing unit and calculate the first target indicator parameter based on the first target parameter. For example, the first target parameter may include a current signal and a voltage signal, or may include a voltage value across a resistor with a known impedance value. The first target indicator parameter may be equal to the product of the voltage and the current, or may be equal to the product of a quotient and a corresponding voltage value. The quotient is obtained by dividing the difference between the voltage values ​​across the resistor by the known impedance value of the resistor.

[0044] It can be understood that for the implementation method in which the first logic unit obtains the first target indicator parameter by monitoring the first target parameter provided to the target processing unit, since the monitoring is performed in real time, the first target parameter and the first target indicator parameter obtained through the first target parameter both change dynamically in real time.

[0045] Step S302: The second logic and calculation unit calculates a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; based on the target result, the regulator is controlled to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains the change of the first target indicator parameter.

[0046] Here, the form of the second logic and computing unit is not specifically limited. The first logic and computing unit can be a chip with logic processing and output processing functions, or a partial circuit on a chip. For example, the second logic and computing unit can be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a microcontroller, and a microprocessor.

[0047] It is understood that the regulator may include multiple sub-regulators; the number of sub-regulators may be consistent with the number of power modules in the GPU or CPU processing system. For example, if the number of power modules in the GPU processing system is two, the number of sub-regulators is also two.

[0048] In some possible implementations, the second target parameter can be a parameter completely different from the first target parameter, as long as the second target parameter is linearly proportional to the first target parameter corresponding to the first target parameter. For example, the second target parameter may include temperature information of each power module in the GPU system or CPU system that supplies power to the GPU or CPU, and the GPU or CPU itself; the first target parameter may be a power consumption parameter that is linearly proportional to the temperature information.

[0049] It can be understood that the target result can be a result related to the first target parameter or a result related to the second target parameter.

[0050] In a first possible implementation, the second logic and calculation unit calculates the target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit. The second logic and calculation unit may calculate the temperature parameter status of each power module and the GPU or CPU itself in the GPU or CPU system based on the monitored temperature parameter; for example, whether each power module and the GPU or CPU itself is at a high temperature, a low temperature, or a normal temperature;

[0051] Correspondingly, based on the target result, the regulator is controlled to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains the change of the first target indicator parameter. The second logic and calculation unit can control the target sub-regulator in the regulator according to whether each power module and the GPU or CPU itself is at high temperature, low temperature or normal temperature to adjust the voltage or current parameters provided to the GPU or CPU, so that the power consumption parameters output to the target processing unit in the first logic unit change.

[0052] In a second possible implementation, the second logic and calculation unit calculates the target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit. The second logic and calculation unit may calculate the power consumption state of each power module in the GPU or CPU system and the GPU or CPU itself based on the monitored voltage and current parameters provided to the GPU or CPU and the voltage and current parameters of each power module in the GPU processing system or the CPU processing system; for example, whether each power module and the GPU or CPU itself is in high power consumption, low power consumption, or normal power consumption;

[0053] Correspondingly, based on the target result, the regulator is controlled to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains the change of the first target indicator parameter. The second logic and calculation unit can control the target sub-regulator in the regulator according to whether each power module and the GPU or CPU itself is in high power consumption, low power consumption or normal power consumption to adjust the voltage or current parameters provided to the GPU or CPU, so that the power consumption parameters obtained in the first logic unit change.

[0054] In a third possible implementation, the second logic and calculation unit calculates the target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit. The second logic and calculation unit may be based on the monitored voltage and current parameters provided to the GPU or CPU at the same time; and calculates the power consumption status of each power module in the GPU or CPU system and the GPU or CPU itself according to the voltage and current parameters of each power module in the GPU processing system or the CPU processing system, and calculates the temperature status of each power module in the GPU or CPU system and the GPU or CPU itself based on the monitored temperature parameters; in a case where the determined power consumption status corresponds to the temperature status, any state of the power consumption status or the temperature status is determined as the target result; in a case where the determined power consumption status does not correspond to the temperature status, the determined temperature parameter state is determined as the target result.

[0055] It can be understood that, in the implementation method in which the second logic and calculation unit calculates the target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit, since the monitored second target parameter and the first target parameter provided to the target processing unit are both performed in real time, the determined target result also changes dynamically in real time. In the implementation manner of the present application, the target result can be calculated by the second logic and calculation unit based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit, and then the regulator is controlled based on the target result to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains a change in the first target indicator parameter, and the target processing unit can further adjust its own indicator parameter in response to the change in the first target indicator parameter, so that the target processor unit operates at a suitable target indicator parameter.

[0056] Figure 4 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 4 As shown, the implementation process of the processing method includes:

[0057] Step S401: a first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0058] Step S402: The second logic and calculation unit obtains a second target parameter and a first parameter threshold corresponding to the second target parameter; compares the second target parameter with the first parameter threshold to obtain a first comparison result; determines the first comparison result as the target result; and controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains the change in the first target indicator parameter.

[0059] Here, the second target parameter may include multiple parameters; correspondingly, the first parameter threshold includes the threshold of each parameter in the multiple parameters. The threshold of each parameter may be the same or different.

[0060] It is understood that the first parameter threshold may represent a normal parameter value range for each parameter in the second target parameter. The first comparison result may be that the second target parameter is within the parameter range corresponding to the first parameter threshold; or that the second target parameter is lower than each threshold in the first parameter threshold; or that the second target parameter is higher than each threshold in the first parameter threshold.

[0061] In some possible implementations, the second logic and calculation unit obtains the second target parameter and the first parameter threshold corresponding to the second target parameter, and the second logic and calculation unit may obtain each parameter in the second target parameter and the parameter threshold corresponding to each parameter.

[0062] In one embodiment, comparing the second target parameter with the first parameter threshold to obtain the first comparison result may be comparing each parameter in the second target parameter with the corresponding parameter threshold to determine whether each parameter is within the corresponding parameter threshold.

[0063] In the embodiment of the present application, by comparing the second target parameter with the first parameter threshold corresponding to the second target parameter, it can be determined whether the second target parameter is within the first parameter threshold range, which is conducive to adjusting the first target parameter.

[0064] Figure 5 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 5 As shown, the implementation process of the processing method includes:

[0065] Step S501: A first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state; a power supply of the target processing unit includes at least one power module;

[0066] In some possible implementations, the target processing unit may be a GPU; the power supply of the target processing unit includes a core power module and a memory power module.

[0067] In some other possible implementations, the target processing unit may be a CPU; and the power supply of the target processing unit may include a VR.

[0068] Step S502: The second logic and calculation unit obtains a second target parameter and a first parameter threshold corresponding to the second target parameter; the second target parameter includes the temperature value of the target processing unit and the temperature value of each of the power modules; the first parameter threshold includes the first temperature value range of the target processing unit and the second temperature value range of the corresponding power module; compares the temperature value of the target processing unit with the first temperature value range of the target processing unit to obtain a first sub-result; compares the temperature value of each of the power modules with the second temperature value range of the corresponding power modules to obtain a second sub-result; determines the first sub-result and the second sub-result as a first comparison result; determines the first comparison result as the target result; controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter.

[0069] It can be understood that, when the first target indicator parameter is power consumption, the second target parameter may be a temperature parameter that is positively correlated with power consumption.

[0070] In an embodiment of the present application, the temperature value of the target processing unit is compared with the first temperature value range of the target processing unit to obtain a first sub-result; the temperature value of each power module is compared with the second temperature value range of the corresponding power module to obtain a second sub-result; the first comparison result and the second comparison result are determined as the target results. In this way, it can be accurately determined whether each parameter in the second target parameter is within the corresponding parameter threshold range, which is conducive to the adjustment of the first target parameter.

[0071] In some possible implementations, the first sub-result includes at least a target processing unit low temperature, a target processing unit normal temperature, and a target processing unit high temperature;

[0072] The comparing the temperature value of the target processing unit with the first temperature value range to obtain the first sub-result may be, when the temperature value of the target processing unit is within the first temperature value range, determining that the first sub-result is that the temperature of the target processing unit is normal; when the temperature value of the target processing unit is lower than the lowest temperature value in the first temperature value range, determining that the first sub-result is that the temperature of the target processing unit is low; when the temperature value of the target processing unit is higher than the highest temperature value in the first temperature value range, determining that the first sub-result is that the temperature of the target processing unit is high.

[0073] Figure 6 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 6 As shown, the implementation process of the processing method includes:

[0074] Step S601: A first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0075] Step S602: The second logic and calculation unit obtains a second target indicator parameter through the first target parameter of the target processing unit; obtains a second parameter threshold corresponding to the second target indicator parameter; compares the second target indicator parameter with the second parameter threshold to obtain a second comparison result; determines the second comparison result as the target result; and controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit so that the first logic unit obtains a change in the first target indicator parameter.

[0076] Here, the second target indicator parameter may also be power consumption; the second target indicator parameter may have the same parameter value as the first target indicator parameter, the difference being that the second target indicator parameter is obtained by the second logic and calculation unit, while the first target indicator parameter is obtained by the first logic unit.

[0077] In a possible implementation, the second parameter threshold corresponding to the second target indicator parameter may be a power consumption threshold.

[0078] In some possible implementations, the second target indicator parameter is compared with the second parameter threshold to obtain a second comparison result; determining the second comparison result as the target result may be determining whether the second target indicator parameter is within a parameter range corresponding to the second parameter threshold, and determining the determined result as the target result. For example, the second logic and calculation unit compares the power consumption of each power module with the corresponding power consumption threshold, and compares the power consumption of the GPU or CPU with the corresponding power consumption threshold based on the power consumption of each power module and the GPU or CPU itself in the GPU or CPU system and the power consumption threshold of each power module and the power consumption threshold of the GPU or CPU itself, thereby determining whether each power module and the UDP or CPU itself is in high power consumption, low power consumption, or normal power consumption.

[0079] In an embodiment of the present application, the second logic and calculation unit determines the second comparison result obtained by comparing the second target indicator parameter and the corresponding second parameter threshold as the target result. In this way, the second target indicator parameter can represent the target result, which is conducive to the adjustment of the first target parameter.

[0080] Figure 7 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 7 As shown, the implementation process of the processing method includes:

[0081] Step S701: A first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state; a power supply of the target processing unit includes at least one power module;

[0082] Here, the first target parameter includes at least the voltage value of the target processing unit and each of the power modules.

[0083] Step S702: The second logic and calculation unit obtains a second target indicator parameter through the first target parameter of the target processing unit; obtains a second parameter threshold corresponding to the second target indicator parameter; the second target indicator parameter includes the power consumption value of the target processing unit and each of the power modules; the second parameter threshold includes the first power consumption value range of the target processing unit and the second power consumption value range of each of the power modules; compares the power consumption value of the target processing unit with the first power consumption value range to obtain a third sub-result; compares the power consumption value of each of the power modules with the second power consumption value range of the corresponding power modules to obtain a fourth sub-result; determines the third sub-result and the fourth sub-result as a second comparison result; determines the second comparison result as the target result; controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains a change in the first target indicator parameter.

[0084] In an embodiment of the present application, the power consumption value of the target processing unit is compared with the first power consumption value range to obtain a third sub-result; the power consumption value of each power module is compared with the second power consumption value range of the corresponding power module to obtain a fourth sub-result; the third sub-result and the fourth sub-result are determined as target results. In this way, it is possible to accurately determine whether each indicator parameter in the second target indicator parameter is within the corresponding parameter threshold range, which is conducive to the adjustment of the first target parameter.

[0085] In some possible implementations, the third sub-result includes at least: low power consumption of the target processing unit, normal power consumption of the target processing unit, and high power consumption of the target processing unit; the comparison of the power consumption value of the target processing unit with the first power consumption value range to obtain the third sub-result may be, when the power consumption value of the target processing unit is within the first power consumption value range, determining that the third sub-result is normal power consumption of the target processing unit; when the power consumption value of the target processing unit is lower than the lowest power consumption value in the first power consumption value range, determining that the third sub-result is low power consumption of the target processing unit; when the power consumption value of the target processing unit is higher than the highest power consumption value in the first power consumption value range, determining that the third sub-result is high power consumption of the target processing unit.

[0086] Figure 8 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 8 As shown, the implementation process of the processing method includes:

[0087] Step S801: a first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0088] Step S802: The second logic and calculation unit calculates the first target result based on monitoring the second target parameter; calculates the second target result by monitoring the first target parameter provided to the target processing unit; when the first target result corresponds to the second target result, determines the first target result or the second target result as the target result; when the first target result does not correspond to the second target result, determines the first target result as the target result; controls the regulator based on the target result to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter.

[0089] In an embodiment of the present application, a first target result is calculated based on monitoring a second target parameter; a second target result is calculated by monitoring the first target parameter provided to the target processing unit; when the first target result corresponds to the second target result, the first target result or the second target result is determined as the target result; when the first target result does not correspond to the second target result, the first target result is determined as the target result, so that the determined target result is more accurate.

[0090] Figure 9 A schematic diagram of the implementation flow of another processing method provided in the embodiment of the present application is shown as follows: Figure 9 As shown, the implementation process of the processing method includes:

[0091] Step S901: a first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0092] Step S902: The second logic and calculation unit calculates the target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; obtains the correspondence between the target result and the sub-regulator and the adjustment ratio; determines at least one sub-regulator corresponding to the target result and the target adjustment ratio corresponding to each sub-regulator from the correspondence; controls the corresponding sub-regulator through the target adjustment ratio to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter.

[0093] It is understandable that the target adjustment ratio corresponding to the target result can be different adjustment ratios set for different target results; of course, in the case where the regulator corresponding to the target result includes multiple sub-regulators, each target result can correspond to the adjustment ratio of each sub-regulator. For example, for the case where the target result is a high temperature of the GPU, a normal temperature of the first power module, and a high temperature of the second power module, the adjustment ratio corresponding to the first sub-regulator (corresponding to the GPU) among the multiple sub-regulators can be 1.5, and the adjustment ratio corresponding to the second sub-regulator (corresponding to the second power module) among the multiple sub-regulators can be 1.5 or 2. For the case where the target result is a high power consumption of the GPU, a normal power consumption of the first power module, and a low power consumption of the second power module, the adjustment ratio of the first sub-regulator (corresponding to the GPU) among the multiple sub-regulators can be 2, and the adjustment ratio corresponding to the second sub-regulator (corresponding to the second power module) among the multiple sub-regulators can be 0.5.

[0094] In some possible implementations, a correspondence between each target result, a sub-regulator, and an adjustment ratio may be pre-established, as shown in Table 1 below:

[0095] Table 1

[0096]

[0097]

[0098] Here, Table 1 may be pre-stored in the second logic and calculation unit so that the second logic and calculation unit can directly obtain each sub-regulator and the adjustment ratio of each sub-regulator corresponding to the real-time target result by querying Table 1.

[0099] In an embodiment of the present application, by obtaining the correspondence between the target result and the sub-regulator and the adjustment ratio, at least one sub-regulator corresponding to the target result and the target adjustment ratio corresponding to each sub-regulator are determined from the correspondence; then, the corresponding sub-regulator can be controlled by the target adjustment ratio to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter; in this way, accurate adjustment of the first target indicator parameter can be achieved, so that the target processing unit can further adjust its own indicator parameters in response to the change of the first target indicator parameter, so that the target processor unit operates at a suitable target indicator parameter.

[0100] Figure 10 A schematic diagram of the structure of a GPU system provided in an embodiment of the present application is shown in FIG. Figure 10As shown, the GPU system includes: a power supply 1000, a core power module (Core power) 1001, a memory power module (Vram power) 1002, a first temperature sensor 1003, a second temperature sensor 1004, an artificial intelligence (AI) chip 1005, a power consumption acquisition chip 1006, a first voltage regulator 1007, a second voltage regulator 1008, a GPU 1009, a fifth resistor R5, and a sixth resistor R6;

[0101] R6 is connected in series between the output of the power supply 1000 and the input of the Core power 1001; R5 is connected in series between the common node of R6 and the Core power 1001 and the input of the VRAM power 102; the power supply 1000 is used to provide power to the Core power 1001 and the VRAM power 1002; the outputs of the Core power 1001 and the VRAM power 1002 are connected to the first power input and the second power input of the GPU 1009 respectively;

[0102] The first input terminal of the power consumption acquisition chip 1006 is connected to the common node of R5 and Vram power 1002; the second input terminal of the power consumption acquisition chip 1006 is connected to the common node of Core power 1001 and R6; the third input terminal of the power consumption acquisition chip 1006 is connected to the signal output terminal of the first voltage regulator 1007; the signal input terminal of the first voltage regulator 1007 is connected to the common node of Core power 1001 and R5; the control signal terminal of the first voltage regulator 1007 is connected to the control output terminal of the AI ​​chip 1005; the fourth input terminal of the power consumption acquisition chip 1006 is connected to R6 and Core power 1001; the fifth input terminal of the power consumption acquisition chip 1006 is connected to the common node of the power supply 1000 and R6; the sixth input terminal of the power consumption acquisition chip 1006 is connected to the signal output terminal of the second voltage regulator 1008; the signal input terminal of the second voltage regulator 1008 is connected to the common node of the power supply 1000 and R6; the control signal terminal of the second voltage regulator 1008 is connected to the control output terminal of the AI ​​chip 1005; the output terminal of the power consumption acquisition chip 1006 is connected to the power consumption signal input terminal of the GPU; the power consumption acquisition chip 1006 is used to collect the power consumption values ​​of Corepower 1001, Vram power 1002 and GPU 1009, and output the power consumption values ​​of Corepower 1001, Vram power1002 and GPU 1009 to GPU 1009;

[0103] The first input terminal of the AI ​​chip 1005 is connected to the common node of R5 and Vram power 1002; the second input terminal of the AI ​​chip 1005 is connected to the common node of Core power 1001 and R6; the third input terminal of the AI ​​chip 1005 is connected to the common node of R6 and Corepower 1001; the fourth input terminal of the AI ​​chip 1005 is connected to the common node of the power supply 1000 and R6; the fifth input terminal of the AI ​​chip 1005 is connected to the temperature signal output terminal of the first temperature sensor 1003 and the second temperature sensor 1004; the sixth input terminal of the AI ​​chip 1005 is connected to the temperature signal input terminal of the GPU; the AI ​​chip 1005 is used to determine the power consumption state and / or temperature state of Core power 1001, Vram power 1002 and GPU 1009 based on the detected voltage signal and temperature signal, and the preset power consumption threshold and temperature threshold; based on Core power 1001, Vram power 1002 and GPU The power consumption state and / or temperature state of 1009 generates a control signal to control the first voltage regulator 1007 and / or the second voltage regulator 1008 to control the voltage signals at the third input terminal and the sixth input terminal of the power consumption acquisition chip 1006, thereby controlling the power consumption signal output by the power consumption acquisition chip 1006 to the GPU 1009.

[0104] In the embodiment of the present application, after the system is working, the power provided by Core power 1001 and VRAM power 1002 enters GPU 1009. At this time, the power consumption acquisition chip 1006 continuously captures the total graph power (TGP) and the power consumption information of VRAM power 1002.

[0105] 2) The GPU reads the TGP and VRAM power 1002 power consumption information in the power consumption acquisition chip 1006 and compares it with its own set power consumption value M. When TGP is less than M, the GPU increases its own load to control the power consumption to M;

[0106] 3) AI chip 1005 reads the temperature sensor;

[0107] The AI ​​chip 1005 reads the temperature data of the Core power 1001, VRAM power 1002, and GPU 1009 through the first temperature sensor 1003, the second temperature sensor 1004, and the GPU 1009, respectively, and then performs logical processing;

[0108] ① If the component temperatures of GPU 1009, Core power 1001, and VRAM power 1002 are all lower than the set value N, AI chip 1005 will adjust the voltage regulation value of the second voltage regulator (the voltage regulator corresponding to TGP) 1008 so that the data read by GPU 1009 on power consumption acquisition chip 1006 is lower than the actual value. GPU 1009 will then adjust its own power consumption to achieve optimal performance.

[0109] ② When the GPU 1009 temperature is normal, the Core power 1001 component temperature is too high, and the VRAM power 1002 temperature is low, the AI ​​chip 1005 will adjust the voltage regulation value of the first voltage regulator (the voltage regulator corresponding to VRAM power 1002) 1007 so that the GPU 1009 reads a low VRAM power 1002 data. The GPU 1009 will automatically increase the power consumption of VRAM power 1002 and reduce the power consumption of Core power 1001, so that the temperature of each component operates within its own reasonable range;

[0110] According to the above logic, multiple adjustments are automatically made to enable the system to run at optimal performance while ensuring that the component temperature does not exceed the standard.

[0111] Figure 11 A schematic diagram of the structure of a CPU processing system provided in an embodiment of the present application is shown in FIG. Figure 11 As shown, the CPU processing system includes: a power supply 1101, a VR 1102, a CPU 1103, an AI chip 1104, a voltage regulating unit 1105, a third temperature sensor 1006 and a seventh resistor R7;

[0112] Among them, R7 is connected in series between the power output end of the power supply 1101 and the power input end of the VR 1102; the voltage regulating unit 1105 is connected in series between the ground end and the Imon pin of the VR 1102; the control input end of the voltage regulating unit 1105 is connected to the control output end of the AI ​​chip 1104; the voltage regulating unit 1105 is used to adjust the voltage on the Imon pin in response to the control signal of the AI ​​chip 1104 to change the system power consumption; the power output end of the VR 1102 is connected to the power input end of the CPU 1103; the communication protocol signal end of the VR 1102 is connected to the signal receiving end of the CPU 1103; the first input end of the AI ​​chip 1104 is connected to the common node of R7 and VR 1102; the second input end of the AI ​​chip 1104 is connected to the common node of the power supply 1101 and R7; the third input end of the AI ​​chip 1104 is connected to the third temperature sensor 1006; the fourth input end of the AI ​​chip 1104 is connected to the temperature signal output end of the CPU 1103; the AI ​​chip 1104 is used to monitor the CPU 1103 power consumption and temperature, the temperature of VR 1102, based on the power consumption and temperature of CPU 1103, the temperature of VR 1102, generates a control signal to adjust the voltage regulation unit 1105, so as to adjust the voltage on the Imon pin of VR 1102.

[0113] For CPU processing system:

[0114] 1) The CPU 1103 is powered on and uses Serial Voltage Identification (SVID) to set the output voltage information and read data such as maximum power consumption.

[0115] 2) AI chip 1104 monitors the temperature of VR 1102 components and CPU 1103 in real time. If, under certain performance scenarios, the CPU 1103 temperature reading from AI chip 1104 does not reach the maximum set value, the voltage regulator 1105 will reduce the voltage. This will cause the CPU 1103 to read a low value, and the CPU 1103 load will be increased to achieve optimal performance.

[0116] 3) When AI chip 1104 detects that VR 1102 or CPU 1103 is overheating, AI chip 1104 increases the voltage of voltage regulator 1105. CPU 1103 reads that the set upper power consumption limit is too high, and CPU 1103 reduces the load, thereby reducing the component temperature.

[0117] Based on the above embodiments, the present application also provides a processing system, such as Figure 12 As shown, the processing system 1200 includes:

[0118] A first logic unit 1201 is configured to obtain a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state;

[0119] A second logic and calculation unit 1202 is configured to calculate a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; and control the regulator 1203 based on the target result;

[0120] The regulator 1203 is configured to adjust the first target parameter provided to the target processing unit 1204 in response to control of the second logic and calculation unit;

[0121] The first logic unit 1201 is configured to obtain a change in the first target indicator parameter in response to the regulator 1203 adjusting the first target parameter provided to the target processing unit 1204;

[0122] The target processing unit 1204 is configured to adjust its own indicator parameters in response to a change in the first target indicator parameter.

[0123] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0124] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0125] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0126] The features disclosed in the various method or system embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or system embodiments.

[0127] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned implementation methods. The above-mentioned implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A processing method, characterized in that: The method comprises: The first logic unit obtains a first target indicator parameter by monitoring a first target parameter provided to the target processing unit, where the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state; a second logic and calculation unit calculating a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; controlling at least one sub-regulator based on the target result to adjust the first target parameter provided to the target processing unit, wherein there is a corresponding relationship between the target result, the sub-regulator, and the adjustment ratio; Determine, from the corresponding relationship, at least one sub-regulator corresponding to the target result and a target adjustment ratio corresponding to each sub-regulator; The corresponding sub-regulator is controlled to adjust the target adjustment ratio to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter.

2. The method according to claim 1, characterized in that The second logic and calculation unit calculates a target result by monitoring the second target parameter, including: The second logic and calculation unit obtains a second target parameter and a first parameter threshold corresponding to the second target parameter; comparing the second target parameter with the first parameter threshold to obtain a first comparison result; The first comparison result is determined as the target result.

3. The method according to claim 2, characterized in that The power supply of the target processing unit includes at least one power module, the second target parameter includes a temperature value of the target processing unit and a temperature value of each of the power modules; the first parameter threshold includes a first temperature value range of the target processing unit and a second temperature value range of each of the power modules; The comparing the second target parameter with the first parameter threshold to obtain a first comparison result includes: comparing the temperature value of the target processing unit with the first temperature value range to obtain a first sub-result; comparing the temperature value of each power module with a corresponding second temperature value range of the power module to obtain a second sub-result; The first sub-result and the second sub-result are determined as the first comparison result.

4. The method according to claim 3, characterized in that The first sub-result includes at least a target processing unit low temperature, a target processing unit normal temperature, and a target processing unit high temperature; The comparing the temperature value of the target processing unit with the first temperature value range to obtain a first sub-result includes: If the temperature value of the target processing unit is within the first temperature value range, determining the first sub-result as indicating that the temperature of the target processing unit is normal; When the temperature value of the target processing unit is lower than the lowest temperature value in the first temperature value range, determining the first sub-result as a low temperature of the target processing unit; When the temperature value of the target processing unit is higher than the highest temperature value in the first temperature value range, the first sub-result is determined to be a high temperature of the target processing unit.

5. The method according to claim 1, wherein The second logic and calculation unit calculates a target result by monitoring the first target parameter provided to the target processing unit, including: The second logic and calculation unit obtains a second target indicator parameter through the first target parameter of the target processing unit; Obtaining a second parameter threshold corresponding to the second target indicator parameter; Comparing the second target indicator parameter with the second parameter threshold to obtain a second comparison result; The second comparison result is determined as the target result.

6. The method according to claim 5, characterized in that The power supply of the target processing unit includes at least one power module; the second target indicator parameter includes the power consumption value of the target processing unit and each of the power modules; the second parameter threshold includes a first power consumption value range of the target processing unit and a second power consumption value range of each of the power modules; The comparing the second target indicator parameter with the second parameter threshold to obtain a second comparison result includes: comparing the power consumption value of the target processing unit with the first power consumption value range to obtain a third sub-result; comparing the power consumption value of each of the power modules with the corresponding second power consumption value range of the power module to obtain a fourth sub-result; The third sub-result and the fourth sub-result are determined as the second comparison result.

7. The method according to claim 6, characterized in that The third sub-result includes at least: the target processing unit has low power consumption, the target processing unit has normal power consumption, and the target processing unit has high power consumption; The comparing the power consumption value of the target processing unit with the first power consumption value range to obtain a third sub-result includes: If the power consumption value of the target processing unit is within the first power consumption value range, determining the third sub-result as normal power consumption of the target processing unit; When the power consumption value of the target processing unit is lower than the lowest power consumption value in the first power consumption value range, determining the third sub-result as low power consumption of the target processing unit; When the power consumption value of the target processing unit is higher than the highest power consumption value in the first power consumption value range, the third sub-result is determined to be high power consumption of the target processing unit.

8. A processing system, characterized in that The system comprises: a first logic unit, configured to obtain a first target indicator parameter by monitoring a first target parameter provided to a target processing unit, wherein the first target indicator parameter is used to indicate a target performance of the target processing unit in a computing state; a second logic and calculation unit, configured to calculate a target result based on monitoring the second target parameter and / or by monitoring the first target parameter provided to the target processing unit; and control at least one sub-regulator based on the target result; wherein a corresponding relationship exists between the target result, the sub-regulator, and the adjustment ratio; A target processing unit is used to control at least one sub-regulator based on the target result to adjust the first target parameter provided to the target processing unit, and there is a corresponding relationship between the target result, the sub-regulator, and the adjustment ratio; it is also used to determine at least one sub-regulator corresponding to the target result and the target adjustment ratio corresponding to each sub-regulator from the corresponding relationship; control the corresponding sub-regulator to adjust the target adjustment ratio to adjust the first target parameter provided to the target processing unit, so that the first logic unit obtains the change of the first target indicator parameter.

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