A method and system for accelerating a radio astronomy correlator based on FPGA

Abstract

The present invention discloses a method and system for accelerating a radio astronomy cross-correlator based on FPGA, which relates to the field of radio astronomy. The technical solution provided by the present invention is used for the cross-correlation operation of radio array signals, stores antenna signal data on-chip and performs multi-channel segmentation in the time window dimension to achieve multi-channel parallel accumulation, improve the calculation efficiency, and adopts a streaming transmission structure and a method for reducing the data storage amount to enhance the scalability.

Description

Technical Field

[0001] The present invention relates to the field of radio astronomy, and specifically relates to a method and system for accelerating a radio astronomy cross-correlator based on FPGA.

Background Art

[0002] In the field of radio astronomy, radio interferometry is widely used to measure radio astronomy data. However, this method is a computationally intensive application, involving the processing of ultra-large-scale numbers in a short period of time. With the expansion of the scale of the antenna receiving array, the demand for high-speed data processing is becoming increasingly strong.

[0003] In the prior art, the correlator is designed using ASIC (Application Specific Integrated Circuit) hardware, or some specific boards are used in a set of overall determined antenna arrays, such as ROACH or ROACH2. The development cycle of these circuits is long, and the robustness to changes in different data streams and the number of antenna arrays is relatively poor. Currently, there are also studies on correlator designs based on GPUs, such as using mature linear operation libraries such as the cuBLAS library to accelerate operations, but there will be higher energy consumption.

Summary of the Invention

[0004] To solve the foregoing problems, the present invention proposes a method for accelerating a radio astronomy cross-correlator based on FPGA, which is used for the cross-correlation operation of radio array signals to improve the calculation efficiency and reduce the data storage amount.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for accelerating a radio astronomy cross-correlator based on FPGA, the radio astronomy cross-correlator acceleration method comprising the following steps:

[0007] The on-chip processor receives the antenna signal data of each antenna station and transmits the antenna signal data to the on-chip cross-correlation operation engine; the antenna signal data is data with F frequency points, S antenna numbers, T clock windows, and a polarization direction of 2.

[0008] The on-chip cross-correlation operation engine performs a cross-correlation operation on the antenna signal data to generate output values of the cross-correlation operation between two antenna stations, and transmits the output values to the on-chip processor.

[0009] The on-chip processor transmits the output values to the host computer.

[0010] Optionally, the on-chip cross-correlation operation engine includes an interface module and a cross-correlation operation processing architecture.

[0011] The interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, and transmit the output value to the on-chip processor;

[0012] The cross-correlation operation processing architecture includes:

[0013] A data receiving end, which is used to receive the antenna signal data packed by the interface module;

[0014] A cross-correlation operation structure, which is used to calculate the auto-correlation and cross-correlation operations of the antenna signal data between two antenna sites and generate an output value;

[0015] A data sending end, which is used to transmit the output value to the interface module.

[0016] Optionally, the cross-correlation operation structure includes:

[0017] An on-chip data segmentation module, which is used to segment the read antenna signal data;

[0018] An antenna storage sequence number calculation module, which is used to calculate the antenna storage sequence number for the segmented antenna signal data;

[0019] A first cross-correlation operation structure, when all the received antenna signal data can be stored in the on-chip memory, stores all the received antenna signal data in the on-chip memory, and then performs the cross-correlation and auto-correlation calculations of the antenna sites to form an output value;

[0020] A second cross-correlation operation structure, when all the received antenna signal data cannot be stored in the on-chip memory, receives the antenna signal data in batches, performs the cross-correlation and auto-correlation calculations of the received antenna signal data for the antenna sites, and accumulates the results to form an output value.

[0021] Optionally, the antenna storage sequence number calculation module calculates the antenna storage sequence number for the segmented antenna signal data in the form of a look-up table, and the antenna storage sequence number corresponds to the loop parameter one by one.

[0022] Optionally, the first cross-correlation operation structure includes:

[0023] A time window segmentation module, which parallelizes several channels for the time window and calculates the cross-multiplication of the several time windows in one clock cycle.

[0024] A segmented window integration module, which accumulates and integrates the cross-multiplication results of the several time windows to form the output value.

[0025] Optionally, the second cross-correlation operation structure includes a multiplication module and an addition module. The second cross-correlation operation structure performs hierarchical processing on the multiplication module and the addition module. When performing operations, it includes the following steps:

[0026] Adjust the input order of the antenna signal data. Receive the antenna signal data of all antenna sites in one clock window at one frequency point in each batch, and the multiplication module calculates the current cross-correlation and auto-correlation results;

[0027] The addition module accumulates the cross-correlation and auto-correlation results of the antenna signal data in each batch;

[0028] Loop through the above steps until all the antenna signal data in all clock windows at all frequency points are received and calculated, and all the cross-correlation and auto-correlation results are accumulated to form the output value.

[0029] Optionally, the on-chip data segmentation module segments the read antenna signal data including the following steps:

[0030] Select a pair of antenna unit data from the input antenna signal data, and the antenna unit data includes two sets of floating-point complex numbers;

[0031] Segment the one-dimensional vector stored on the chip again and split it into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna serial number, T is the clock window, X is the component of the antenna unit data on the X-axis, Y is the component of the antenna unit data on the Y-axis, R is the component of the antenna unit data on the R-axis, and I is the component of the antenna unit data on the I-axis. Fully expand the last two dimensions and read four data in parallel each time;

[0032] Calculate the multiplication and addition results of eight data in parallel.

[0033] Optionally, the on-chip processor includes a host computer sending and receiving end. The received antenna signal data and the output value are sent to the host computer through the host computer sending and receiving end, and the host computer sending and receiving end packs the antenna signal data in the overall format of time window order - frequency point order - antenna serial number order - polarization direction order.

[0034] Optionally, the data receiving end unpacks the antenna signal data packed by the interface module. The unpacking bit width is an integer multiple of 32, and the unpacked antenna signal data is stored in matrix format or FIFO stream data.

[0035] Optionally, the data sending end packs the output value generated by the cross-correlation operation structure according to the unpacking bit width and sends it to the interface module.

[0036] The present invention has the following beneficial effects:

[0037] The present invention designs relevant operation structures in a combination of software and hardware, allocates hardware resources by software methods, has high parallelism, fast operation speed, and fast deployment; the data is based on 32-bit floating-point data, and the IP module is designed using the Xilinx HLS high-level synthesis tool, which can be configured on boards with different resources according to different requirements. Moreover, the present invention adopts configurable parameter design, can perform relevant operations for different numbers of antennas, effectively improves the calculation efficiency, and reduces the power consumption. At the same time, the present invention adopts a streaming transmission structure, which increases the expandability of the subsequent cross-correlator.

[0038] In addition, the present invention also provides a radio astronomy cross-correlator acceleration system based on FPGA, and the radio astronomy cross-correlator acceleration system includes an on-chip processor and an on-chip cross-correlation operation engine;

[0039] The on-chip processor receives the antenna signal data of each antenna site and transmits the antenna signal data to the on-chip cross-correlation operation engine; the antenna signal data is data with F frequency points, S antenna serial numbers, T clock windows, and a polarization direction of 2;

[0040] The on-chip cross-correlation operation engine performs cross-correlation operations on the antenna signal data to generate output values of the cross-correlation operations between two antenna sites, and transmits the output values to the on-chip processor;

[0041] The on-chip processor transmits the output values to the host computer through the serial port.

[0042] Optionally, the on-chip cross-correlation operation engine includes an interface module and a cross-correlation operation processing architecture,

[0043] The interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, and transmit the output values to the on-chip processor;

[0044] The cross-correlation operation processing architecture includes:

[0045] A data receiving end, which is used to receive the antenna signal data packed by the interface module;

[0046] A cross-correlation operation structure, which is used to calculate the autocorrelation and cross-correlation operations of the antenna signal data between two antenna sites and generate output values;

[0047] A data sending end, which is used to transmit the output values to the interface module.

[0048] Optionally, the cross-correlation operation structure includes:

[0049] An on-chip data segmentation module, which is used to segment the read antenna signal data;

[0050] An antenna storage sequence calculation module is used to calculate the antenna storage sequence for the segmented antenna signal data;

[0051] A first cross-correlation operation structure, when all the received antenna signal data can be stored in the on-chip memory, stores all the received antenna signal data in the on-chip memory, and then performs cross-correlation and auto-correlation calculations on the antenna stations to form an output value;

[0052] A second cross-correlation operation structure, when all the received antenna signal data cannot be stored in the on-chip memory, receives the antenna signal data in batches, performs cross-correlation and auto-correlation calculations on the received antenna signal data, and accumulates the results to form an output value.

[0053] Optionally, the antenna storage sequence calculation module calculates the antenna storage sequence for the segmented antenna signal data by using a look-up table, and the antenna storage sequence corresponds one-to-one with the loop parameter.

[0054] Optionally, the first cross-correlation operation structure includes:

[0055] A time window segmentation module that parallelizes several channels of the time window and calculates the cross multiplication of the several channels of time windows in one clock cycle.

[0056] A segmented window integration module that accumulates and integrates the cross multiplication results of the several channels of time windows to form the output value.

[0057] Optionally, the second cross-correlation operation structure includes a multiplication module and an addition module. The second cross-correlation operation structure processes the multiplication module in a hierarchical manner. The second cross-correlation operation structure adjusts the input order of the antenna signal data, receives one copy of the antenna signal data of all antenna stations in one clock window at one frequency point in each batch, and the multiplication module calculates the current cross-correlation and auto-correlation results; the addition module accumulates the cross-correlation and auto-correlation results of each batch of antenna signal data, and loops until all the antenna signal data of all clock windows at all frequency points are received and calculated, and all the cross-correlation and auto-correlation results are accumulated to form an output value.

[0058] Optionally, when the on-chip data segmentation module segments the read antenna signal data, a pair of antenna unit data is selected from the input antenna signal data, and the antenna unit data includes two sets of floating-point complex numbers; the one-dimensional vector stored on the chip is segmented again and split into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna serial number, T is the clock window, X is the component of the antenna unit data on the X-axis, Y is the component of the antenna unit data on the Y-axis, R is the component of the antenna unit data on the R-axis, and I is the component of the antenna unit data on the I-axis. The last two dimensions are fully expanded, and four data are read in parallel each time; the multiplication and addition results of eight data are calculated in parallel.

[0059] Optionally, the on-chip processor includes a host computer sending and receiving end. The received antenna signal data and the output value are sent to the host computer through the host computer sending and receiving end. The host computer sending and receiving end packs the antenna signal data in the overall format of time window sequence - frequency point sequence - antenna serial number sequence - polarization direction sequence.

[0060] Optionally, the data receiving end unpacks the antenna signal data packed by the interface module. The unpacking bit width is an integer multiple of 32, and the unpacked antenna signal data is stored in matrix format or FIFO stream data.

[0061] Optionally, the data sending end packs the output value generated by the cross-correlation operation structure according to the unpacked bit width and then sends it to the interface module.

[0062] The beneficial effects of the radio astronomy cross-correlator acceleration system based on FPGA provided by the present invention are similar to those of the aforementioned radio astronomy cross-correlator acceleration method based on FPGA, and will not be elaborated here.

[0063] These features and advantages of the present invention will be disclosed in detail in the following specific embodiments. The best embodiments or means of the present invention are not limitations to the technical solutions of the present invention. In addition, these features, elements, and components appear multiple times below, and different symbols or numbers are marked for convenience of representation, but all represent components with the same or similar structures or functions.

Specific Embodiments

[0064] Next, the technical solutions of the embodiments of the present invention will be explained and described. However, the following embodiments are only the preferred embodiments of the present invention, not all of them. Based on the embodiments in the embodiments, other embodiments obtained by those skilled in the art without creative work all fall within the protection scope of the present invention.

[0065] As used herein, the phrase "one embodiment" or "example" or "instance" means that a particular feature, structure, or characteristic described in connection with the embodiment itself may be included in at least one embodiment of the present patent disclosure. The appearances of the phrase "in one embodiment" in various places in the specification do not necessarily all refer to the same embodiment.

[0066] Embodiment 1:

[0067] This embodiment provides a method for accelerating a radio astronomy cross-correlator based on FPGA. The method for accelerating the radio astronomy cross-correlator includes the following steps:

[0068] Data reception step: The on-chip processor receives the antenna signal data of each antenna site.

[0069] In this step, the on-chip processor includes a host computer sending and receiving end. The antenna signal data is data with F frequency points, S antenna numbers, T clock windows, and a polarization direction of 2. Each antenna site has several receiving points for receiving antenna signals. The antenna signal data received by all receiving points of each antenna site forms an antenna signal data array. In this embodiment, the data is based on 32-bit floating-point data, and an IP module is designed using the Xilinx HLS high-level synthesis tool, which can be configured on boards with different resources according to different requirements.

[0070] Data calculation step: The on-chip processor transmits the received antenna signal data to the on-chip cross-correlation operation engine, and the on-chip cross-correlation operation engine performs cross-correlation operations on the antenna signal data to generate output values of the cross-correlation operations between every two antenna sites.

[0071] In this step, the on-chip cross-correlation operation engine includes an interface module and a cross-correlation operation processing architecture. The interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, with the packed bit width being an integer multiple of 32, and transmit the output value to the on-chip processor. The cross-correlation operation processing architecture includes a data reception end, a cross-correlation operation structure, and a data transmission end. The data reception end is used to receive the antenna signal data packed by the interface module and unpack it, with the unpacked bit width being an integer multiple of 32. The unpacked antenna signal data is stored in matrix format or FIFO stream data; the cross-correlation operation structure is used to calculate the autocorrelation and cross-correlation operations of the antenna signal data between every two antenna sites to generate output values; the data transmission end is used to pack the output values generated by the cross-correlation operation structure according to the unpacked bit width and then transmit them to the interface module.

[0072] The cross-correlation operation structure includes an on-chip data segmentation module, an antenna storage sequence number calculation module, a first cross-correlation operation structure, and a second cross-correlation operation structure.

[0073] The on-chip data segmentation module is used to segment the input antenna signal data, and the number of segments is the number of configurable hardware resources; segmenting the input antenna signal data includes the following sub-steps:

[0074] Since at least a pair of unit data of antenna signal data needs to be taken for the most basic operation regardless of the size of the data input volume, therefore, a pair of antenna unit data is selected from the input antenna signal data, and the antenna unit data includes two sets of floating-point complex numbers. A total of eight floating-point data of the two antenna unit data will be taken in the operation. Therefore, the one-dimensional vector stored on the chip, that is, the antenna unit data, is segmented again and split into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna serial number, T is the clock window, X is the component of the antenna unit data on the X-axis, Y is the component of the antenna unit data on the Y-axis, R is the component of the antenna unit data on the R-axis, and I is the component of the antenna unit data on the I-axis. The last two dimensions are fully expanded, and four data are read in parallel each time; the multiplication and addition results of eight data are calculated in parallel. In this way, overall, eight data of two stations can be read in parallel in one cycle, and eight data can also be output in one cycle after the operation. Such parallel reading of antenna unit data can be reduced to 1 / 8 of the original clock cycle.

[0075] The antenna storage sequence number calculation module is used to calculate the antenna storage sequence number for the segmented antenna signal data. The antenna storage sequence number for the segmented antenna signal data is calculated by using a look-up table, and the antenna storage sequence number corresponds one-to-one with the loop parameter. According to the principle of cross-correlation operation, it can be known that only half of the output matrix is required for the overall result. Therefore, it is necessary to calculate the result of the position of the rows and columns processed in the antenna signal array operation. The antenna storage sequence number is determined by using the loop parameter in the result according to the number of results as the loop parameter, and the overall loop period uses a look-up table to replace the operation result, reducing the time consumption by 50% compared with the original operation period. The overall operation period is reduced by reducing the number of loops.

[0076] According to the trade-off between on-chip resources and data volume, for different data volumes, this embodiment provides two cross-correlation operation structures:

[0077] The first cross-correlation operation structure is used to store all the received antenna signal data in the on-chip memory when all the received antenna signal data can be stored in the on-chip memory, so as to avoid the data transmission consumption with the off-chip memory unit. The antenna signal array A[ST][T] stored in the on-chip memory is adjusted to a three-dimensional matrix B[ST][K][M], and then the cross-correlation and auto-correlation calculations of the antenna sites are performed to form an output value. The first cross-correlation operation structure includes: a time window segmentation module and a segmented window integration module; the time window segmentation module is used to parallelize several channels for the time window and calculate the cross-multiplication of several time windows in one clock cycle; the segmented window integration module is used to accumulate and integrate the cross-multiplication results of several time windows to form an output value. Compared with the complete parallelism of the antenna signal data of one unit, in this embodiment, the first mutual operation structure performs K-channel parallelism for each T clock window each time, calculates the cross-multiplication of K time channels in one clock cycle, and then accumulates and integrates. During the accumulation process, an adder tree is designed to further reduce the accumulation time to the value of log2(K). Using 8-channel parallelism, the clock cycle is further reduced to 1 / 8 of the original.

[0078] The second cross-correlation operation structure is used to receive the antenna signal data in batches when all the received antenna signal data cannot be stored in the on-chip memory, perform the cross-correlation and auto-correlation calculations of the received antenna signal data, and accumulate the results to form an output value. Specifically, each time a full antenna array data in a clock window T at a frequency point is received, after calculating the current result, it is accumulated with the operation results of subsequent antenna array data. In this embodiment, the on-chip memory of the second mutual operation structure only needs to store the operation data of the number of antennas and the output data of the number of baselines. Compared with storing all the data completely on the chip, such a pipelined architecture can be reduced to 1 / T storage. The second cross-correlation operation structure includes a multiplication module and an addition module. The second cross-correlation operation structure processes the multiplication module and the addition module hierarchically. When performing operations, it includes the following sub-steps:

[0079] Adjust the input order of the antenna signal data, receive the antenna signal data of all antenna sites in a clock window at a frequency point in each batch, and the multiplication module calculates the current cross-correlation and auto-correlation results;

[0080] The addition module accumulates the cross-correlation and auto-correlation results of the antenna signal data in each batch;

[0081] Loop through the above steps until all the antenna signal data of all clock windows at all frequency points are received and calculated, and all the cross-correlation and auto-correlation results are accumulated to form an output value.

[0082] For example, when reading the antenna signal data of the first part, it takes N cycles to read the antenna signal data of all antenna sites into the chip, and then it is handed over to the Kernel_mul module for the operation of the baseline value. The read antenna signal data is split to achieve an eight-fold parallelism, and row-column positioning optimization is used to reduce the overall clock cycles. The operation cycle of Kernel_mul is about the value of the number of baselines. Similarly, the operation cycle of the accumulation result in the third part is also about the value of the number of baselines, while the clock cycle of the data reading module is the number of N*4, which is less than the value of the number of baselines, meeting the requirement of processing data in a pipeline. The final output module outputs the value of Kernel_sum after receiving all T groups of antenna signal data, and obtains the final correlation product accumulation result to form the output value.

[0083] Result output step: The on-chip processor transmits the output value to the host computer.

[0084] In this step, the output value calculated by the on-chip cross-correlation operation engine needs to be sent to the host computer together with the received antenna signal data. After the host computer's receiving end packs the antenna signal data in the overall format of time window order-frequency point order-antenna serial number order-polarization direction order, the antenna signal data is sent to the host computer through the network serial port via the PYNQ top-level design.

[0085] This embodiment designs the cross-correlation operation structure in a combination of software and hardware. It allocates hardware resources by software methods, with high parallelism, fast operation speed, and fast deployment. The data is based on 32-bit floating-point data, and the IP module is designed using the Xilinx HLS high-level synthesis tool, which can be configured on boards with different resources according to different requirements. Moreover, this embodiment adopts a configurable parameter design, which can perform cross-correlation operations for different numbers of antennas, effectively improving the calculation efficiency and reducing the power consumption. At the same time, this embodiment adopts a streaming transmission structure, which increases the scalability of the subsequent cross-correlator.

[0086] Embodiment 2

[0087] This embodiment provides a radio astronomy cross-correlator acceleration system based on FPGA, which is used to execute the radio astronomy cross-correlator acceleration method based on FPGA in Embodiment 1, including an on-chip processor and an on-chip cross-correlation operation engine.

[0088] The on-chip processor receives the antenna signal data of each antenna site, transmits the antenna signal data to the on-chip cross-correlation operation engine, and transmits the output value to the host computer through the serial port. The on-chip processor includes a host computer sending and receiving end, and the received antenna signal data and output value are sent to the host computer through the host computer sending and receiving end. In this embodiment, the antenna signal data is data with F frequency points, S antenna numbers, T clock windows, and 2 polarization directions; the host computer sending and receiving end packs the antenna signal data in the overall format of time window order - frequency point order - antenna number order - polarization direction order and then sends it to the host computer.

[0089] The on-chip cross-correlation operation engine performs cross-correlation operations on the antenna signal data to generate output values of the cross-correlation operations between two antenna sites, and transmits the output values to the on-chip processor. It includes an interface module and a cross-correlation operation processing architecture. The interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, and transmit the output value to the on-chip processor; the cross-correlation operation processing architecture includes a data receiving end, a data sending end, and a cross-correlation operation structure.

[0090] The data receiving end is used to receive the antenna signal data packed by the interface module; the antenna signal data packed by the interface module is unpacked, and the unpacked bit width is an integer multiple of 32. The unpacked antenna signal data is stored in matrix format or FIFO stream data. The data sending end packs the output value generated by the cross-correlation operation structure according to the unpacked bit width and then sends it to the interface module. The cross-correlation operation structure is used to calculate the autocorrelation and cross-correlation operations of the antenna signal data between two antenna sites to generate output values, including: an on-chip data segmentation module, an antenna storage sequence number calculation module, a first cross-correlation operation structure, and a second cross-correlation operation structure.

[0091] The on-chip data segmentation module is used to segment the read antenna signal data; the antenna storage sequence number calculation module is used to calculate the antenna storage sequence number for the segmented antenna signal data; the first cross-correlation operation structure is used to store all the received antenna signal data in the on-chip storage when all the received antenna signal data can be stored in the on-chip storage, and then perform cross-correlation and autocorrelation calculations on the antenna sites to form output values; the second cross-correlation operation structure is used to receive the antenna signal data in batches when all the received antenna signal data cannot be stored in the on-chip storage, perform cross-correlation and autocorrelation calculations on the received antenna signal data, and accumulate the results to form output values.

[0092] Specifically:

[0093] When the on-chip data segmentation module segments the read antenna signal data, a pair of antenna element data is selected from the input antenna signal data, and the antenna element data includes two sets of floating-point complex numbers; the one-dimensional vector stored on the chip is further segmented and split into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna serial number, T is the clock window, X is the component of the antenna element data on the X-axis, Y is the component of the antenna element data on the Y-axis, R is the component of the antenna element data on the R-axis, and I is the component of the antenna element data on the I-axis. The last two dimensions are fully expanded, and four data are read in parallel each time; the multiplication and addition results of eight data are calculated in parallel.

[0094] The antenna storage sequence calculation module calculates the antenna storage sequence for the segmented antenna signal data in the way of a lookup table, and the antenna storage sequence corresponds to the loop parameters one by one.

[0095] The first cross-correlation operation structure includes a time window segmentation module and a time window segmentation module. The time window segmentation module is used to parallelize several channels of the time window and calculate the cross-multiplication of several channels of time windows in one clock cycle; the segmented window integration module is used to accumulate and integrate the cross-multiplication results of several channels of time windows to form an output value.

[0096] The second cross-correlation operation structure includes a multiplication module and an addition module. The second cross-correlation operation structure processes the multiplication module in a hierarchical manner. The second cross-correlation operation structure adjusts the input order of the antenna signal data. Each batch receives the antenna signal data of all antenna sites in one clock window at one frequency point. The multiplication module calculates the current cross-correlation and autocorrelation results; the addition module accumulates the cross-correlation and autocorrelation results of each batch of antenna signal data, and loops until all the antenna signal data of all clock windows at all frequency points are received and calculated, and all the cross-correlation and autocorrelation results are accumulated to form an output value.

[0097] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes but is not limited to the content described in the above specific implementation manner. Any modification that does not deviate from the functional and structural principles of the present invention will be included in the scope of the claims.

Claims

1. A method for accelerating a radio astronomy cross-correlator based on FPGA, characterized in that: The method for accelerating a radio astronomy cross-correlator includes the following steps: The on-chip processor receives the antenna signal data of each antenna site and transmits the antenna signal data to the on-chip cross-correlation operation engine; the antenna signal data is data with F frequency points, S antenna serial numbers, T clock windows, and a polarization direction of 2. The on-chip cross-correlation operation engine performs cross-correlation operations on the antenna signal data to generate output values of the cross-correlation operations between two antenna sites, and transmits the output values to the on-chip processor. The on-chip processor transmits the output values to the host computer; wherein, The on-chip cross-correlation operation engine includes a cross-correlation operation processing architecture containing a cross-correlation operation structure, and the cross-correlation operation structure includes: An on-chip data segmentation module for segmenting the read antenna signal data. An antenna storage serial number calculation module for calculating the antenna storage serial numbers of the segmented antenna signal data. A first cross-correlation operation structure, when all the received antenna signal data can be stored in the on-chip storage, stores all the received antenna signal data in the on-chip storage, and then performs cross-correlation and auto-correlation calculations on the antenna sites to form output values. A second cross-correlation operation structure, when all the received antenna signal data cannot be stored in the on-chip storage, receives the antenna signal data in batches, performs cross-correlation and auto-correlation calculations on the received antenna signal data, and accumulates the results to form output values.

2. The radio astronomy cross-correlator acceleration method according to claim 1, characterized in that The on-chip cross-correlation operation engine further includes an interface module, and the interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, and transmit the output values to the on-chip processor. And, the cross-correlation operation processing architecture further includes: A data receiving end for receiving the antenna signal data packed by the interface module. A data sending end for transmitting the output values to the interface module.

3. The radio astronomy cross-correlator acceleration method according to claim 1, wherein The antenna storage serial number calculation module calculates the antenna storage serial numbers of the segmented antenna signal data in a look-up table manner, and the antenna storage serial numbers correspond one-to-one with the loop parameters.

4. The radio astronomy cross-correlator acceleration method according to claim 1, wherein The first cross-correlation operation structure includes: A time window segmentation module that parallelizes several channels of the time window and calculates the cross-multiplication of the several channels of time windows in one clock cycle. A segmented window integration module that accumulates and integrates the cross-multiplication results of the several channels of time windows to form the output values.

5. The radio astronomy cross-correlator acceleration method according to claim 1, characterized in that The second cross-correlation operation structure includes a multiplication module and an addition module, and the second cross-correlation operation structure performs hierarchical processing on the multiplication module and the addition module. When performing operations, it includes the following steps: Adjust the input order of the antenna signal data, receive one copy of the antenna signal data of all antenna sites in one clock window at one frequency point in each batch, and the multiplication module calculates the current cross-correlation and auto-correlation results. The addition module accumulates the cross-correlation and auto-correlation results of each batch of antenna signal data. Repeat the above steps until all the antenna signal data of all frequency points and all clock windows are received and calculated, and all the cross-correlation and auto-correlation results are accumulated to form output values.

6. The radio astronomy cross-correlator acceleration method according to claim 1, wherein The on-chip data segmentation module segments the input antenna signal data, which includes the following steps: Select a pair of antenna element data from the input antenna signal data, where the antenna element data includes two sets of floating-point complex numbers; Further segment the antenna element data stored on the chip and split it into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna serial number, T is the clock window, X is the component of the antenna element data on the X-axis, Y is the component of the antenna element data on the Y-axis, R is the component of the antenna element data on the R-axis, and I is the component of the antenna element data on the I-axis. Unfold the last two dimensions completely and read four data in parallel each time; Calculate the multiplication and addition results of eight data in parallel.

7. The radio astronomy cross-correlator acceleration method according to claim 1, characterized in that, The on-chip processor includes a host computer sending and receiving end. The received antenna signal data and the output value are sent to the host computer through the host computer sending and receiving end. The host computer sending and receiving end packs the antenna signal data in the overall format of time window order - frequency point order - antenna serial number order - polarization direction order.

8. The radio astronomy cross-correlator acceleration method according to claim 2, characterized in that The data receiving end unpacks the antenna signal data packed by the interface module. The unpacking bit width is an integer multiple of 32. The unpacked antenna signal data is stored in matrix format or FIFO stream data.

9. The method for accelerating a radio astronomy cross-correlator according to claim 8, wherein The data sending end packs the output value generated by the cross-correlation operation structure according to the unpacked bit width and sends it to the interface module.

10. A radio astronomy cross-correlator acceleration system based on FPGA, characterized in that: The radio astronomy cross-correlator acceleration system includes an on-chip processor and an on-chip cross-correlation operation engine; The on-chip processor receives the antenna signal data of each antenna site and transmits the antenna signal data to the on-chip cross-correlation operation engine; the antenna signal data is data with F frequency points, S antenna serial numbers, T clock windows, and a polarization direction of 2; The on-chip cross-correlation operation engine performs cross-correlation operations on the antenna signal data to generate output values of the cross-correlation operations between two antenna sites, and transmits the output values to the on-chip processor; The on-chip processor transmits the output value to the host computer; where, The on-chip cross-correlation operation engine includes a cross-correlation operation processing architecture containing a cross-correlation operation structure, and the cross-correlation operation structure includes: An on-chip data segmentation module for segmenting the input antenna signal data; An antenna storage serial number calculation module for calculating the antenna storage serial number of the segmented antenna signal data; A first cross-correlation operation structure. When the received antenna signal data can be fully stored on the on-chip storage, store all the received antenna signal data on the on-chip storage, and then perform cross-correlation and autocorrelation calculations of antenna sites to form an output value; A second cross-correlation operation structure. When the received antenna signal data cannot be fully stored on the on-chip storage, receive the antenna signal data in batches, perform cross-correlation and autocorrelation calculations of antenna sites on the received antenna signal data, and accumulate the results to form an output value.

11. The radio astronomy cross-correlator acceleration system according to claim 10, characterized in that, The on-chip cross-correlation operation engine further includes an interface module. The interface module is used to receive the antenna signal data sent by the on-chip processor, pack the antenna signal data sent by the on-chip processor, and transmit the output value to the on-chip processor; Moreover, the cross-correlation operation processing architecture further includes: A data receiving end, configured to receive the antenna signal data packed by the interface module; A data sending end, configured to transmit the output value to the interface module.

12. The radio astronomy cross-correlator acceleration system according to claim 10, wherein The antenna storage sequence calculation module calculates the antenna storage sequence for the segmented antenna signal data in a lookup table manner, and the antenna storage sequence corresponds to the loop parameter one by one.

13. The radio astronomy cross-correlator acceleration system according to claim 10, wherein The first cross-correlation operation structure includes: A time window segmentation module that parallelizes several channels for the time window and calculates the cross multiplication of the several time windows in one clock cycle; A segmented window integration module that accumulates and integrates the cross multiplication results of the several time windows to form the output value.

14. The radio astronomy cross-correlator acceleration system according to claim 10, characterized in that, The second cross-correlation operation structure includes a multiplication module and an addition module. The second cross-correlation operation structure performs hierarchical processing on the multiplication module and the addition module. The second cross-correlation operation structure adjusts the input order of the antenna signal data, receives one copy of the antenna signal data of all antenna sites in one clock window at one frequency point in each batch, and the multiplication module calculates the current cross-correlation and auto-correlation results; The addition module accumulates the cross-correlation and auto-correlation results of each batch of antenna signal data, and loops until all the antenna signal data of all clock windows at all frequency points are received and calculated, and all the cross-correlation and auto-correlation results are accumulated to form the output value.

15. The radio astronomy cross-correlator acceleration system according to claim 10, wherein When the on-chip data segmentation module segments the read antenna signal data, it selects a pair of antenna unit data from the input antenna signal data. The antenna unit data includes two sets of floating-point complex numbers; the antenna unit data stored on the chip is segmented again and split into three-dimensional data of data[ST][X,Y][R,I], where S is the antenna sequence number, T is the clock window, X is the component of the antenna unit data on the X axis, Y is the component of the antenna unit data on the Y axis, R is the component of the antenna unit data on the R axis, and I is the component of the antenna unit data on the I axis. The last two dimensions are fully expanded, and four data are read in parallel each time; the multiplication and addition results of eight data are calculated in parallel.

16. The radio astronomy cross-correlator acceleration system according to claim 10, wherein The on-chip processor includes a host computer sending and receiving end. The received antenna signal data and the output value are sent to the host computer through the host computer sending and receiving end. The host computer sending and receiving end packs the antenna signal data in the overall format of time window sequence - frequency point sequence - antenna sequence number sequence - polarization direction sequence.

17. The radio astronomy cross-correlator acceleration system according to claim 11, characterized in that The data receiving end unpacks the antenna signal data packed by the interface module. The unpacked bit width is an integer multiple of 32, and the unpacked antenna signal data is stored in matrix format or FIFO stream data.

18. The radio astronomy cross-correlator acceleration system according to claim 17, wherein The data sending end packs the output value generated by the cross-correlation operation structure according to the unpacked bit width and sends it to the interface module.