A method and system for verifying asynchronous event conflicts in Verilog designs

Abstract

A Verilog-designed asynchronous event conflict verification method and system, which includes a Verilog language parsing module, a basic device identification module, a suspected asynchronous event automatic extraction module, and an asynchronous event port confirmation module. The verification system analyzes suspected ports of asynchronous events in large-scale logic designs through a static analysis method, models input and output ports through a manual analysis method, and finally verifies the problem through a simulation verification method, thereby ultimately improving the reliability of large-scale logic design products.

Description

Technical Field

[0001] The invention relates to a Verilog-design-oriented asynchronous event conflict verification method and system, belonging to the technical field of asynchronous event conflict automatic verification based on full circuit structure recognition. Background Art

[0002] Asynchronous events in large-scale logic design are two independent control signals in large-scale logic design that work together to complete a task in a certain sequence. When there is a timing loophole in the design logic, the two control signals arrive in a specific sequence and conflict, which will cause the task to fail. This type of failure is called asynchronous event conflict in large-scale logic design. Asynchronous event conflicts in large-scale logic design have the following two characteristics: 1. They are difficult to detect. The event must be triggered in a specific time window, and conventional experiments, prevention, and hardware testing are not easy to detect; 2. They are highly harmful to the product. Tasks that require multiplexing of multiple control signals are generally critical functions, and their success or failure is related to the main tasks of the product.

[0003] With the development of my country's integrated circuit industry, electronic products are becoming miniaturized and intelligent, and the role and status of large-scale integrated circuits in electronic products are becoming more and more prominent, and the scale and complexity of the design are also increasing. White box testing is an effective means of verifying asynchronous event conflicts in large-scale integrated circuit design, but it is difficult to detect them through purely manual means due to factors such as design complexity and professional background knowledge. Therefore, in order to improve the quality and reliability of large-scale logic design products, it is necessary to find automated auxiliary methods to discover asynchronous event conflict scenarios and conduct rapid verification.

[0004] At present, there are no patents or articles with the same direction at home and abroad for the automatic verification method of asynchronous event conflicts in large-scale logic designs designed using the Verilog language, but there are related patents and articles.

[0005] Maipu Communication Technology Co., Ltd. CN201210022986.3 discloses a fault-tolerant and order-preserving event scheduling device, including a request queue module, a result queue module, a blocking queue module, a waiting queue module, an error queue module and an event scheduling task module, wherein the request queue module is used to store the pending events initiated by the external task in the form of event nodes; the result queue module is used to store the event processing results returned asynchronously from the outside in the form of event nodes; the blocking queue module is used to store the event nodes that must wait for the completion of the preceding event processing due to timing problems; the waiting queue module is used to store the event nodes that need to wait for the results returned asynchronously from the outside; the error queue module is used to store the event nodes that failed to execute; and the event scheduling task module is used to schedule the event nodes. The present invention can solve the fault tolerance and timing problems of event scheduling during software operation, and improve the execution efficiency and reliability of data communication equipment.

[0006] "A Study on the Processing of Serial Port Data Frame Splicing Phenomenon" describes a method for processing data conflicts caused by asynchronous events. In a control module based on FPGA+C8051 single-chip microcomputer architecture, the serial communication bus RS232 is used to realize data interaction between FPGA and single-chip microcomputer; in order to realize the single-chip microcomputer's external high-priority interrupt triggers the serial port receiving interrupt to close, resulting in the abnormal problem of data frame dislocation and data frame splicing after the serial port reception is opened again; the duration of the single-chip microcomputer receiving a complete data frame, the processing mechanism for receiving a frame of data, the mechanism for receiving data frame splicing, etc. are studied and processed, and monitoring points are set in the program to monitor the shutdown duration of the serial port data frame triggered by the external interrupt, the frequency of interruption, etc.; it is confirmed that the factors causing the serial port data frame splicing and data frame error problems are that after the single-chip microcomputer serial port reception is turned on, the serial port interrupt is closed by an external high-priority interrupt. While executing the high-priority interrupt, the FPGA control software does not stop sending serial port data frames. After the serial port interrupt is reopened, the new serial port data frame is spliced ​​with part of the data frame received before the single-chip microcomputer closes the interrupt, resulting in abnormal data frame splicing; and when the spliced ​​data frame contains data consistent with the end of the data frame in the communication protocol, the frame data will be judged as a normal data frame, resulting in abnormal data frame splicing and misalignment during data parsing; by adding monitoring signals and corresponding test cases to the software with abnormal communication data misalignment to capture the closing time of the serial port receiving interrupt, the result analysis and experimental verification of the serial port data frame splicing are realized; after taking measures such as reducing the closing time of the serial port interrupt for the abnormal communication data misalignment, it is ensured that when the serial port data frame is received, the abnormal communication data splicing and misalignment caused by the long serial port closing time is avoided; the data splicing problem caused by the long serial port closing time is effectively solved, and the normal communication data between the FPGA and the single-chip microcomputer of the control module is ensured.

[0007] To sum up, on the one hand, asynchronous event conflicts in large-scale logic designs are very harmful and difficult to detect through manual testing and experimental means; on the other hand, there is still a lack of automated verification methods for asynchronous event conflicts in large-scale logic designs. Summary of the invention

[0008] The technical problem solved by the present invention is: in view of the fact that asynchronous event conflicts in large-scale logic designs in the current prior art are very harmful and difficult to be discovered through manual testing and experimental means, and that there is still a lack of automated verification methods for asynchronous event conflicts in large-scale logic designs, a method and system for verifying asynchronous event conflicts for Verilog designs are proposed.

[0009] The present invention solves the above technical problems by the following technical solutions:

[0010] An asynchronous event conflict verification method for Verilog design, comprising:

[0011] For Verilog design projects and gate-level netlist files, the Verilog language acquisition and analysis module is used to perform language parsing;

[0012] Identify basic components for Verilog design projects;

[0013] Automatically identify ports with suspected asynchronous events and form a port relationship record table;

[0014] Asynchronous events are confirmed through simulation verification and principle analysis, and a list of asynchronous event conflicts is formed. Support is provided for subsequent experiments based on the obtained list of asynchronous event conflicts.

[0015] The specific steps for language parsing are as follows:

[0016] Load the Verilog design project, obtain the Verilog file names in order, and store them to form a file list;

[0017] According to the file list, each Verilog file is parsed line by line, syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list based on modules;

[0018] According to the calling relationship of the modules to be called designed from top to bottom in each Verilog file, the top-level design files in all top-down designs are searched, all the corresponding modules to be called are determined from the top-level design files, and a design structure list is obtained;

[0019] Perform unified analysis based on the design structure list, syntax analysis, and lexical analysis results to obtain the symbol table.

[0020] Load the obtained symbol table to identify the basic devices, specifically:

[0021] Respectively identify the identification block statements and assign statements in the symbol table. If the identification result of any statement is an assign statement, store the relevant content of the statement into the logic connection information list, otherwise perform logic judgment;

[0022] Determine the logic type of the recognition block statement, if it is sequential logic, store it in the register information list, otherwise store it in the logic connection information list;

[0023] After traversing all the statements in the symbol table, obtain a complete register information list and a logical connection information list.

[0024] The specific steps to obtain the port relationship record table are as follows:

[0025] Read the output interface list of the module to be called, query the connection relationship between the logic information list and the register information list according to the port, form the connection relationship between the devices through the name relationship of the registers, latches, and logical combinations, and use the name to match and infer the input port list at the end of each output port connection. All matching failures are recorded as asynchronous events to form the final port relationship record table.

[0026] The register or latch includes a clock port, a reset port, an enable port, a data input port, and a data output port, and the logic combination includes an input port and an output port.

[0027] The steps to obtain the asynchronous event conflict list are:

[0028] Define the time base 0, determine the update rule and number of bytes of the input interface data or control information at the starting point of the asynchronous event, and model the relationship between the input signals and the time of the input cycle; clarify the update rule and number of bytes of the output data interface data or control information, and model various situations of the output cycle; collect all the asynchronous events that can be analyzed for simulation verification and confirmation, and form a final asynchronous event list to record the conflict time of asynchronous events.

[0029] An asynchronous event conflict verification system for Verilog design includes a Verilog language parsing module, a basic device identification module, a suspected asynchronous event automatic extraction module, and an asynchronous event port confirmation module, wherein:

[0030] The Verilog language parsing module performs language parsing on Verilog design projects and gate-level netlist files through the Verilog language acquisition and analysis module; the basic device identification module identifies basic devices for Verilog design projects; the suspected asynchronous event automatic extraction module automatically identifies ports with suspected asynchronous events and forms a port relationship record table; the asynchronous event port confirmation module confirms asynchronous events through simulation verification and principle analysis, and forms an asynchronous event conflict list, and provides support for subsequent experiments based on the obtained asynchronous event conflict list.

[0031] In the Verilog language parsing module, the Verilog design project is loaded, and the Verilog file names are obtained in sequence according to the file name order, and stored to form a file list; each Verilog file is parsed line by line according to the file list, and syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list with modules as units; the calling relationship of the modules to be called is designed from top to bottom according to each Verilog file, and the top-level design files in all top-down designs are searched, and all corresponding modules to be called are determined by the top-level design files to obtain a design structure list; a unified analysis is performed based on the design structure list and the results of syntax analysis and lexical analysis to obtain a symbol table.

[0032] The basic device identification module loads the symbol table, identifies the basic device, and respectively identifies the identification block statement and the assign statement in the symbol table. If the identification result of any statement is an assign statement, the relevant content of the statement is stored in the logic connection information list, otherwise a logic judgment is performed; the logic type of the identification block statement is judged, if it is a sequential logic, it is stored in the register information list, otherwise it is stored in the logic connection information list; after traversing all the statements in the symbol table, a complete register information list and a logic connection information list are obtained.

[0033] The suspected asynchronous event automatic extraction module reads the output interface list of the module to be called, performs reverse inference on each output port, reads the output interface list of the module to be called, queries the connection relationship between the logic information list and the register information list according to the port, forms the connection relationship between the devices through the name relationship of the register, latch, and logical combination, and performs reverse inference; for each output port connection end, matches the name with the input port list to form a final port relationship record table.

[0034] The asynchronous event port confirmation module defines the time base 0, determines the update rule and the number of bytes of the input interface data or control information at the starting point of the asynchronous event, and models the relationship between each input signal and the time change of the input cycle; clarifies the update rule and the number of bytes of the output data interface data or control information, and models various situations of the output cycle; collects all asynchronous events that can be analyzed for simulation verification and confirmation, and forms a final asynchronous event list to record the asynchronous event conflict time.

[0035] The advantages of the present invention compared with the prior art are:

[0036] (1) The present invention provides a Verilog design-oriented asynchronous event conflict verification method and system, which analyzes suspected ports of asynchronous events in large-scale logic design through static analysis, models input and output ports using manual analysis, and then verifies the problem using simulation verification methods. This method can overcome the problem that the existing technology cannot confirm the asynchronous event conflicts of large-scale logic design, and ultimately improve the reliability of large-scale logic design products.

[0037] (2) The present invention can overcome the problem of the overall design defect of Verilog design in the prior art that the problem cannot be analyzed by abstracting the basic device methods such as registers and latches expressed by Verilog code, and realize the overall signal analysis for the Verilog design project;

[0038] (3) The present invention can overcome the problem that the prior art is unable to analyze the relationship between gate-level netlist ports through an automated extraction algorithm for suspected asynchronous event ports, and can implement gate-level netlist asynchronous event conflict detection for the final form of large-scale logic design products. It can also solve the problem that the prior art is unable to detect and locate asynchronous event conflicts in large-scale logic designs, and can solve the problem of asynchronous event conflicts that are difficult to detect in engineering experiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The principle flow chart of the method for automatic analysis of gate-level netlists across clock domains for programmable logic design provided by the invention;

[0040] Figure 2 A flow chart of the basic device identification principle provided for the invention;

[0041] Figure 3 A flow chart of the principle of automated extraction of suspected asynchronous event ports provided for the invention;

[0042] Figure 4 Asynchronous event port confirmation principle flow chart provided for the invention; DETAILED DESCRIPTION

[0043] A Verilog-designed asynchronous event conflict verification method and system is provided. The suspected ports of large-scale logic design asynchronous events are analyzed by static analysis, the input and output ports are modeled by manual analysis, and the problems are finally verified by simulation verification, thereby improving the reliability of large-scale logic design products. The verification system specifically includes:

[0044] It includes Verilog language parsing module, basic device identification module, suspected asynchronous event automatic extraction module, and asynchronous event port confirmation module, among which:

[0045] The Verilog language parsing module performs language parsing on Verilog design projects and gate-level netlist files through the Verilog language acquisition and analysis module; the basic device identification module identifies basic devices for Verilog design projects; the suspected asynchronous event automatic extraction module automatically identifies ports with suspected asynchronous events and forms a port relationship record table; the asynchronous event port confirmation module confirms asynchronous events through simulation verification and principle analysis, and forms an asynchronous event conflict list, providing support for subsequent experiments based on the obtained asynchronous event conflict list;

[0046] Specifically, in the Verilog language parsing module, the Verilog design project is loaded, and the Verilog file names are obtained in sequence according to the file name order, and stored to form a file list; each Verilog file is parsed line by line according to the file list, and syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list with modules as units; according to the calling relationship between each module designed from top to bottom in each Verilog file, all top-level files, that is, the top-level design files designed from top to bottom, are searched, and all corresponding modules to be called are determined from the top-level design files to obtain a design structure list; unified analysis is performed based on the design structure list and the results of syntax analysis and lexical analysis to obtain a symbol table;

[0047] The basic device identification module loads the symbol table, identifies the basic device, and identifies the identification block statements and assign statements in the symbol table respectively. If the identification result of any statement is an assign statement, the relevant content of the statement is stored in the logic connection information list, otherwise a logic judgment is performed; the logic type of the identification block statement is judged, if it is a sequential logic, it is stored in the register information list, otherwise it is stored in the logic connection information list; after traversing all the statements in the symbol table, a complete register information list and a logic connection information list are obtained;

[0048] The suspected asynchronous event automatic extraction module reads the output interface list of the module to be called, performs reverse inference on each output port, and forms the connection relationship between each device through the name relationship of registers, latches, and logical combinations according to the connection relationship between the port query logic information list and the register information list, and performs reverse inference; for each output port connection end, the name is matched with the input port list to form the final port relationship record table;

[0049] The asynchronous event port confirmation module defines the time base 0, determines the update rules and number of bytes of the asynchronous event starting point input interface data or control information of each module in the Verilog design, and models the relationship between each input signal and time change of the input cycle; clarifies the update rules and number of bytes of the output data interface data or control information, and models various situations of the output cycle; collects all asynchronous events that can be analyzed for simulation verification and confirmation, and forms a final asynchronous event list to record the asynchronous event conflict time.

[0050] According to the above system, asynchronous event conflict verification is performed, and the method steps are specifically as follows:

[0051] (1) For Verilog design projects and gate-level netlist files, language parsing is performed through the Verilog language acquisition and analysis module;

[0052] The specific steps for language parsing are as follows:

[0053] Load the Verilog design project, obtain the Verilog file names in order, and store them to form a file list;

[0054] According to the file list, each Verilog file is parsed line by line, syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list based on modules;

[0055] According to the calling relationship of the modules to be called designed from top to bottom in each Verilog file, the top-level design files in all top-down designs are searched, all the corresponding modules to be called are determined from the top-level design files, and a design structure list is obtained;

[0056] Perform unified analysis based on the design structure list and the results of syntax analysis and lexical analysis to obtain the symbol table;

[0057] (2) Identify basic components for Verilog design projects;

[0058] The symbol table obtained in step (1) is loaded to identify the basic devices, specifically:

[0059] Respectively identify the identification block statements and assign statements in the symbol table. If the identification result of any statement is an assign statement, store the relevant content of the statement into the logic connection information list, otherwise perform logic judgment;

[0060] Determine the logic type of the recognition block statement, if it is sequential logic, store it in the register information list, otherwise store it in the logic connection information list;

[0061] After traversing all the statements in the symbol table, obtain the complete register information list and logical connection information list;

[0062] (3) Automatically identify ports with suspected asynchronous events and form a port relationship record table;

[0063] The specific steps to obtain the port relationship record table are as follows:

[0064] Read the output interface list of each module of the Verilog design, perform reverse inference on each output port, query the connection relationship of the logic information list and the register information list according to the port, form the connection relationship between each device through the name relationship of the register, latch, and logic combination, and perform reverse inference; for each output port connection end, use the name to match with the input port list to form the final port relationship record table;

[0065] The register or latch includes a clock port, a reset port, an enable port, a data input port, and a data output port, and the logic combination includes an input port and an output port;

[0066] (4) Confirm asynchronous events through simulation verification and principle analysis, and form a list of asynchronous event conflicts, and provide support for subsequent experiments based on the obtained asynchronous event conflict list;

[0067] The steps to obtain the asynchronous event conflict list are:

[0068] Define the time base 0, determine the update rules and update bytes of the input interface data or control information of each module of the Verilog design, and model the relationship between each input signal and time of the input cycle; clarify the update rules and update bytes of the output data interface data or control information, and model various situations of the output cycle; collect all asynchronous events that can be analyzed for simulation verification and confirmation, and form a final asynchronous event list to record the conflict time of asynchronous events.

[0069] The following is further described based on specific embodiments:

[0070] In the current embodiment, if Figure 1As shown, it is based on Verilog code parsing technology, does not rely on any other application software, is not restricted by operating system and software copyright, abstracts basic devices such as registers and latches expressed in Verilog code, can perform overall signal analysis on the project, and can automatically extract algorithms through suspected asynchronous event ports. It can also be applied to gate-level netlist analysis to determine whether there are asynchronous event conflicts in the final form of large-scale logic design products.

[0071] Traditional methods do not have a system verification method for asynchronous event conflicts in large-scale logic designs. Asynchronous event conflict problems are often considered to be special application scenarios of a certain design, but this application scenario is difficult to discover during product development and verification, and there is no such scenario yet. For example, the main function of a certain design is to output serial port data instructions in multiplexing. When the arrival time difference of multiple serial port instructions is within 100us, the output data will be spliced. In engineering experiments, it is difficult to find this problem, but it can be found through this method.

[0072] Through the verification system including Verilog language acquisition and analysis module, basic device identification module, suspected asynchronous event port automatic extraction module and asynchronous event port confirmation module, in the asynchronous event automatic conflict analysis, firstly, the Verilog language acquisition and analysis module performs language parsing on the Verilog design and gate-level netlist files, and the language parsing results are stored in the symbol table; secondly, the basic device identification module uses the symbol table to analyze the statements in the design, and identifies the registers, latches, logical combinations and link relationships; thirdly, the suspected asynchronous event port automatic extraction module traverses all output ports, and uses the data flow analysis method to infer the source of its input port according to the device connection relationship; finally, the asynchronous event port confirmation module determines the asynchronous event conflict according to the definition of the reference time, input port signal modeling, output port signal modeling and simulation verification and verification.

[0073] The specific process is as follows:

[0074] (1) Verilog language acquisition and analysis module performs language analysis on Verilog design and gate-level netlist files, specifically:

[0075] First, load the Verilog design project, obtain the Verilog file names in the project in order of file names, and store them to form a file list;

[0076] Secondly, parse the files one by one and line by line according to the file list, complete syntax analysis and lexical analysis, and store the analysis results in a list based on modules;

[0077] Again, all top-level design files are searched according to the module calling relationships described in each file. Then, starting from the top-level file, all modules called by it are searched, and finally a design structure list is formed.

[0078] Finally, the design structure list is combined with the lexical and grammatical analysis results to form the final symbol table;

[0079] (2) Identify basic components for Verilog design, such as Figure 2 As shown, specifically:

[0080] First, load the symbol list for subsequent operation steps to read. Secondly, identify the identification block statement and assign statement of the symbol expression respectively. If it is an assignment statement, store the relevant content of the statement in the logic connection information list; thirdly, identify whether the expression of the block statement is sequential logic or combinational logic. If it is sequential logic, store it in the register information list, otherwise store it in the logic connection information list; finally, the register list and logic connection list of the entire design are formed;

[0081] (3) Automatically identify ports with suspected asynchronous events and form a port relationship record table. Figure 3 As shown, specifically:

[0082] First, read the output interface list and perform reverse inference for each output port to ensure that all output ports are included.

[0083] Secondly, query the connection relationship between the logic information list and the register list according to the output port. Among them, the register or latch includes the clock port, reset port, enable port, data input port and data output port, and the logic combination includes the input port and the output port. The connection relationship between each device is formed through the name relationship of the register, latch and logic combination, and reverse inference is performed.

[0084] Finally, for all port connection ends, the names are matched with the input port list to form the final port relationship record table;

[0085] (4) Confirm the asynchronous events through principle analysis and simulation verification to form an asynchronous event conflict list. Figure 4 As shown, specifically:

[0086] First, a time base 0 is clearly defined, for example, the reset cancellation time is defined as 0.

[0087] Secondly, the update rules and update bytes of input interface data or control information are clarified, and various input cycle conditions are modeled. For example, data is updated in a certain cycle or cycle range according to design constraints.

[0088] Secondly, clarify the update rules and update bytes of the output data interface data or control information, and model various situations of the output cycle. For example, according to the design constraints, determine the data update time through inspection. If it is pure asynchronous data with no definite relative relationship, there must be a time when the data is not completely updated.

[0089] Finally, all analyzed asynchronous events are collected for simulation verification and confirmation, forming a final asynchronous event list to record the asynchronous event conflict time.

[0090] The large-scale logic design asynchronous event conflict automatic verification method designed in Verilog language applied in this embodiment solves the problem of reliable verification of large-scale logic design asynchronous event conflicts and fills some technical gaps in the field of traditional technology.

[0091] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0092] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. An asynchronous event conflict verification method for Verilog design, characterized in that include: For Verilog design projects and gate-level netlist files, the Verilog language acquisition and analysis module is used to perform language parsing; Identify basic components for Verilog design projects; Automatically identify ports with suspected asynchronous events and form a port relationship record table; Confirm asynchronous events through simulation verification and principle analysis, and form a list of asynchronous event conflicts, and provide support for subsequent experiments based on the obtained asynchronous event conflict list; The specific steps for obtaining the port relationship record table are as follows: Read the output interface list of the module to be called, query the connection relationship of the logic information list and the register information list according to the port, form the connection relationship between the devices through the name relationship of the register, latch, and logic combination, and match and infer the name with the input port list for each output port connection end, record all matching failures as asynchronous events, and form the final port relationship record table; The steps to obtain the asynchronous event conflict list are: Define the time base 0, determine the update rule and number of bytes of the input interface data or control information at the starting point of the asynchronous event, and model the relationship between the input signals and the time of the input cycle; clarify the update rule and number of bytes of the output data interface data or control information, and model various situations of the output cycle; collect all the asynchronous events that can be analyzed for simulation verification and confirmation, and form a final asynchronous event list to record the conflict time of asynchronous events.

2. The method for verifying asynchronous events in Verilog design according to claim 1, characterized in that: The specific steps for language parsing are as follows: Load the Verilog design project, obtain the Verilog file names in order, and store them to form a file list; According to the file list, each Verilog file is parsed line by line, syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list based on modules; According to the calling relationship of the modules to be called designed from top to bottom in each Verilog file, the top-level design files in all top-down designs are searched, all the corresponding modules to be called are determined from the top-level design files, and a design structure list is obtained; Perform unified analysis based on the design structure list, syntax analysis, and lexical analysis results to obtain the symbol table.

3. The method for verifying asynchronous events in Verilog design according to claim 2, characterized in that: Load the obtained symbol table to identify the basic devices, specifically: Respectively identify the identification block statements and assign statements in the symbol table. If the identification result of any statement is an assign statement, store the relevant content of the statement into the logic connection information list, otherwise perform logic judgment; Determine the logic type of the recognition block statement, if it is sequential logic, store it in the register information list, otherwise store it in the logic connection information list; After traversing all the statements in the symbol table, obtain a complete register information list and a logical connection information list.

4. The method for verifying asynchronous event conflicts in Verilog design according to claim 1, characterized in that: The register or latch includes a clock port, a reset port, an enable port, a data input port, and a data output port, and the logic combination includes an input port and an output port.

5. A verification system for implementing the Verilog design-oriented asynchronous event conflict verification method according to claim 1, characterized in that: It includes Verilog language parsing module, basic device identification module, suspected asynchronous event automatic extraction module, and asynchronous event port confirmation module, among which: The Verilog language parsing module performs language parsing on Verilog design projects and gate-level netlist files through the Verilog language acquisition and analysis module; the basic device identification module identifies basic devices for Verilog design projects; the suspected asynchronous event automatic extraction module automatically identifies ports with suspected asynchronous events and forms a port relationship record table; the asynchronous event port confirmation module confirms asynchronous events through simulation verification and principle analysis, and forms an asynchronous event conflict list, and provides support for subsequent experiments based on the obtained asynchronous event conflict list.

6. The verification system according to claim 5, characterized in that: In the Verilog language parsing module, the Verilog design project is loaded, the Verilog file names are obtained in order according to the file name sequence, and stored to form a file list; each Verilog file is parsed line by line according to the file list, syntax analysis and lexical analysis are completed, and the analysis results are stored in a storage list based on modules; According to the calling relationship of the modules to be called designed from top to bottom in each Verilog file, the top-level design files in all top-down designs are searched, all the corresponding modules to be called are determined from the top-level design files, and a design structure list is obtained; Perform unified analysis based on the design structure list, syntax analysis, and lexical analysis results to obtain the symbol table.

7. The verification system according to claim 6, characterized in that: The basic device identification module loads the symbol table, identifies the basic device, and respectively identifies the identification block statement and the assign statement in the symbol table. If the identification result of any statement is an assign statement, the relevant content of the statement is stored in the logic connection information list, otherwise a logic judgment is performed; the logic type of the identification block statement is judged, if it is a sequential logic, it is stored in the register information list, otherwise it is stored in the logic connection information list; after traversing all the statements in the symbol table, a complete register information list and a logic connection information list are obtained.

8. The verification system according to claim 7, characterized in that: The suspected asynchronous event automatic extraction module reads the output interface list of the module to be called, performs reverse inference for each output port, reads the output interface list of the module to be called, queries the connection relationship between the logic information list and the register information list according to the port, forms the connection relationship between the devices through the name relationship of the register, latch, and logic combination, and performs reverse inference; For each output port connection end, the name is matched with the input port list to form a final port relationship record table.

9. The verification system according to claim 8, characterized in that: The asynchronous event port confirmation module defines the time base 0 moment, determines the update rule and the number of updated bytes of the input interface data or control information at the asynchronous event starting point, and models the relationship between each input signal and the time change of the input cycle; Clarify the update rules and number of bytes of output data interface data or control information, and model various situations of the output cycle; Collect all asynchronous events that can be analyzed for simulation verification and confirmation, and form a final asynchronous event list to record the asynchronous event conflict time.

Images