Cache memory

Abstract

This application is directed to notebook memory in a cache. An apparatus can operate a portion of volatile memory in a cache mode having non-deterministic latency for servicing requests of a host device. The apparatus can monitor a register having an output pin associated with the portion and indicative of a mode of operation of the portion. Based on or in response to monitoring the output pin, the apparatus can determine whether to change the mode of operation of the portion from the cache mode to a notebook mode having deterministic latency for servicing requests of the host device.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 140,094, filed January 21, 2021, entitled “SCRATCHPAD MEMORY IN A CACHE”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to note-based storage in caches. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically represented as logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memories such as FeRAM can maintain their stored logic state for a long time even without an external power supply. Volatile memory devices such as DRAM may lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] A method is described. The method is executable by a memory device and may include: operating a portion of volatile memory in a cache mode having a nondeterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and non-volatile memory; monitoring an output pin of a register in the memory device, the output pin being associated with the portion and indicating an operating mode of the portion; determining, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from the cache mode to a note mode having a deterministic latency for satisfying a request from the host device, the note mode being used to operate the portion independently of the non-volatile memory; and operating the portion of volatile memory in the note mode, at least in part based on determining the change in the operating mode of the portion.

[0007] Describe a device. The device may include: non-volatile memory; volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller is configured to cause the device to: operate a portion of the volatile memory in a cache mode having a nondeterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and the non-volatile memory; monitor an output pin of a register in the device, the output pin being associated with the portion and indicating an operating mode of the portion; determine, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from the cache mode to a note mode having a deterministic latency for satisfying a request from the host device, the note mode being used to operate the portion independently of the non-volatile memory; and operate the portion of the volatile memory in the note mode, at least in part based on determining the change in the operating mode of the portion.

[0008] Describe a device. The device may include: non-volatile memory; volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller is configured to cause the device to: operate a portion of the volatile memory in a note mode having a deterministic latency for satisfying a request from a host device, the note mode being used to operate the portion independently of the non-volatile memory; monitor an output pin of a register in the device, the output pin being associated with the portion and indicating an operating mode of the portion; determine, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from the note mode to a cache mode having a non-deterministic latency for satisfying a request from the host device, the cache mode being associated with data movement between the portion and the non-volatile memory; and operate the portion of the volatile memory in the cache mode, at least in part based on determining the change in the operating mode of the portion. Attached Figure Description

[0009] Figure 1 Examples of systems supporting note-taking memory in caches are shown, based on the examples disclosed herein.

[0010] Figure 2 An example of a memory subsystem supporting note-taking memory in a cache is shown, based on the examples disclosed herein.

[0011] Figure 3 Examples of devices supporting note-like storage in a cache are shown, according to the examples disclosed herein.

[0012] Figure 4 An example of a process flow supporting note-based memory in a cache, based on the examples disclosed herein, is shown.

[0013] Figure 5 An example of a process flow supporting note-based memory in a cache, based on the examples disclosed herein, is shown.

[0014] Figure 6 A block diagram is shown of an interface controller that supports note-taking memory in a cache, according to an example disclosed herein.

[0015] Figure 7 and 8 The flowcharts shown below illustrate one or more methods for supporting note-based storage in caches, based on examples disclosed herein. Detailed Implementation

[0016] Devices such as electronic devices may include non-volatile memory (e.g., main memory for storing information and other operations) and volatile memory (e.g., secondary memory) that can be used as a cache for the non-volatile memory. This configuration allows the device to benefit from the advantages of non-volatile memory (e.g., non-volatile and persistent storage, high storage capacity, low power consumption) while maintaining compatibility with the host device, among other things, through volatile memory. Operation of volatile memory as a cache (or "in cache mode") may result in non-deterministic latency for satisfying requests from the host device, as the memory used to satisfy the request may change, and for other reasons. For example, volatile memory may be used to satisfy a request where the target data exists in volatile memory, while non-volatile memory (which has a longer access time than volatile memory) may be used to satisfy a request where the target data does not exist in volatile memory. However, non-deterministic latency may not be suitable for a particular application or scenario and may degrade system and device performance.

[0017] According to the techniques described herein, a device can operate a portion of volatile memory as a note (or "in note mode"), allowing specific requests from the host device to be satisfied with deterministic latency. In note mode, requests implying that the portion can only be satisfied by volatile memory and non-deterministic latency operations used in cache mode can be avoided, thereby allowing the device to operate with deterministic latency. To accommodate fluctuating demands of deterministic memory operation, the device can be configured to dynamically adjust the size of the portion operating in note mode. For example, the device can switch the operation mode of a region of volatile memory from cache mode to note mode, thereby increasing the size of the note portion. As another example, the device can switch the operation mode of a region of volatile memory from note mode to cache mode, thereby decreasing the size of the note portion.

[0018] The features of this disclosure are firstly in reference to Figure 1 and 2 The system and memory subsystem described herein are described in the context of the system and memory subsystem described. Features of this disclosure are described in reference to... Figure 3 The described apparatus and reference Figure 4 and 5 The process flow described herein is described in the context of the process flow. These and other features of this disclosure are further illustrated by reference. Figure 6-8 The device diagrams and flowcharts describing dynamic notes in the cache are shown and described with reference to these diagrams.

[0019] Figure 1An example of a system 100 supporting note-taking memory in a cache, according to the examples disclosed herein, is shown. System 100 may be included in an electronic device such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Host device 105 may be a processor or a system-on-a-chip (SoC) that interfaces with interface controller 115 and other components of the electronic device containing system 100. Memory subsystem 110 may store electronic information (e.g., digital information, data) of host device 105 and provide access to that electronic information. Memory subsystem 110 may include interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, interface controller 115, volatile memory 120, and non-volatile memory 125 may be included in the same physical package, such as package 130. However, interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different corresponding dies (e.g., silicon dies).

[0020] Devices in system 100 can be coupled via various conductive lines (e.g., traces, printed circuit board (PCB) routes, redistribution layer (RDL) routes) that enable the transmission of information (e.g., commands, addresses, data) between devices. These conductive lines can form channels, data buses, command buses, address buses, and so on.

[0021] Memory subsystem 110 may be configured to provide the benefits of non-volatile memory 125 while maintaining compatibility with host device 105 that supports protocols supporting different types of memory, such as volatile memory 120 and other instances. For example, non-volatile memory 125 may offer benefits (e.g., relative to volatile memory 120) such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be incompatible with or inefficiently configured with various aspects of non-volatile memory 125. For instance, host device 105 may support voltages, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 may be configured with volatile memory 120 that is compatible with host device 105 and serves as a cache for non-volatile memory 125. Therefore, host device 105 can use the protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0022] In some instances, system 100 may be contained in or coupled to a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 is capable of machine-to-machine (MTC), machine-to-machine (M2M), or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as a user equipment (UE), site (STA), mobile terminal, etc.

[0023] Host device 105 may be configured to interface with memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by interface controller 115. Therefore, in some instances, host device 105 may interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 may interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 may also interface with other components of the electronic device comprising system 100. Host device 105 may be or include a SoC, general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In some instances, host device 105 may be referred to as a host.

[0024] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on or in response to one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate data retrieval and storage in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as data transfer between host device 105, volatile memory 120, or at least some of non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol, and can interface with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0025] Non-volatile memory 125 may be configured to store digital information (e.g., data) of electronic devices comprising system 100. Accordingly, non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a second protocol, different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer access operation latency compared to volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, nonvolatile memory 125 may have a smaller page size than volatile memory 120, as described herein.

[0026] Volatile memory 120 may be configured to serve as a cache for one or more components (e.g., non-volatile memory 125). For example, volatile memory 120 may store information (e.g., data) of electronic devices containing system 100. Accordingly, volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 may be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0027] In some instances, volatile memory 120 may have shorter access operation latency than non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time than retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size than non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB), and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0028] Although non-volatile memory 125 may be a higher density memory than volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Accordingly, operating volatile memory 120 as a cache can reduce latency in system 100. As an example, data access requests from host device 105 can be satisfied relatively quickly by retrieving data from volatile memory 120 instead of from non-volatile memory 125. To facilitate the operation of volatile memory 120 as a cache, interface controller 115 may include multiple buffers 135. Buffers 135 may be located on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0029] Access operations may also be referred to as access procedures or access routines, and may involve one or more sub-operations performed by one or more components in the memory subsystem 110. Examples of access operations may include storage operations in which data provided by the host device 105 is stored (e.g., written to) volatile memory 120 or non-volatile memory 125 (or both), and retrieval operations in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0030] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by transmitting a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command may target a set of non-volatile memory cells in non-volatile memory 125. In some instances, a set of memory cells may also be referred to as part of memory. Host device 105 may also provide interface controller 115 with data to be written to the set of non-volatile memory cells. Interface controller 115 may temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 may transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 may transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, the interface controller 115 may transfer only the data to the volatile memory 120 (where the data is subsequently transferred to the non-volatile memory 125 during the write-back process).

[0031] In either mode, interface controller 115 may identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a store command. To do this, interface controller 115 may implement a group-associated mapping, wherein each set of one or more non-volatile memory cells in non-volatile memory 125 may be mapped to multiple sets (e.g., rows) of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement an n-way associated mapping, which allows data in one set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Therefore, interface controller 115 can manage volatile memory 120 as a cache of non-volatile memory 125 by referencing the n sets of volatile memory cells associated with the targeted set of non-volatile memory cells. As used herein, a “set” of objects may refer to one or more of objects unless otherwise described or indicated. Although the reference group associative mapping is described, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mapping (such as direct mapping or associative mapping, and other instances).

[0032] After identifying n sets of volatile memory cells associated with a targeted set of non-volatile memory cells, the interface controller 115 can store the data in one or more of the n sets of volatile memory cells. Therefore, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied by retrieving data from the lower-latency volatile memory 120 instead of from the higher-latency non-volatile memory 125. The interface controller 115 can determine which stored data is in the n sets of volatile memory 120 based on or in response to one or more parameters associated with the data stored in the n sets of volatile memory 120, such as validity, usage period, or data modification status. Therefore, the storage commands from the host device 105 can be satisfied entirely (e.g., in write-back mode) or partially (e.g., in write-through mode) by storing the data in the volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 can store tag addresses for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells), indicating non-volatile memory cells with data stored in a given set of volatile memory cells.

[0033] To retrieve data from memory subsystem 110, host device 105 can initiate a retrieval operation (also known as a retrieval process) by transmitting a retrieval command (also known as a retrieval request, read command, or read request) to interface controller 115. The retrieval command may target one or more non-volatile memory cells in non-volatile memory 125. Upon receiving the retrieval command, interface controller 115 may examine the requested data in volatile memory 120. For example, interface controller 115 may examine the requested data in n sets of volatile memory cells associated with the targeted set of non-volatile memory cells. If the requested data is stored in one of the n sets of volatile memory cells (e.g., data stored in the targeted set of non-volatile memory cells), then interface controller 115 may transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining that the requested data is stored in one of the n sets of volatile memory cells, such as...). Figure 4 and 5 (as described in the document), which allows it to be transmitted to the host device 105.

[0034] Generally, the term "hit" can be used to refer to a scenario where the volatile memory 120 stores the data targeted by the host device 105. If one or more sets of n volatile memory cells do not store the requested data (e.g., the n sets of volatile memory cells store data from a set of non-volatile memory cells that are not the targeted set of non-volatile memory cells), then the interface controller 115 may transfer the requested data from the non-volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n sets of volatile memory cells do not store the requested data, as referenced). Figure 4 and 5 (as described), enabling it to be transmitted to host device 105. Generally, the term "miss" can be used to refer to a scenario where the volatile memory 120 does not store the data targeted by host device 105.

[0035] More precisely, a write hit may refer to a scenario where data in volatile memory 120 is associated with a non-volatile memory address targeted by a write command from the host device (e.g., matching data stored at the non-volatile memory address targeted by a write command from the host device); while a write miss may refer to a scenario where no data associated with the non-volatile memory address exists in volatile memory 120.

[0036] In a miss scenario, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied by volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store the data in one of n sets of volatile memory cells associated with a targeted set of non-volatile memory cells. However, the n sets of volatile memory cells may already store data in other sets of non-volatile memory cells. Therefore, to retain this other data, interface controller 115 may transfer the other data to buffer 135-b, so that it can be transferred to non-volatile memory 125 for storage. This process may be referred to as "retrieval," and the data transferred from volatile memory 120 to buffer 135-b may be referred to as "victim" data. In some cases, interface controller 115 may transfer a subset of victim data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 may transmit one or more subsets of victim data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory and no update in the other) may, in some cases, be referred to as “modified” or “dirty” data. In some instances (e.g., if the interface controller is operating in a mode, such as write-back mode), dirty data may be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0037] Therefore, if volatile memory 120 is full, interface controller 115 can execute a recovery procedure to save data from volatile memory 120 to non-volatile memory 125 (e.g., to make room in volatile memory 120 for new data). In some instances, interface controller 115 can execute a "filling" procedure, in which data from non-volatile memory 125 is saved to volatile memory 120. In the event of a miss, interface controller 115 can execute a filling procedure (e.g., to fill volatile memory 120 with relevant data). For example, in the event of a read miss (which occurs when a read command from host device 105 targets data that does not exist in volatile memory 120), interface controller 115 can retrieve the data requested by the read command and, in addition to returning it to the host device, store it in volatile memory 120 (e.g., so that the data can be quickly retrieved in the future).

[0038] Therefore, depending on the hit or miss status of the request (e.g., a read command, a write command) from the host device 105, the memory subsystem 110 can satisfy (or "implement") the request using either volatile memory 120 or non-volatile memory 125. For example, in the case of a read miss, the read command from the host device 105 can be satisfied by the non-volatile memory 125, meaning that the data returned from the host device 105 can originate from the non-volatile memory 125. And in the case of a read hit, the read command from the host device 105 can be satisfied by the volatile memory 120, meaning that the data returned from the host device 105 can originate from the volatile memory 120.

[0039] However, volatile memory 120 and non-volatile memory may have different memory cell access latencies (or "access latencies"), meaning that the latency associated with satisfying a request from host device 105 can be nondeterministic (e.g., unpredictable, unknown). Access latency can refer to the amount of time it takes for memory subsystem 110 to satisfy (or "implement") a request from host device 105 and can be measured relative to request reception. If volatile memory 120 operates in cache mode, the access latency can be further aggravated by the variation in the different architectures of volatile memory 120 and non-volatile memory 125 due to unpredictable use of reclamation and refill procedures. For example, the latency of satisfying a write command (referred to as "write latency") can vary depending on whether a reclamation procedure is implemented to make room for the written data in volatile memory 120.

[0040] According to the techniques described herein, memory subsystem 110 can provide deterministic latency to host device 105 by operating a portion of volatile memory 120 in note mode, among other advantages. If said portion of volatile memory 120 is operated in note mode, memory subsystem 110 can eliminate the recall and fill procedures used in cache mode and can ensure that requests from host device 105 are satisfied by using volatile memory 120. In some instances, memory subsystem 110 can dynamically adjust the size of said portion operating in note mode (e.g., based on or in response to control signaling from host device 105).

[0041] System 100 may include any number of non-transitory computer-readable media supporting note-taking memory in a cache. For example, host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing functions belonging to host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 herein. For example, such instructions, when executed by host device 105 (e.g., host device controller), interface controller 115, volatile memory 120 (e.g., local controller), or non-volatile memory 125 (e.g., local controller), may cause host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 to perform the associated functions described herein.

[0042] Figure 2 An example of a memory subsystem 200 supporting note-taking memory in a cache, according to the examples disclosed herein, is shown. The memory subsystem 200 may be a reference. Figure 1 An example of the described memory subsystem 110. Correspondingly, the memory subsystem 200 may be referenced. Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be referenced respectively. Figure 1 The described interface controller 115, volatile memory 120, and non-volatile memory 125 are examples. Therefore, the interface controller 202 may represent a reference. Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, interface controller 202 can operate volatile memory 204 as a cache for non-volatile memory 206. Operating volatile memory 204 as a cache allows the subsystem to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from those of non-volatile memory 206.

[0043] exist Figure 2 In this diagram, dashed lines between components represent data flows or data communication paths, while solid lines between components represent command flows or command communication paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that may be included in an electronic device. Each subsystem may be referred to as a slice, and in some instances, may be associated with a corresponding channel of the host device.

[0044] Non-volatile memory 206 can be configured to serve as the main memory of a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may comprise one or more FeRAM cell arrays. Each FeRAM cell may include a selection component and a ferroelectric capacitor, and can be accessed by applying appropriate voltages to one or more access lines, such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line may be sensed, for example, in parallel or simultaneously, without having to sense all FeRAM cells coupled to the active word line. Accordingly, the page size of the FeRAM array may differ from (e.g., be smaller than) the DRAM page size. In the context of a memory device, a page may refer to a memory cell in a row (e.g., a group of memory cells with a common row address), and the page size may refer to the number of memory cells or column addresses in a row or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the amount of data processed through various interfaces or the amount of data that can be stored in a row. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0045] The smaller page size of FeRAM arrays offers various efficiency benefits because a single FeRAM cell may require more power to read or write compared to a single DRAM cell. For example, the smaller page size of FeRAM arrays facilitates efficient energy use because a smaller number of FeRAM cells can be activated when the associated information changes little. In some instances, the page size of a FeRAM cell array can vary, for example, dynamically (e.g., during operation of the FeRAM cell array), depending on the nature of the data and commands used for FeRAM operations.

[0046] Although a single FeRAM cell may require more power to read or write than a single DRAM cell, a FeRAM cell can maintain its stored logic state for a long time without an external power supply because the ferroelectric material in the FeRAM cell can maintain a non-zero polarization in the absence of an electric field. Therefore, including an FeRAM array in the non-volatile memory 206 provides power and efficiency benefits compared to volatile memory cells (e.g., DRAM cells in volatile memory 204) because it reduces or eliminates the requirement to perform refresh operations.

[0047] Volatile memory 204 can be configured to serve as a cache for non-volatile memory 206. In some cases, volatile memory 204 may comprise one or more DRAM cell arrays. Each DRAM cell may include a capacitor containing a dielectric material that stores charge representing a programmable state. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory groups (referred to herein as “groups”). For example, volatile memory 204 may comprise sixteen groups. The memory cells of a group may be arranged as a grid or array with intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digital lines (e.g., column lines) and word lines (e.g., row lines) of the memory cell. A row in a group may be referred to as a page, and the page size may refer to the number of columns or memory cells in a row (and thus the amount of data that a row can store). As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0048] Interface controller 202 may include circuitry for interfacing (e.g., communicating) with other devices, such as a host device, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support information communication using one or more communication protocols. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information transmitted using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information transmitted using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0049] Data bus interface 208 may be coupled to data bus 260, transaction bus 222, and buffer circuitry 224. Data bus interface 208 may be configured to transmit and receive data via data bus 260 and to transmit and receive control information (e.g., acknowledgment / negative acknowledgment) or metadata via transaction bus 222. Data bus interface 208 may also be configured to transfer data between data bus 260 and buffer circuitry 224. Data bus 260 and transaction bus 222 may be coupled to interface controller 202 and host device, thereby establishing a conductive path between interface controller 202 and host device. In some instances, the pins of transaction bus 222 may be referred to as Data Mask Inversion (DMI) pins. Although one data bus 260 and one transaction bus 222 are shown, any number of data buses 260 and any number of transaction buses 222 may be coupled to one or more data bus interfaces 208.

[0050] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to transmit and receive commands and addresses via C / A bus 226. Commands and addresses received via C / A bus 226 can be associated with data received or transmitted via data bus 260. C / A bus interface 210 can also be configured to transmit commands and addresses to decoder 228, such that decoder 228 can decode the commands and forward the decoded commands and associated addresses to command circuitry system 230.

[0051] Data bus interface 212 may be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 may be configured to transmit and receive data via data bus 232, which may be coupled to non-volatile memory 206. Data bus interface 212 may also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 may be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 may be configured to receive commands and addresses from memory interface circuitry 234 and forward the commands and addresses to non-volatile memory 206 (e.g., to a local controller of non-volatile memory 206) via C / A bus 236. Commands and addresses transmitted via C / A bus 236 may be associated with data received or transmitted via data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206, thereby establishing a conductive path between the interface controller 202 and the non-volatile memory 206.

[0052] Data bus interface 216 may be coupled to data bus 238 (e.g., data bus 238-a, data bus 238-b) and memory interface circuitry 240. Data bus interface 216 may be configured to transmit and receive data via data bus 238, which may be coupled to volatile memory 204. Data bus interface 216 may also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 may be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 may be configured to receive commands and addresses from memory interface circuitry 240 and forward commands and addresses to volatile memory 204 (e.g., to a local controller of volatile memory 204) via C / A bus 242. Commands and addresses transmitted via C / A bus 242 may be associated with data received or transmitted via data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204, thereby establishing a conductive path between the interface controller 202 and the volatile memory 204.

[0053] In addition to the bus and bus interface for communicating with the coupled device, the interface controller 202 may also include circuitry for operating the non-volatile memory 206 as main memory and the volatile memory 204 as a cache. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0054] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes (e.g., from a host device) command information and stored information from other components (e.g., cache management circuitry system 244, buffer circuitry system 224) and uses said information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to transmit address information (e.g., address bits) to cache management circuitry system 244. In some instances, logic 262 may be circuitry configured to function as a finite state machine (FSM).

[0055] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 234. Buffer circuitry system 224 may include one or more buffer circuits for at least some groups (if not every group) in volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuits (e.g., a memory controller). In one example, volatile memory 204 may contain sixteen groups, and buffer circuitry system 224 may contain sixteen groups of buffer circuits. Each group of buffer circuits may be configured to store data from or for a corresponding group of volatile memory 204 (or both). As an example, the group of buffer circuits for group 0 (BK0) may be configured to store data from or for the first group of volatile memory 204 (or both), and the buffer circuitry for group 15 (BK15) may be configured to store data from or for the sixteenth group of volatile memory 204 (or both).

[0056] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an Open Page Data (OPD) buffer) configured to store data targeted by an access command (e.g., a write command or read command) from the host device; and another buffer (e.g., a Victim Page Data (VPD) buffer) configured to store data for a recall process triggered by the access command. For example, the buffer circuit set for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from the host device. Buffer 220 may be configured to store data transferred from BK0 as part of a recall process triggered by an access command. Each buffer in the buffer circuit set may be configured with a size corresponding to the page size (e.g., storage capacity) of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer may be 2kB. Therefore, in some instances, the size of the buffer can be equal to the page size of the volatile memory 204.

[0057] Cache management circuitry 244 may be coupled to command circuitry 230, engine 246, scheduler 248, and other components. Cache management circuitry 244 may include cache management circuitry groups for one or more groups (e.g., each group) of volatile memory. As an example, cache management circuitry 244 may include sixteen cache management circuitry groups for BK0 through BK15. Each cache management circuitry group may include two memory arrays configurable to store storage information for volatile memory 204. As an example, the cache management circuitry group for BK0 may include memory array 252 (e.g., a cache DRAM (CDRAM) tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array) configured to store storage information for BK0. In some instances, the memory array may also be referred to as an array or buffer. In some cases, the memory array may be or contain volatile memory cells, such as static RAM (SRAM) cells.

[0058] Storage information (or "metadata") may include content information, validity information, or dirty information (or any combination thereof) associated with volatile memory 204, and other instances. Content information (also referred to as tag information or address information) may indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) of a row in volatile memory 204 may indicate which set of one or more non-volatile memory cells currently has data stored in that row. As mentioned, validity information may indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., data that is random or dummy and does not have an expected or important order). And, dirty information may indicate whether the data stored in a set of one or more volatile memory cells of volatile memory 204 is different from the corresponding data stored in a set of one or more non-volatile memory cells of non-volatile memory 206. For example, dirty information may indicate whether the data stored in a set of volatile memory cells has been updated relative to the data stored in non-volatile memory 206.

[0059] Memory array 252 may include memory cells storing storage information (e.g., tag information, validity information, dirty information) of an associated group (e.g., BK0) of volatile memory 204. The storage information may be stored row-by-row (e.g., each row of an associated non-volatile memory group may have corresponding storage information). Interface controller 202 can examine requested data in volatile memory 204 by referencing the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to reference the storage information in memory array 252. For example, using group association mapping, interface controller 202 may reference content information in memory array 252 to determine which set of volatile memory cells (if present) stores the requested data.

[0060] In addition to storing the content information of the volatile memory cells, memory array 252 may also store validity information indicating whether the data in a group of volatile memory cells is actual data (also called valid data) or random data (also called invalid data). For example, volatile memory cells in volatile memory 204 may initially store random data and continue to do so until the volatile memory cells are written with data from a host device or non-volatile memory 206. To track which data is valid, if actual data is stored in one group of volatile memory cells, memory array 252 may be configured to set a bit for each group (e.g., row) of volatile memory cells. This bit may be called a validity bit or validity flag. Like content information, the validity information stored in memory array 252 may be stored row by row. Therefore, in some instances, each validity bit may indicate the validity of data stored in the associated row.

[0061] In some instances, memory array 252 may store dirty information indicating whether a set (e.g., rows) of volatile memory cells contains any dirty data. Like validity information, dirty information stored in memory array 252 may be stored row by row.

[0062] Memory array 254 may be similar to memory array 252 and may also include memory cells that store storage information for groups (e.g., BK0) of volatile memories 204 associated with memory array 252. For example, memory array 254 may store validity information and dirty information for a group of volatile memories 204. However, the storage information stored in memory array 254 may be stored on a sub-block basis rather than a row basis. For example, validity information stored in memory cells of memory array 254 may indicate the validity of data in a subset of volatile memory cells in a row of volatile memories 204.

[0063] As an example, validity information in memory array 254 can indicate the validity of each data subset (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Similarly, dirty information stored in memory cells of memory array 254 can indicate which subsets of volatile memory cells in a row of volatile memory 204 store dirty data. For example, dirty information in memory array 254 can indicate the dirty state of each data subset (e.g., 32B or 64B) stored in a row of BK0 in volatile memory 204. Storing storage information (e.g., tag information, validity information) row by row in memory array 252 allows interface controller 202 to determine whether there is a hit or miss for data in volatile memory 204. The storage of information (e.g., validity information, dirty information) in the memory array 254 based on sub-block storage allows the interface controller 202 to determine one or more subsets of data to be returned to the host device (e.g., during the retrieval process) and one or more subsets of data to be kept in the non-volatile memory 206 (e.g., during the recovery process).

[0064] Each cache management circuitry may also include a corresponding pair of registers coupled to command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and the memory array for the cache management circuitry, as well as other components. For example, the cache management circuitry may include a first register (e.g., register 256, which may be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information, other information, or any combination thereof) from memory array 252 or scheduler 248-b or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a victim page tag (VPT) register) configured to receive storage information (e.g., validity information, dirty information, or both) from memory array 254 and scheduler 248-a or both. Information in registers 256 and 258 may be passed to command circuitry 230 and engine 246 to enable decisions by these components. For example, the command circuitry 230 may issue a command to read non-volatile memory 206 or volatile memory 204 based on or in response to stored information in register 256 or register 258 or both.

[0065] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive stored information from various components and issue commands to scheduler 248 based on the stored information. For example, if interface controller 202 is in a first mode (e.g., write-through mode), then engine 246-a can issue a command to scheduler 248-b, and in response, scheduler 248-b initiates or facilitates the transfer of data from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, if interface controller 202 is in a second mode (e.g., write-back mode), then engine 246-a can issue a command to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate the transfer of data from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent recovery process.

[0066] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue a command to scheduler 248-a to initiate or facilitate the transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of a retrieval process). If buffer 220 holds a set of data (e.g., victim data) transferred from volatile memory 204, then engine 246-b may indicate that one or more subsets of said set of data in buffer 220 should be transferred to non-volatile memory 206 (e.g., 64B of which).

[0067] Scheduler 248-a can be coupled to various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. Commands issued by scheduler 248-a can be based on or in response to commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled to various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. Commands issued by scheduler 248-b can be based on or in response to commands from command circuitry 230 or engine 246-a, or both.

[0068] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to forward commands issued by the memory interface circuitry 234 to the local controller in the non-volatile memory 206 via the C / A bus 236. Furthermore, the memory interface circuitry 234 can transmit or receive data from the non-volatile memory 206 via the data bus 232. In some instances, the commands issued by the memory interface circuitry 234 may be supported by the non-volatile memory 206 but not by the volatile memory 204 (e.g., the commands issued by the memory interface circuitry 234 may differ from the commands issued by the memory interface circuitry 240).

[0069] The memory interface circuitry 240 can communicate with the volatile memory 204 via one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuitry 240 can prompt the C / A bus interface 264 to forward commands issued by the memory interface circuitry 240 to the local controller of the volatile memory 204 via the C / A bus 242. Furthermore, the memory interface circuitry 240 can transmit or receive data from the volatile memory 204 via one or more data buses 238. In some instances, commands issued by the memory interface circuitry 240 may be supported by the volatile memory 204 but not by the non-volatile memory 206 (e.g., commands issued by the memory interface circuitry 240 may differ from commands issued by the memory interface circuitry 234).

[0070] The components of interface controller 202 can together operate non-volatile memory 206 as main memory and volatile memory 204 as cache. Such operations can be prompted by one or more access commands (e.g., read / retrieve command / request and write / store command / request) received from the host device.

[0071] In some instances, interface controller 202 may receive a store command from the host device. The store command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command may include or be accompanied by address bits for a memory address of non-volatile memory 206. Data to be stored may be received via data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, interface controller 202 may transmit data only to volatile memory 204.

[0072] In either mode, the interface controller 202 may first check whether the volatile memory 204 has memory cells available for storing data. To do this, the command circuitry 230 may reference the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups (e.g., rows) of volatile memory cells associated with the memory address are empty (e.g., storing random or invalid data). For example, the command circuitry 230 may determine whether one or more of the n groups (e.g., rows) of volatile memory cells are available (or unavailable) based on tag information and validity information stored in the memory array 252. In some cases, a group of volatile memory cells in the volatile memory 204 may be referred to as a line, cache line, or row.

[0073] If one of the associated n sets of volatile memory cells is available to store information, the interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in said set of volatile memory cells. However, if none of the associated sets of volatile memory cells are empty, the interface controller 202 can initiate a reclamation process to free up space for data in volatile memory 204. The reclamation process may involve transferring victim data from one of the associated n sets of volatile memory cells to buffer 220. Dirty information of the victim data can be transferred from memory array 254 to register 258 to identify a dirty subset of the victim data. After the victim data is stored in buffer 220, new data can be transferred from buffer 218 to volatile memory 204, and victim data can be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of the old data is transferred to non-volatile memory 206, and a clean subset (e.g., an unmodified subset) is discarded. The dirty subset can be identified by engine 246-b during the recovery process based on or in response to dirty information transferred from memory array 254 to register 258.

[0074] In another example, interface controller 202 may receive commands, such as retrieval commands, from a host device. Retrieval commands may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The retrieval command may contain address bits for a memory address of non-volatile memory 206. Before attempting to access the targeted memory address of non-volatile memory 206, interface controller 202 may check whether volatile memory 204 stores data. To do this, command circuitry 230 may reference memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups (e.g., rows) of volatile memory cells associated with the memory address store the requested data (e.g., whether one or more of the n groups of volatile memory cells associated with the memory address store or not). If the requested data is stored in volatile memory 204, then interface controller 202 may transfer the requested data to buffer 218 for transmission to the host device via data bus 260.

[0075] If the requested data is not stored in volatile memory 204 (e.g., the requested data may be stored in non-volatile memory 206 or another location), then interface controller 202 may retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Alternatively, interface controller 202 may transfer the requested data from buffer 218 to volatile memory 204, allowing for low-latency data access during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 may first determine whether one or more of the associated n sets of volatile memory cells are available to store the requested data. Interface controller 202 may determine the availability of the associated n sets of volatile memory cells by communicating with the associated cache management circuitry. If the associated set of volatile memory cells is available, then interface controller 202 may transfer the data in buffer 218 to volatile memory 204 without performing a eviction process. Otherwise, the interface controller 202 may transfer data from the buffer 218 to the volatile memory 204 after performing the recovery process.

[0076] The memory subsystem 200 can be implemented in one or more configurations, including single-chip and multi-chip versions. The multi-chip version may include one or more components of the memory subsystem 200, including an interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip containing the other components of the memory subsystem 200. For example, in a multi-chip version, a corresponding individual chip may contain each of the interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, the single-chip version may contain the interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0077] Therefore, memory subsystem 200 can operate volatile memory 204 as a cache of non-volatile memory 206. This allows memory subsystem 110 to interface with the host device through volatile memory 204 while providing the advantages of non-volatile memory 206. However, operating volatile memory 204 as a cache can prevent memory subsystem 200 from satisfying requests from the host device with deterministic latency, for example, because some requests are satisfied by volatile memory 204—which has relatively short access operation latency—while other requests are satisfied by non-volatile memory 206—which has relatively long access operation latency. To provide deterministic latency and other advantages to the host device, memory subsystem 200 can operate one or more portions of volatile memory 204 in note mode and one or more portions in cache mode, such as one or more of the remaining portions in some instances.

[0078] Figure 3 An example of a device 300 supporting note-taking memory in a cache, according to the examples disclosed herein, is shown. Device 300 may be a reference. Figure 1 The described memory subsystem 110 or reference Figure 2 An example of the described memory subsystem 200. The device may include an interface controller 302, volatile memory 305, and non-volatile memory 310, which may be coupled to each other via one or more transmission lines, buses, or both. The interface controller 302 may also include one or more control registers 320. As described herein, the device 300 may operate different portions of the volatile memory 305 in different operating modes (e.g., note mode and cache mode). The device 300 may also dynamically change the operating mode of one or more portions of the volatile memory 305 (e.g., based on or in response to control register 320 or one or more other conditions). In some instances, note mode and cache mode may be referred to as a first mode and a second mode.

[0079] Device 300 is shown and described with reference to a specific configuration of volatile memory 305 and non-volatile memory 310. However, other configurations are also considered.

[0080] Volatile memory 305 may comprise multiple groups (e.g., sixteen groups) and may be conceptually or logically divided into portions containing rows of each group (or one or more of these groups). For example, a portion may contain a total of x rows, consisting of y rows (e.g., 250 rows) from each group (or one or more of these groups). Each portion may be associated with a corresponding track identifier (ID) that distinguishes it from the other portion. Thus, portions may be represented as a track 0 portion through a track 15 portion (in the sixteen-track instance). Each track may be associated with a corresponding segment of non-volatile memory 310, which may contain rows of non-volatile memory 310 permitted for recall and fill procedures of the portion of volatile memory 305 associated with the track. As an example, interface controller 302 may use memory cells in the track 0 segment of non-volatile memory 310 to perform recall and fill procedures of memory cells in the track 0 portion of volatile memory 305. Terms and sections, as well as other appropriate terms (e.g., region, subsection, subset or fragment, or any combination thereof), are used interchangeably.

[0081] Like volatile memory 305, non-volatile memory 310 may contain multiple groups (e.g., sixteen groups) and may be conceptually or logically divided into segments containing rows of each group or one or more of them. Each segment may be associated with a corresponding track ID that distinguishes the segments. Thus, a segment may be represented as a track 0 segment to a track 15 segment (in the sixteen-track instance). In some instances, the segments of non-volatile memory 310 may be further divided into (or logically included) memory cell blocks (referred to as slices). Parts and segments associated with the same track ID are... Figure 3 The same shading pattern is used to illustrate this.

[0082] Interface controller 302 can operate one or more portions of volatile memory 305 in note mode to provide deterministic latency to the host device, and can operate other portions (e.g., the remainder) in cache mode to provide other advantages (e.g., the advantages of non-volatile memory 310 as main memory). Interface controller 302 can operate volatile memory 305 and non-volatile memory 310 by sending commands to them, as referenced in [reference]. Figure 1 and 2 As described.

[0083] As an example of a split mode, the interface controller 302 can operate channel 0 and channel 2 in note mode and some or all of the remaining channels in cache mode. If a channel operates in note mode, the interface controller 302 can directly use the volatile memory 305 to satisfy requests associated with that channel (e.g., from the host device) and can avoid interaction with the non-volatile memory 310 (for those requests), such as reclaiming and filling procedures.

[0084] In some instances, the interface controller 302 can expand or shrink the size of the note by changing the operating mode of one or more sections (this can be referred to as adding or removing sections from the note). For example, continuing the discussion above, the interface controller 302 can increase the size of the note from two sections to three sections by changing the operating mode of section 1 from cache mode to note mode. As another example, the interface controller 302 can reduce the size of the note from two sections to one section by changing the operating mode of section 0 from note mode to cache mode.

[0085] Interface controller 302 can operate various parts based on output pins of control register 320, which indicate the operating mode of each part. Interface controller 302 can monitor the state of the output pins of control register 320, where each output pin can be associated with a corresponding part of volatile memory 305. For example, output pin PW0 can be associated with track 0, output pin PW1 with track 1, and so on. A first state of an output pin (e.g., logic 0) can be associated with a first operating mode (e.g., cache mode) (e.g., indicating the first operating mode, representing the first operating mode), and a second state of an output pin (e.g., logic 1) can be associated with a second operating mode (e.g., notepad mode). Therefore, interface controller 302 can operate the parts in the operating mode associated with the current state of the output pins associated with each part.

[0086] In some instances, the interface controller 302 can adjust the size of the notepad (and thus the size of the cache) based on the output pins of the control register 320, which can be updated according to control signals received from the host device. For example, if the interface controller 302 receives a control signal from the host device to change the state of the output pin from a first state to a second state, then the interface controller 302 can change the operating mode of that portion from cache mode to notepad mode. Conversely, if the interface controller 302 receives a signal from the host device to change the state of the output pin from a second state to a first state, then the interface controller 302 can change the operating mode of that portion from notepad mode to cache mode.

[0087] In some instances, the output pin of control register 320 may be the output pin of a flip-flop circuit. The output pin may also be referred to as a control pin or other suitable terminology, and the state of the output pin may be referred to as a bit value, flag value, logic value, voltage value, or other suitable terminology.

[0088] Compared to other techniques, in addition to providing deterministic latency, using one or more sections as notes can also provide power savings. For example, if sections of volatile memory 305 operate in note mode, the interface controller 302 can save power by powering off sections of non-volatile memory 310 that are associated with those sections. This technique is possible because note mode is independent of non-volatile memory 310, meaning that requests from host devices that indicate note sections can be satisfied without accessing non-volatile memory 310 as a satisfied section (of course, non-volatile memory 310 can still be accessed to satisfy requests from cache sections of volatile memory 305). Therefore, although section n operates in note mode, section n of non-volatile memory 310 can be powered off, thereby saving power.

[0089] Figure 4 An example of a process flow 400 supporting note-taking memory in a cache, according to the examples disclosed herein, is shown. Process flow 400 can be found in references. Figure 1 The described memory subsystem 110 or interface controller 115, reference Figure 2 The described memory subsystem 200 or interface controller 202 or reference Figure 3 The described device 300 or interface controller 302 is implemented. However, other types of devices may also implement process flow 400. Process flow 400 may illustrate device operation that dynamically increases the note size in volatile memory.

[0090] For ease of reference, process flow 400 is described with reference to an apparatus. For example, aspects of process flow 400 may be implemented by means including volatile memory and non-volatile memory. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, these instructions, when executed by a controller, may cause the controller to perform operations of process flow 400.

[0091] At 405, a portion of the volatile memory can operate in cache mode. For example, a device (e.g., via interface controller 302) can operate track 0 in cache mode. Track 0 can operate in cache mode based on or in response to the state of an output pin (e.g., output pin PW0) associated with track 0. Operating track 0 in cache mode may include satisfying specific missed requests (e.g., those requests for volatile memory cells in track 0) using non-volatile memory, and moving data between track 0 and non-volatile memory using a eviction and filling procedure. Additionally, operating track 0 in cache mode may include updating the storage information (e.g., validity information, dirty information, tag information) of those rows when data is read from and written to those rows in track 0. The storage information may also be referred to as metadata and may facilitate the operation of volatile memory 305 in cache mode (e.g., by enabling eviction and filling procedures, and other procedures).

[0092] At 410, it can be determined whether the operating mode of the portion is a notepad mode. For example, the device can determine whether the state of the output pin associated with channel 0 is set to a first state associated with cache mode or a second state associated with notepad mode. Interface controller 302 can determine the operating mode of channel 0 by monitoring (e.g., continuously, intermittently, periodically) the state of the output pin associated with channel 0. In some instances, interface controller 302 can change the state of the output pin before operation at 410 (e.g., based on or in response to control signaling from the host device). The host device can determine to change the operating mode of channel 0 based on or in response to another metric, such as latency requirements, expected access frequency, or a set of data to be stored in channel 0. Changing the state of the output pin can also be referred to as masking the output pin.

[0093] If it is determined at 410 that the operating mode of the portion is cache mode, then the device may return to 405 and continue operating the portion in cache mode. If it is determined at 410 that the operating mode of the portion is note mode, then the device may proceed to 415.

[0094] At 415, one or more recall procedures may be executed. For example, the device may execute one or more recall procedures for track 0. The recall procedure may be part of cache mode and executed before track 0 operates in note mode at 420. The recall procedure may be executed to save data (e.g., dirty data) from track 0 in non-volatile memory 310, so that the data can be quickly accessed (if track 0 subsequently returns to cache mode). As an example, dirty data from one or more rows of track 0 may be stored in a track 0 segment associated with track 0. At 420, the storage information of said section may be updated based on or in response to the operation at 415.

[0095] In some instances, the device may perform a retrieval procedure based on or in response to one or more signals from the host device indicating that data in section 0 will be retained. If the host device does not indicate that data should be retained, the device may discard (e.g., overwrite) the data without first saving it to non-volatile memory 310.

[0096] At 425, a segment of non-volatile memory associated with the portion of volatile memory can be de-energized. For example, the device can de-energize track 0 of non-volatile memory 310 (e.g., to save power) because the device does not access track 0 when the track 0 portion is operating in note-taking mode. De-energizing a segment may include disconnecting components of the portion from one or more power sources or operating the portion in a low-power mode.

[0097] At 430, the portion can be operated in note mode. For example, the device can operate portion 0 in note mode based on or in response to a note mode indication from the state of an output pin. Operating the portion in note mode can include using the portion to satisfy requests for the portion and avoiding interaction with non-volatile memory (e.g., a reclaim procedure, a fill procedure) to satisfy those requests. Because the data in the portion is not saved to non-volatile memory during operation in note mode, requests for the portion from the host device are guaranteed to be hits, which allows the interface controller 302 to use volatile memory to satisfy requests (and thus provides deterministic latency). Operating the portion in note mode can also include maintaining the stored information of the portion in the state it was in after entering note mode (or, in other words, after exiting cache mode).

[0098] Therefore, the size of a note in volatile memory can be increased by changing the operating mode of a portion of it from cache mode to note mode.

[0099] Alternative instances of the above may be implemented, in which some operations may be performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, some operations may be performed multiple times, or certain combinations of operations may be repeated or cyclical.

[0100] Figure 5 An example of a process flow 500 supporting note-taking memory in a cache, according to the examples disclosed herein, is shown. Process flow 500 can be found in references. Figure 1 The described memory subsystem 110 or interface controller 115, reference Figure 2 The described memory subsystem 200 or interface controller 202 or reference Figure 3 The described device 300 or interface controller 302 is implemented. However, other types of devices may also implement process flow 500. Process flow 500 may illustrate device operation that dynamically reduces the size of notes in volatile memory.

[0101] For ease of reference, process flow 500 is described with reference to an apparatus. For example, aspects of process flow 500 may be implemented by means including volatile memory and non-volatile memory. Alternatively, aspects of process flow 500 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, these instructions, when executed by a controller, may cause the controller to perform operations of process flow 500.

[0102] At 505, a portion of the volatile memory can be operated in note mode. For example, the device may (e.g., via interface controller 302) operate the portion in note mode based on or in response to a note mode indication from an output pin. Operating the portion in note mode may include using the portion to satisfy requests for the portion and avoiding interaction with non-volatile memory (e.g., reclaiming a program, filling a program) to satisfy those requests. Operating the portion in note mode may also include maintaining the stored information of the portion in the state it was in upon entering note mode (or, in other words, upon exiting cache mode).

[0103] At 510, it can be determined whether the operating mode of the portion is cache mode. For example, the device can determine whether the state of the output pin associated with track 0 is set to a first state associated with cache mode or a second state associated with notepad mode. Interface controller 302 can determine the operating mode of track 0 by monitoring (e.g., continuously, intermittently, periodically) the state of the output pin associated with track 0. In some instances, interface controller 302 can change the state of the output pin before operation at 510 (e.g., based on or in response to control signaling from the host device). The host device can determine to change the operating mode of track 0 based on or in response to another metric, such as latency requirements, expected access frequency, or a set of data to be stored in track 0.

[0104] If it is determined at 510 that the operating mode of the portion is note mode, then the device may return to 505 and continue operating the portion in note mode. If it is determined at 510 that the operating mode of the portion is cache mode, then the device may proceed to 515.

[0105] At 515, a segment of non-volatile memory associated with the portion can be powered. For example, the device can power track 0 segment so that a reclamation procedure and a filling procedure, etc., can be performed on the portion during operation in cache mode. Powering a segment may involve connecting components in the segment to one or more power sources or switching from a low-power mode to a high-power mode.

[0106] At 520, the portion can operate in cache mode. For example, the device can operate the lane 0 portion in cache mode based on or in response to an output pin indicating cache mode. Operating the lane 0 portion in cache mode may include using non-volatile memory to satisfy specific missed requests (e.g., those requests for volatile memory cells in the lane 0 portion), and using a eviction and filling procedure to move data between the lane 0 portion and non-volatile memory. Additionally, operating the lane 0 portion in cache mode may include updating the storage information (e.g., validity information, dirty information, tag information) of those rows when data is read from and written to those rows in the lane 0 portion.

[0107] If the portion operates in cache mode, the device can determine the hit or miss status of the request to determine which memory to use to satisfy the request. For example, at 525, a request from a host device can be received. For instance, the device can receive a read request for a memory cell in track 0. At 530, it can be determined whether the read request is a hit or a miss. If the read request is determined to be a hit at 530, the device can proceed to 535 and satisfy the request using track 0 of the volatile memory. If the read request is for data stored in the volatile memory (e.g., associated with or indicating the data), then the read request is a hit. If the read request is determined to be a miss at 530, then the device can proceed to 540. If the read request is for data that is not present in the volatile memory, then the read request is a miss.

[0108] At point 540, non-volatile memory can be used to satisfy the read request. For example, the device can read the data targeted by the read request from the non-volatile memory and transfer the data to the host device. At point 545, a padding operation can be performed (e.g., to enable rapid transfer of data from volatile memory to the host device in the event of a subsequent read request for the data). For example, the device can store data from non-volatile memory to volatile memory. The data involved in the padding operation can be the data targeted by the read request.

[0109] If the request received at 525 is a write request for a memory cell in track 0, then at 530 it can be determined whether the write request is a hit or a miss. If the write request is determined to be a hit at 530, the device can proceed to 535 and satisfy the request using track 0 of the volatile memory. If the write request is for data stored in the volatile memory (e.g., associated with or indicating the data), then the write request is a hit. If the write request is determined to be a miss at 530, then the device can proceed to 545 (skipping 540) and perform a filling procedure. If the write request is for data that does not exist in the volatile memory, then the write request is a miss. After performing filling at 545, the device can satisfy the write request by updating some or all of the data in the volatile memory with dirty data associated with the write request.

[0110] Therefore, the size of a note in volatile memory can be reduced by changing the operating mode of a portion of it from cache mode to note mode.

[0111] Alternative instances of the above may be implemented, in which some operations may be performed in a different order than described, in parallel, or not at all. In some cases, operations may include additional features not mentioned below, or additional operations may be added. Furthermore, some operations may be performed multiple times, or certain combinations of operations may be repeated or cyclical.

[0112] Figure 6 A block diagram 600 illustrates an interface controller 620 supporting note-taking memory in a cache, according to an example disclosed herein. The interface controller 620 may be a reference... Figures 1 to 5 Examples of various aspects of the described interface controller. Interface controller 620 or its various components may be examples of components used to perform various aspects of the note-taking memory in the cache described herein. For example, interface controller 620 may include controller 625, recall circuitry 630, fill circuitry 635, receive circuitry 640, non-volatile memory 645, volatile memory 650, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0113] Controller 625 may be or include logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Retrieval circuitry 630 may be or include logic, circuitry, a controller, registers, buffers, a data bus, a data bus interface, components forming a data path, or other components capable of performing the functions described herein. Filling circuitry 635 may be or include logic, circuitry, a controller, registers, buffers, a data bus, a data bus interface, components forming a data path, or other components capable of performing the functions described herein. Receiving circuitry 640 may be or include a data bus, a data bus interface, logic, circuitry, a processor, a controller, or other components capable of performing the functions described herein. Non-volatile memory 645 may be an example of the non-volatile memory described herein and may be or include a memory die, a memory array, a memory device, or other components capable of performing the functions described herein. Volatile memory 650 may be an example of the volatile memory described herein and may be or include a memory die, a memory array, a memory device, or other components capable of performing the functions described herein.

[0114] Controller 625 may be configured or otherwise support means for operating a portion of volatile memory in a cache mode having a nondeterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and non-volatile memory. In some instances, controller 625 may be configured or otherwise support means for monitoring output pins of registers in the memory device, the output pins being associated with the portion and indicating the operating mode of the portion. In some instances, controller 625 may be configured or otherwise support means for determining, at least in part, based on monitoring the output pins of registers, whether to change the operating mode of the portion from cache mode to a note mode having a deterministic latency for satisfying a request from a host device, the note mode being used to operate the portion independently of non-volatile memory. In some instances, controller 625 may be configured or otherwise support means for operating the portion of volatile memory in note mode, at least in part, based on determining that the operating mode of the portion has been changed.

[0115] In some instances, to support the operation of the portion of volatile memory in cache mode, the recovery circuitry 630 may be configured or otherwise supported to support means for performing a recovery procedure to store data from the portion in non-volatile memory. In some instances, to support the operation of the portion of volatile memory in cache mode, the filling circuitry 635 may be configured or otherwise supported to support means for performing a filling procedure to store data from non-volatile memory in the portion.

[0116] In some instances, to support the operation of the volatile memory portion in note mode, controller 625 may be configured or otherwise support components for avoiding the execution of recall and fill procedures.

[0117] In some instances, to support the operation of the portion of volatile memory in cache mode, controller 625 may be configured or otherwise support components for updating metadata to operate the portion in cache mode and enabling data movement between the portion and non-volatile memory.

[0118] In some instances, the receiving circuitry 640 may be configured or otherwise supported for receiving from the host device a signal that changes the state of an output pin from a first state associated with a cache mode to a second state associated with a note mode, wherein the determination is at least in part based on the change of the output pin's state from the first state to the second state.

[0119] In some instances, the non-volatile memory 645 may be configured or otherwise supported for storing a set of data from the volatile memory in a portion of the non-volatile memory, at least in part based on determining a change in operating mode and prior to operating the portion in note mode. In some instances, the non-volatile memory 645 may be configured or otherwise supported for powering off the portion of the non-volatile memory after storing the set of data and at least in part based on determining that the portion of the volatile memory is operating in note mode.

[0120] In some instances, controller 625 may be configured or otherwise supported to determine whether to operate the portion of volatile memory in cache mode after operating the portion in note mode. In some instances, volatile memory 650 may be configured or otherwise supported to store, at least in part, a set of data from a non-volatile memory based on a request from a host device during operation of the portion in cache mode, after determining that the portion is to be operated in cache mode.

[0121] In some instances, controller 625 may be configured or otherwise support means for determining whether the state of the second output pin of the register has changed from a first state associated with cache mode to a second state associated with note mode. In some instances, controller 625 may be configured or otherwise support means for changing the operating mode of a second portion associated with the second output pin from cache mode to note mode, at least in part, based on the determination that the state of the second output pin has changed from the first state to the second state.

[0122] In some instances, controller 625 may be configured or otherwise supported to include means for determining whether the state of the second output pin of the register has changed from a second state associated with note mode to a first state associated with cache mode. In some instances, controller 625 may be configured or otherwise supported to include means for changing the operating mode of a second portion associated with the second output pin from note mode to cache mode, at least in part, based on the determination that the state of the second output pin has changed from the second state to the first state.

[0123] In some instances, the portion contains rows from multiple groups of volatile memory.

[0124] In some instances, controller 625 may be configured or otherwise support means for operating a portion of volatile memory in a note mode having deterministic latency for satisfying a host device's request, the note mode being used to operate the portion independently of non-volatile memory. In some instances, controller 625 may be configured or otherwise support means for monitoring output pins of registers in the device, the output pins being associated with the portion and indicating the operating mode of the portion. In some instances, controller 625 may be configured or otherwise support means for determining, at least in part, based on monitoring the output pins of registers, whether to change the operating mode of the portion from note mode to a cache mode having non-deterministic latency for satisfying a host device's request, the cache mode being associated with data movement between the portion and non-volatile memory. In some instances, controller 625 may be configured or otherwise support means for operating the portion of volatile memory in cache mode, at least in part, based on determining a change in the operating mode of the portion.

[0125] In some instances, the receiving circuit 640 may be configured or otherwise supported for receiving from the host device a signal that changes the state of an output pin from a second state associated with a note mode to a first state associated with a cache mode, wherein the determination is at least in part based on the change of the output pin state from the second state to the first state.

[0126] Figure 7 A flowchart illustrating an example disclosed herein demonstrates a method 700 for supporting note-taking memory in a cache. Operation of method 700 may be implemented by an interface controller or its components as described herein. For example, operation of method 700 may be provided by a reference... Figures 1 to 6 The described interface controller performs the functions described. In some instances, the interface controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the interface controller may use dedicated hardware to perform aspects of the described functions.

[0127] At 705, the method may include operating a portion of volatile memory in a cache mode having nondeterministic latency for satisfying requests from a host device, the cache mode being associated with data movement between the portion and nonvolatile memory. Operation 705 may be performed according to the examples disclosed herein. In some instances, aspects of operation 705 may be referenced from... Figure 6 The described controller 625 is executed.

[0128] At 710, the method may include monitoring an output pin of a register in the memory device, the output pin being associated with and indicating an operating mode of the portion. Operation 710 may be performed according to the examples disclosed herein. In some examples, aspects of operation 710 may be referenced from... Figure 6 The described controller 625 is executed.

[0129] At 715, the method may include determining, at least in part, based on the output pin of a monitoring register, whether to change the operating mode of the portion from cache mode to a notepad mode with a deterministic delay for satisfying a request from a host device, the notepad mode being used to operate the portion independently of non-volatile memory. Operation 715 may be performed according to the examples disclosed herein. In some examples, aspects of operation 715 may be referenced from... Figure 6 The described controller 625 is executed.

[0130] At 720, the method may include operating said portion of the volatile memory in a note-taking mode, at least in part, based on determining a change in the operating mode of said portion. Operation 720 may be performed according to the examples disclosed herein. In some examples, aspects of operation 720 may be referenced... Figure 6 The described controller 625 is executed.

[0131] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: operating a portion of volatile memory in a cache mode having a nondeterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and non-volatile memory; monitoring an output pin of a register in the memory device, the output pin being associated with the portion and indicating the operating mode of the portion; determining, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from cache mode to a note mode having a deterministic latency for satisfying a request from a host device, the note mode being used to operate the portion independently of the non-volatile memory; and operating the portion of volatile memory in note mode at least in part based on determining the change in the operating mode of the portion.

[0132] In some instances of the method 700 and apparatus described herein, the portion of the volatile memory operating in cache mode may include operations, features, circuitry, logic, components, or instructions for: performing a retrieval procedure to store data from the portion in non-volatile memory, and performing a filling procedure to store data from the non-volatile memory in the portion.

[0133] In some instances of the method 700 and device described herein, the portion of the volatile memory operating in note mode may include operations, features, circuitry, logic, components, or instructions for avoiding the execution of recall and refill procedures.

[0134] In some instances of the method 700 and apparatus described herein, the portion of the volatile memory operating in cache mode may include operations, features, circuitry, logic, components, or instructions for updating metadata to operate the portion in cache mode and enabling data movement between the portion and non-volatile memory.

[0135] Some examples of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving from a host device a signal that changes the state of an output pin from a first state associated with a cache mode to a second state associated with a note mode, wherein the determination may be based at least in part on the change of the output pin's state from the first state to the second state.

[0136] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: storing a set of data from the portion of volatile memory in a portion of non-volatile memory, at least in part based on determining a change in operating mode and before operating the portion in note mode; and after storing the set of data and at least in part based on determining that operating the portion of volatile memory in note mode, de-energizing the portion of non-volatile memory.

[0137] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for: operating the portion of volatile memory in note mode and then determining whether to operate the portion in cache mode; and after determining that the portion is to be operated in cache mode, storing the set of data in the portion at least in part based on a request from the host device for a set of data from non-volatile memory and during the operation of the portion in cache mode.

[0138] Some instances of the method 700 and device described herein may further include operations, features, circuitry, logic, components, or instructions for: determining whether the state of a second output pin of a register may have changed from a first state associated with a cache mode to a second state associated with a note mode, and at least in part based on the determination that the state of the second output pin may have changed from the first state to the second state, changing the operating mode of a second portion associated with the second output pin from cache mode to note mode.

[0139] Some instances of the method 700 and device described herein may further include operations, features, circuitry, logic, components, or instructions for: determining whether the state of a second output pin of a register may have changed from a second state associated with a notepad mode to a first state associated with a cache mode, and at least in part based on the determination that the state of the second output pin may have changed from the second state to the first state, changing the operating mode of a second portion associated with the second output pin from notepad mode to cache mode.

[0140] In some instances of the method 700 and apparatus described herein, the portion comprises rows from multiple groups of volatile memory.

[0141] Figure 8 A flowchart illustrating an example disclosed herein demonstrates a method 800 for supporting note-taking memory in a cache. Operation of method 800 may be implemented by an interface controller or its components as described herein. For example, operation of method 800 may be provided by a reference... Figures 1 to 6The described interface controller performs the functions described. In some instances, the interface controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the interface controller may use dedicated hardware to perform aspects of the described functions.

[0142] At 805, the method may include operating a portion of volatile memory in a note-taking mode having a deterministic delay for satisfying a request from a host device, the note-taking mode being used to operate said portion independently of non-volatile memory. Operation 805 may be performed according to the examples disclosed herein. In some examples, aspects of operation 805 may be referenced from... Figure 6 The described controller 625 is executed.

[0143] At 810, the method may include monitoring an output pin of a register in the device, the output pin being associated with and indicating the operating mode of the portion. Operation 810 may be performed according to the examples disclosed herein. In some examples, aspects of operation 810 may be referenced... Figure 6 The described controller 625 is executed.

[0144] At 815, the method may include determining, at least in part, based on the output pin of a monitoring register, whether to change the operating mode of the portion from a note mode to a cache mode with nondeterministic latency for satisfying requests from a host device, the cache mode being associated with data movement between the portion and nonvolatile memory. Operation 815 may be performed according to the examples disclosed herein. In some examples, aspects of operation 815 may be referenced from... Figure 6 The described controller 625 is executed.

[0145] At 820, the method may include operating said portion of the volatile memory in cache mode, at least in part, based on determining a change in the operating mode of said portion. Operation 820 may be performed according to the examples disclosed herein. In some instances, aspects of operation 820 may be derived from references... Figure 6 The described controller 625 is executed.

[0146] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: operating a portion of volatile memory in a note mode having a deterministic latency for satisfying a request from a host device, the note mode being used to operate the portion independently of non-volatile memory; monitoring an output pin of a register in the device associated with and indicating the operating mode of the portion; determining, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from note mode to a cache mode having a non-deterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and non-volatile memory; and operating the portion of volatile memory in cache mode at least in part based on determining the change in the operating mode of the portion.

[0147] Some examples of the method 800 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for receiving from a host device a signal to change the state of an output pin from a second state associated with a note mode to a first state associated with a cache mode, wherein the determination may be based at least in part on the change of the output pin's state from the second state to the first state.

[0148] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0149] Describe another device. The device may include: non-volatile memory; volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller being configured to cause the device to: operate a portion of the volatile memory in a cache mode having a nondeterministic latency for satisfying a request from a host device, the cache mode being associated with data movement between the portion and the non-volatile memory; monitor an output pin of a register in the device, the output pin being associated with the portion and indicating an operating mode of the portion; determine, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from the cache mode to a note mode having a deterministic latency for satisfying a request from the host device, the note mode being used to operate the portion independently of the non-volatile memory; and operate the portion of the volatile memory in the note mode, at least in part based on determining the change in the operating mode of the portion.

[0150] In some instances, the device may include performing a recall procedure during operation of the portion in the cache mode to store data from the portion in the non-volatile memory, and performing a fill procedure during operation of the portion in the cache mode to store data from the non-volatile memory in the portion.

[0151] In some instances, the device may include a component that prevents the recall and fill procedures from being performed during operation in the note mode.

[0152] In some instances of the device, the interface controller may further be configured to enable the device to update metadata during operation of the portion in the cache mode, thereby operating the portion in the cache mode and enabling data movement between the portion and the non-volatile memory.

[0153] In some instances, the device may include receiving from the host device a signal that changes the state of the output pin from a first state associated with the cache mode to a second state associated with the note mode, wherein the determination may be based at least in part on the change of the state of the output pin from the first state to the second state.

[0154] In some instances, the device may include storing a set of data from the portion of the non-volatile memory in a portion of the non-volatile memory, at least in part based on determining to change the operating mode and before operating the portion in the note mode, and after storing the set of data and at least in part based on determining to operate the portion of the non-volatile memory in the note mode, de-energizing the portion of the non-volatile memory.

[0155] In some instances, the device may include determining whether to operate the portion of the volatile memory in the cache mode after operating the portion in the note mode, and after determining to operate the portion in the cache mode, storing the set of data in the portion at least in part based on a request from the host device for a set of data from the non-volatile memory and during the operation of the portion in the cache mode.

[0156] In some instances, the device may include determining whether the state of the second output pin of the register may have changed from a first state associated with the cache mode to a second state associated with the note mode, and at least in part based on determining that the state of the second output pin may have changed from the first state to the second state, changing the operating mode of a second portion associated with the second output pin from the cache mode to the note mode.

[0157] In some instances, the device may include determining whether the state of the second output pin of the register may have changed from a second state associated with the note mode to a first state associated with the cache mode, and at least in part based on determining that the state of the second output pin may have changed from the second state to the first state, changing the operating mode of a second portion associated with the second output pin from the note mode to the cache mode.

[0158] In some instances of the device, the portion comprises rows from multiple groups of the volatile memory.

[0159] Describe another device. The device may include: non-volatile memory; volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller being configured to cause the device to: operate a portion of the volatile memory in a note mode having deterministic latency for satisfying a request from a host device, the note mode being used to operate the portion independently of the non-volatile memory; monitor an output pin of a register in the device, the output pin being associated with the portion and indicating an operating mode of the portion; determine, at least in part based on monitoring the output pin of the register, whether to change the operating mode of the portion from the note mode to a cache mode having non-deterministic latency for satisfying a request from the host device, the cache mode being associated with data movement between the portion and the non-volatile memory; and operate the portion of the volatile memory in the cache mode, at least in part based on determining the change in the operating mode of the portion.

[0160] In some instances, the device may include performing a recall procedure during operation of the portion in the cache mode to store data from the portion in the non-volatile memory, and performing a fill procedure during operation of the portion in the cache mode to store data from the non-volatile memory in the portion.

[0161] In some instances, the device may include a component that prevents the recall and fill procedures from being performed during operation in the note mode.

[0162] In some instances of the device, the portion of the volatile memory that operates in the cache mode includes updating metadata during the operation of the portion in the cache mode to operate the portion in the cache mode and enable data movement between the portion and the non-volatile memory.

[0163] In some instances, the device may include receiving from the host device a signal to change the state of the output pin from a second state associated with the note mode to a first state associated with the cache mode, wherein the determination may be based at least in part on the change of the state of the output pin from the second state to the first state.

[0164] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0165] When used to describe conditional actions or processes, the terms "if..., then...", "when...", "based on...", "at least in part based on...", and "in response to..." are interchangeable.

[0166] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0167] A protocol can define one or more communication procedures and one or more communication parameters supported for use by a device or component. For example, a protocol can define various operations, timing and frequency for those operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the communication type of reserved pins, the size of data processed at various components of an interface, the data rate supported by various components of an interface, or the bandwidth supported by various components of an interface, and other parameters and metrics, or any combination thereof. The use of shared protocols enables interaction between devices because each device can operate in a way that is expected, recognized, and understood by another device. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols can be incompatible.

[0168] To illustrate, two devices supporting different protocols can be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols can be incompatible because the protocols define different transmission procedures to respond to a single command (e.g., the burst length or number of bytes allowed in response to the command can be different). Simply translating a command into an action should not be interpreted as using two different protocols. In fact, if the corresponding procedures or parameters defined by the two protocols change, then the protocols can be considered different. For example, if a device supports different addressing schemes or different transmission procedures to respond to commands, then the device can be said to support two different protocols.

[0169] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, based on or in response to the operation of a device containing the connected components, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0170] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0171] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0172] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0173] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0174] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0175] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0176] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0177] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0178] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that different parts of the functionality are implemented in different physical locations. And, as used herein (included in the claims), the word "or" used in a list of items (e.g., a list of items ending with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0179] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0180] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method executed by a memory device, comprising: A portion of volatile memory is operated in a cache mode with nondeterministic latency for satisfying requests from a host device, the cache mode being associated with data movement between the portion and nonvolatile memory; Monitor the output pins of registers in the memory device, the output pins being associated with the portion and indicating the operating mode of the portion; Based at least in part on monitoring the output pin of the register and on the latency requirements, expected access frequency, or both of a set of data to be stored in the portion of the volatile memory, it is determined whether to change the operating mode of the portion from the cache mode to a note mode with deterministic latency for satisfying the request of the host device, the note mode being used to operate the portion independently of the non-volatile memory. as well as The portion of the volatile memory is operated in the note mode, at least in part, based on determining the change in the operating mode of the portion.

2. The method of claim 1, wherein operating the portion of the volatile memory in the cache mode comprises: Execute the recovery procedure to store the data from the portion in the non-volatile memory; as well as A filling procedure is performed to store data from the non-volatile memory in the portion.

3. The method of claim 2, wherein operating the portion of the volatile memory in the note mode comprises: Avoid executing the recovery and fill procedures.

4. The method of claim 1, wherein operating the portion of the volatile memory in the cache mode comprises: Update metadata to operate the portion in the cache mode and enable the data movement between the portion and the non-volatile memory.

5. The method of claim 1, further comprising: The host device receives a signal that changes the state of the output pin from a first state associated with the cache mode to a second state associated with the note mode, wherein the determination is at least in part based on the change of the state of the output pin from the first state to the second state.

6. The method of claim 1, further comprising: At least in part, based on determining to change the operating mode and before operating the portion in the note mode, the set of data from the portion of the volatile memory is stored in a portion of the non-volatile memory; as well as After storing the set of data and based at least in part on determining that the portion of the volatile memory was operating in the note mode, the portion of the non-volatile memory was powered off.

7. The method of claim 1, further comprising: After operating the portion in the note mode, determine whether to operate the portion of the volatile memory in the cache mode; as well as After determining that the portion is to operate in the cache mode, the portion is stored in the portion at least in part based on a request from the host device for the set of data from the non-volatile memory and during the operation of the portion in the cache mode.

8. The method of claim 1, further comprising: Determine whether the state of the second output pin of the register has changed from a first state associated with the cache mode to a second state associated with the note mode; as well as Based at least in part on determining that the state of the second output pin has changed from the first state to the second state, the operating mode of the second part associated with the second output pin is changed from the cache mode to the note mode.

9. The method of claim 1, further comprising: Determine whether the state of the second output pin of the register has changed from a second state associated with the note mode to a first state associated with the cache mode; as well as Based at least in part on determining that the state of the second output pin has changed from the second state to the first state, the operating mode of the second part associated with the second output pin is changed from the note mode to the cache mode.

10. The method of claim 1, wherein the portion comprises rows from a plurality of groups of the volatile memory.

11. A memory device comprising: Non-volatile memory; Volatile memory; as well as An interface controller, coupled to both the non-volatile memory and the volatile memory, is configured to enable the memory device to: A portion of the volatile memory is operated in a cache mode with nondeterministic latency for satisfying requests from a host device, the cache mode being associated with data movement between the portion and the nonvolatile memory; Monitor the output pins of registers in the memory device, the output pins being associated with the portion and indicating the operating mode of the portion; Based at least in part on monitoring the output pin of the register and on the latency requirements, expected access frequency, or both of a set of data to be stored in the portion of the volatile memory, it is determined whether to change the operating mode of the portion from the cache mode to a note mode with deterministic latency for satisfying the request of the host device, the note mode being used to operate the portion independently of the non-volatile memory. as well as The portion of the volatile memory is operated in the note mode, at least in part, based on determining the change in the operating mode of the portion.

12. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: During operation of the portion in the cache mode, a recovery procedure is executed to store data from the portion in the non-volatile memory; and During the operation of the portion in the cache mode, a filling procedure is performed to store data from the non-volatile memory in the portion.

13. The memory device of claim 12, wherein the interface controller is further configured to enable the memory device to: During operation in the note mode, the recall and fill procedures are avoided.

14. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: The metadata is updated during the operation of the portion in the cache mode to operate the portion in the cache mode and enable the data movement between the portion and the non-volatile memory.

15. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: The host device receives a signal that changes the state of the output pin from a first state associated with the cache mode to a second state associated with the note mode, wherein the determination is at least in part based on the change of the state of the output pin from the first state to the second state.

16. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: At least in part, based on determining to change the operating mode and before operating the portion in the note mode, the set of data from the portion of the volatile memory is stored in a portion of the non-volatile memory; and After storing the set of data and based at least in part on determining that the portion of the volatile memory was operating in the note mode, the portion of the non-volatile memory was powered off.

17. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: After operating the portion in the note mode, determine whether to operate the portion of the volatile memory in the cache mode; and After determining that the portion is to operate in the cache mode, the portion is stored in the portion at least in part based on a request from the host device for a set of data from the non-volatile memory and during the operation of the portion in the cache mode.

18. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: Determine whether the state of the second output pin of the register has changed from a first state associated with the cache mode to a second state associated with the note mode; and Based at least in part on determining that the state of the second output pin has changed from the first state to the second state, the operating mode of the second part associated with the second output pin is changed from the cache mode to the note mode.

19. The memory device of claim 11, wherein the interface controller is further configured to enable the memory device to: Determine whether the state of the second output pin of the register has changed from a second state associated with the note mode to a first state associated with the cache mode; and Based at least in part on determining that the state of the second output pin has changed from the second state to the first state, the operating mode of the second part associated with the second output pin is changed from the note mode to the cache mode.

20. The memory device of claim 11, wherein the portion comprises rows from a plurality of groups of the volatile memory.

21. A memory device comprising: Non-volatile memory; Volatile memory; as well as An interface controller, coupled to both the non-volatile memory and the volatile memory, is configured to enable the memory device to: A portion of the volatile memory is operated in a note mode with deterministic latency for satisfying requests from the host device, the note mode being used to operate the portion independently of the non-volatile memory; Monitor the output pins of registers in the memory device, the output pins being associated with the portion and indicating the operating mode of the portion; The determination of whether to change the operating mode of the portion from the note mode to a cache mode with nondeterministic latency for satisfying the host device’s request is based at least in part on monitoring the output pin of the register and on the latency requirements, expected access frequency, or both of a set of data to be stored in the portion of the volatile memory. as well as The portion of the volatile memory is operated in the cache mode, at least in part, based on determining the change in the operating mode of the portion.

22. The memory device of claim 21, wherein the interface controller is further configured to enable the memory device to: During operation of the portion in the cache mode, a recovery procedure is executed to store data from the portion in the non-volatile memory; and During the operation of the portion in the cache mode, a filling procedure is performed to store data from the non-volatile memory in the portion.

23. The memory device of claim 22, wherein the interface controller is further configured to enable the memory device to: During operation in the note mode, the recall and fill procedures are avoided.

24. The memory device of claim 21, wherein the interface controller is further configured to enable the memory device to: The metadata is updated during the operation of the portion in the cache mode to operate the portion in the cache mode and enable the data movement between the portion and the non-volatile memory.

25. The memory device of claim 21, wherein the interface controller is further configured to enable the memory device to: The host device receives a signal that changes the state of the output pin from a second state associated with the note mode to a first state associated with the cache mode, wherein the determination is at least in part based on the change of the state of the output pin from the second state to the first state.

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