Discrete memristor analog circuit and its design method

Abstract

The present invention discloses a discrete memristor analog circuit and a design method thereof, wherein a first inverting adder is used to implement iterative accumulation of input charge to obtain a first accumulated value; a first inverter is used to restore the first accumulated value to a positive value to obtain the internal charge q of the memristor. n A sampling and holding circuit, the input end of which is connected to the output end of the first inverter, and the output end of which is connected to the negative input end of the first inverting adder; a second inverter, the negative input end and the output end of which are both connected to the sampling and holding circuit, inputting a pulse voltage of opposite phase to the sampling and holding circuit; a second inverting adder, used to implement the following operation: V(t n )=(α‑βq n )i(t n ), where α and β are memristor parameters; a voltage follower, the positive input terminal is connected to the input power supply; a multiplier, the input terminal is connected to the output terminal of the second inverting adder and the output terminal of the voltage follower. The present invention uses an analog circuit to realize a discrete memristor constructed in combination with a differential operator, which can further expand the application research of discrete memristor models.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a discrete memristor analog circuit and a design method thereof. Background Art

[0002] In 1971, Professor Cai Shaotang proposed the concept of memristor based on the circuit completeness theory. In 2008, HP Labs used TiO2 and metal platinum to realize the world's first nanoscale memristor physical device for the first time. Since then, a wave of research on memristors has been set off, making memristors have in-depth application research in image processing, memory, neural networks, neural dynamics and other fields. However, the memristors mentioned above that have been widely used in research are continuous memristors. Although the concept of discrete memristors was proposed in the field of materials in 2013, it has not been explained on a mathematical basis and implemented in the field of engineering applications. In 2018, Karthikeyan et al. reported the chaotic mapping of fractional-order discrete memristors, but the main idea is to obtain a discrete iterative model by discrete continuous memristors, rather than directly proposing a discrete memristor mathematical model. Therefore, the model they proposed can still only be used in continuous systems or analog systems. If memristors are to be introduced in discrete systems or other digital fields for further application research, it is necessary to design discrete memristors and carry out discrete memristor simulator design research.

[0003] The definition of a continuous memristor is:

[0004]

[0005] Where V(t) is the input voltage of the continuous memristor, i(t) is the input current, and k is a constant. The expression of the internal charge of the continuous memristor is defined as:

[0006]

[0007] Let the initial charge value be:

[0008]

[0009] Substituting the initial value of the charge, the final expression of the internal charge is:

[0010]

[0011] When implementing a continuous memristor with an analog circuit, the key lies in the realization of the second equation in equation (1). Usually, an integrating circuit composed of resistors, capacitors and operational amplifiers is used, and the input of the initial value of the charge is controlled by setting the initial value of the capacitor C.

[0012] According to the operational amplifier virtual short and virtual break laws and Kirchhoff's laws, the relationship between the output charge q(t) and the input current i(t) can be obtained from the integration circuit:

[0013]

[0014] make:

[0015]

[0016] That is, we get:

[0017]

[0018] That is, the value of the constant k can be changed by adjusting the values ​​of the resistor R and the capacitor C.

[0019] The analog circuit implementations of continuous memristors and discrete memristors are similar. Both mainly use operational amplifiers to implement operations such as addition and subtraction. However, continuous memristors use integral circuits to implement differential operators, while discrete memristors use sample-and-hold circuits to implement differential operators.

[0020] For the equivalent circuit implementation of continuous memristor, discrete memristor mainly combines operational amplifier, digital analog hybrid circuit and active amplifier to build its analog circuit, and the circuit mainly uses integration circuit or current transfer meter to realize the relevant characteristics of memristor. At present, the equivalent circuit implementation of discrete memristor is mainly realized by digital circuits such as FPGA and DSP, but it has limited precision effect. Compared with the capacitor and other devices that construct continuous memristor, which generate continuous signals, the analog circuit implementation of discrete memristor needs to find suitable components that can output discrete signals or achieve delay effect to discrete analog circuit corresponding to analog circuit.

[0021] Discrete memristors are more conducive to the application of memristors in digital circuits and discrete fields than continuous memristors. However, discrete memristors are still in the early stages of research and have a large research space. Summary of the invention

[0022] The technical problem to be solved by the present invention is to provide a discrete memristor analog circuit and a design method thereof in view of the deficiencies in the prior art, so as to solve the problem of limited accuracy of the existing discrete memristor equivalent circuit.

[0023] In order to solve the above technical problems, the technical solution adopted by the present invention is: a discrete memristor analog circuit, comprising:

[0024] A first inverting adder, used for implementing iterative accumulation of input charges to obtain a first accumulated value;

[0025] The first inverter is used to restore the first accumulated value to a positive value, and obtain the internal charge q of the memristorn ;

[0026] A sampling and holding circuit, wherein the input end is connected to the output end of the first inverter, and the output end is connected to the negative input end of the first inverting adder;

[0027] A second inverter, wherein both a negative input terminal and an output terminal are connected to the sampling and holding circuit, and inputs a pulse voltage of opposite phase to the sampling and holding circuit;

[0028] The second inverting adder is used to implement the following operation: V(t n )=(α-βq n )i(t n ), where α and β are memristor parameters, i(t n ) is the input current of the discrete memristor, v(t n ) is the final discrete memristor output voltage;

[0029] Voltage follower, the positive input terminal is connected to the input power supply;

[0030] The multiplier has an input end connected to the output end of the second inverting adder and the output end of the voltage follower.

[0031] The existing digital circuits based on digital processors have limited precision. For example, chaotic circuits may cause chaotic degradation when designed. However, the analog circuits of the present invention are not based on processors with limited precision, so they can produce chaos in the true sense. This solves the problem of limited precision of the existing discrete memristor equivalent circuits, and is of great significance to the interpretation of the physical meaning of discrete memristors and their engineering applications. At the same time, the present invention is based on analog circuits, which can provide an experimental basis for the subsequent implementation of discrete memristor integrated circuits and facilitate the application of discrete memristors in large-scale integrated circuits.

[0032] The first inverting adder comprises:

[0033] a first operational amplifier;

[0034] The positive input terminal of the first operational amplifier is grounded, the negative input terminal is connected to the first resistor, the second resistor and one end of the third resistor, and the input terminal of the first resistor is connected to the input power supply;

[0035] The other end of the second resistor is connected to the output end of the sampling and holding circuit;

[0036] The other end of the third resistor is connected to the output end of the first operational amplifier.

[0037] The first inverter includes a second operational amplifier, a negative input terminal of the second operational amplifier is connected to a fourth resistor and one end of a fifth resistor; the other end of the fourth resistor is connected to an output terminal of the first operational amplifier; the other end of the fifth resistor is connected to the output terminal of the second operational amplifier; and the positive input terminal of the second operational amplifier is grounded.

[0038] The sampling and holding circuit includes two sampling and holding devices; the input end of the first sampling and holding device is connected to the output end of the second operational amplifier, the output end of the first sampling and holding device is connected to the input end of the second sampling and holding device; and the output end of the second sampling and holding device is connected to the second resistor.

[0039] The first sample holder is in a sampling state. When the signal is sampled and discretized by the first sample holder, the second sample holder is controlled by a pulse signal opposite to the first sample holder and is in a holding state, so that the signal value after sampling maintains the existing value until the next sampling pulse signal, thereby realizing the delay of the original signal.

[0040] The calculation formula of the internal charge of the discrete memristor is derived by using forward difference, and the final expression is an accumulative iterative formula between the charge and the input current, which realizes the calculation of the internal charge of the discrete memristor by using addition operation. In the circuit, adders (first inverting adder and second inverting adder) can be used to express the relationship between the charge and the input current. The present invention uses the first inverting adder to realize the iterative accumulation process, and then restores it to a positive value through the first inverter to realize the iterative process.

[0041] The second inverter includes a third operational amplifier, the negative input terminal of the third operational amplifier is connected to the sixth resistor and one end of the seventh resistor; the other end of the sixth resistor is connected to the control end of the first sample and holder; the other end of the seventh resistor is connected to the output end of the third operational amplifier; and the output end of the third operational amplifier is connected to the control end of the second sample and holder.

[0042] The second inverting adder includes a fifth operational amplifier; the negative input terminal of the fifth operational amplifier is connected to the eighth resistor, the ninth resistor and one end of the tenth resistor; the other end of the eighth resistor is connected to the output end of the sampling and holding circuit; the other end of the ninth resistor is connected to the DC power supply; the other end of the tenth resistor is connected to the output end of the fifth operational amplifier. Since the DC input value of 0.1V is too small, in order to avoid a large error, a DC voltage of 1V is used, and then the input of α value 0.1V is realized through the proportional relationship between the resistors of the inverting adder.

[0043] As an inventive concept, the present invention also provides a memristor analog circuit design method, which uses the following memristor mathematical model to design the above-mentioned discrete memristor analog circuit of the present invention:

[0044]

[0045] Where n = 0, 1, 2, 3, ..., +∞; Δq(t n )=q(t n+1 )-q(t n ); M(q(t n ))=α-βq(t n );k=1;q(t n ) is t n The internal charge at the moment, the initial value of the internal charge is set to zero; the memristor is a HP memristor composed of metal and oxide, its main body width is set to D, and the doping layer width is set to W. When the current flows in the forward direction, the movement of oxygen vacancies causes the doping layer width W to become wider, and the resistance of the memristor becomes smaller. When W is infinitely close to D, the memristor has a minimum resistance R on When the current flows in the reverse direction, the movement of oxygen vacancies causes the width of the doped layer W to narrow, and the resistance of the memristor increases. When W is infinitely close to 0, the memristor has a maximum value R off , using μ v Represents the mobility of doped ions, and the memristor parameter α = R off , D is the width of the memristor body, W is the width of the memristor doping layer, R on is the minimum resistance of the memristor, μ ν Represents the mobility of dopant ions.

[0046] In the present invention, the value of α is 0.1, and the value of β is 0.01.

[0047] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention adopts two sample-and-hold devices controlled by opposite logic pulse signals to realize the discretization and delay of the signal, and finally realizes the accumulation and iterative operation of the internal variables of the discrete memristor, and realizes the discretization of the continuous signal and the delay of the signal at the same time, and there is no need to process the two processes separately, and compared with the digital circuit implementation, the use of analog circuits can break through the accuracy limitation; the present invention uses analog circuits to realize the discrete memristor constructed in combination with the differential operator, which can verify the physical meaning of the discrete memristor on the one hand, and further expand the application research of the discrete memristor model on the other hand; the present invention uses analog circuits to realize the discrete memristor, which is more conducive to the further application of discrete memristors in discrete chaotic systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a circuit diagram of a discrete memristor simulation according to an embodiment of the present invention;

[0049] Fig. 2(a), Fig. 2(b) and Fig. 2(c) are simulation results of the discrete memristor according to the embodiment of the present invention in combination with Psim, with the input sine wave amplitude being 1V, the frequencies being 20HZ, 25HZ and 30HZ respectively, the sampling frequency being 1KHZ and the sampling amplitude being 4V;

[0050] Fig. 3(a), Fig. 3(b) and Fig. 3(c) are respectively simulation results of the discrete memristor of the embodiment of the present invention in combination with Psim, with the input sine wave frequency being 25HZ, the amplitude being 0.9V, 1V and 1.1V respectively, the sampling frequency being 1KHZ, and the sampling amplitude being 4V;

[0051] FIG4(a), FIG4(b) and FIG4(c) are test result diagrams respectively showing verification of the discrete memristor of the embodiment of the present invention in combination with actual circuit experiments, with the input sine wave amplitude being 1V, the frequencies being 20HZ, 25HZ and 30HZ respectively, the sampling frequency being 1KHZ, and the sampling amplitude being 4V;

[0052] FIG5(a), FIG5(b) and FIG5(c) are test result diagrams respectively showing the discrete memristor of the embodiment of the present invention verified by combining actual circuit experiments, with the input sine wave frequency being 25 Hz, the amplitudes being 0.9 V, 1 V and 1.1 V respectively, the sampling frequency being 1 KHZ, and the sampling amplitude being 4 V; DETAILED DESCRIPTION

[0053] In the prior art, discrete memristors are mainly used in the field of materials or by discretizing continuous memristors, and cannot be directly applied to discrete systems. The present invention combines the forward difference operator to establish a mathematical model of discrete memristors, which can be directly applied to discrete systems or digital fields.

[0054] The mathematical model of discrete memristor proposed by combining forward difference operator is defined as:

[0055]

[0056] Where n = 0, 1, 2, 3, ... ∞, Δq(t n )=q(t n+1 )-q(t n ) is the forward difference.

[0057]

[0058] Adding both sides of the equal sign, the calculation formula for the memristor's "internal charge" is

[0059]

[0060] On this basis, the Hewlett-Packard (HP) memristor model expression is:

[0061] V(t n )=(α-βq n )i(t n ) (11)

[0062] Among them, α and β are memristor parameters, α=R off , q n is the internal charge of the memristor. Set the memristor parameter α to 0.1 and β to 0.01, that is, the expression is:

[0063] V(t n )=(0.1-0.01q n )i(t n ) (12)

[0064] Since it is a discrete system, the input of the initial charge value and the superposition of the charge in formula (8) cannot be directly implemented by discretization using an integral circuit, otherwise it still cannot be used in a discrete system. Therefore, an inverting adder is selected to implement the superposition, and a sample-and-hold device is used to discretize and delay the signal. For the initial value of the charge, a DC power supply can be used to input it in the inverting adder. The value of k in formula (8) is also implemented by the ratio between the input resistance and the feedback resistance of the inverting adder. In an embodiment of the present invention, k=1, and the initial value of the internal charge is set to zero. For two sample-and-hold devices controlled by opposite pulse signals, the q output of the inverting adder is n+1 Discretize and delay to get q n , and then input into the inverting adder for accumulation. The delay time is the time occupied by the low level in one cycle. Therefore, it is necessary to reasonably adjust the pulse signal input frequency to control the delay time.

[0065] According to the expression (12) of the HP discrete memristor, the analog circuit is implemented by combining analog devices. The designed analog circuit includes operational amplifier A1, operational amplifier A2, operational amplifier A3, operational amplifier A4, operational amplifier A5, sample and hold S_H_1, sample and hold S_H_2, multiplier M, peripheral resistors, and input DC source, sinusoidal voltage source and logic control signal. The operational amplifier A1 and resistors R1, R2, and R3 form an inverting adder to realize the charge q n The iterative accumulation process; operational amplifier A2 and resistors R4 and R5 realize inverters to restore the value after iteration to a positive value; operational amplifier A3 and resistors R6 and R7 form an inverting adder to invert the input pulse signal; operational amplifier A4 is a voltage follower used to isolate power devices and logic devices; operational amplifier A5 and resistors R8, R9, R10 It also constitutes an inverting adder, which not only realizes the expression of the memristor parameter value β but also realizes the addition operation in the HP discrete memristor expression (12); two sample-and-hold devices are used as key components, and the two sample-and-hold devices are input with pulse voltages of opposite phases through an inverter composed of A3 and its peripheral resistors, so that the sampling and holding states are exactly opposite, thereby realizing the discretization of the continuous signal and then delaying it in time; the multiplier M is used to realize the product of the current signal and the memristor value and output the final result; the DC source inputs a DC voltage of -1V, and then after the proportional conversion effect in the inverting adder composed of the operational amplifier A5 and its peripheral resistors, the expression of the initial memristor parameter α is realized; the sinusoidal signal source is used as the initial input to input the sinusoidal signal to verify the correctness of the designed memristor circuit.

[0066] At present, there is no analog circuit implementation for discrete memristors, but they can be numerically simulated in combination with Psim simulation software and implemented in combination with digital circuits using FPGA or DSP. However, numerical simulation does not have a real physical entity. As a device, discrete memristors need to be implemented with corresponding analog circuits to clearly explain their physical meaning. For the implementation of discrete memristors using digital circuits, the accuracy of digital circuits is limited and chaos in the true sense cannot be achieved, while analog circuits can achieve chaos in the true sense. Therefore, the implementation of discrete memristors using analog circuits is more conducive to the further application of discrete memristors in discrete chaotic systems. In addition, the present invention is different from the integral circuit in the continuous memristor analog circuit to realize the calculation of the internal charge of the memristor. Here, a sample-and-hold device is used to realize the discretization of continuous signals and the delay of signals, and the inverting adder composed of an operational amplifier and peripheral resistors is combined to finally realize the iteration of the internal charge.

[0067] For the current technology, we can use Psim simulation software to simulate the designed discrete memristor, keeping the input sine wave amplitude at 1V, the frequencies at 20HZ, 25HZ, and 30HZ respectively, the sampling frequency at 1KHZ, and the sampling amplitude at 4V. The simulation results are shown in Figure 2(a), Figure 2(b), and Figure 2(c); keeping the input sine wave frequency at 25HZ, the amplitudes at 0.9V, 1V, and 1.1V respectively, the sampling frequency at 1KHZ, and the sampling amplitude at 4V. The simulation results are shown in Figure 3(a), Figure 3(b), and Figure 3(c).

[0068] The physical test is built using a breadboard to test the relationship between the input current and the output voltage. The input sine wave amplitude is kept at 1V, the frequencies are 20HZ, 25HZ, and 30HZ, the sampling frequency is 1KHZ, and the sampling amplitude is 4V. The test results are shown in Figures 4(a), 4(b), and 4(c); the input sine wave frequency is kept at 25HZ, the amplitudes are 0.9V, 1V, and 1.1V, the sampling frequency is 1KHZ, and the sampling amplitude is 4V. The test results are shown in Figures 5(a), 5(b), and 5(c). It can be seen that the test results show an oblique 8-shaped hysteresis curve, and the hysteresis curve increases with the increase of the input signal amplitude, decreases with the increase of the input signal frequency, and finally degenerates into a linear device, which meets the definition of the memristor of the generalized memristor, and the experimental test results are basically consistent with the simulation results using Psim, which once again verifies the correctness of the discrete memristor analog circuit constructed by the present invention.

[0069] In the analog circuit of the embodiment of the present invention, one end of the resistor R1 is connected to the input sine wave, and the other end of the resistor R1 is connected to the negative input end of the operational amplifier A1; one end of the resistor R2 is connected to the output end of the two-stage sample and hold device, and the other end of the resistor R2 is connected to the negative input end of the operational amplifier A1; one end of the resistor R3 is connected to the output end of the operational amplifier A1, and the other end of the resistor R3 is connected to the negative input end of the operational amplifier A1; one end of the resistor R4 is connected to the negative input end of the operational amplifier A2, and the other end of the resistor R4 is connected to the output end of the operational amplifier A1; one end of the resistor R5 is connected to the output end of the operational amplifier A2, and the other end of the resistor R5 is connected to the negative input end of the operational amplifier A2; one end of the resistor R6 is connected to the negative input end of the operational amplifier A3, and the other end of the resistor R6 is connected to the logic control end of the sample and hold S_H_1. Input pulse signal Vc; one end of resistor R7 is connected to the negative input end of operational amplifier A3, and the other end of resistor R7 is connected to the output end of operational amplifier A3; the input end of sample holder S_H_1 is connected to the output end of operational amplifier A2, and the output end of sample holder S_H_2 is connected to resistor R2, and the two sample holders are cascaded, that is, the output end of sample holder S_H_1 is connected to the input end of sample holder S_H_2, and the two sample holders are respectively controlled by two opposite logic signals, Vc and Vc' obtained by inverter; one end of resistor R8 is connected to the output end of sample holder S_H_2, and the other end of resistor R8 is connected to the negative input end of operational amplifier A5; one end of resistor R9 is connected to the negative input end of operational amplifier A5; the other end of resistor R9 is connected to the input DC power supply; resistor R 10 One end is connected to the output of operational amplifier A5, and the resistor R 10The other end is connected to the negative input of operational amplifier A5; the output of operational amplifier A5 is connected to one input of the multiplier, and the input sinusoidal voltage signal is connected to the other input of the multiplier after passing through operational amplifier A4; the multiplier outputs the final result. Finally, an oscilloscope is used to detect the invented input signal V1 and output signal V2 to verify its correctness.

Claims

1. A discrete memristor analog circuit, characterized in that: include: A first inverting adder, used for implementing iterative accumulation of input charges to obtain a first accumulated value; The first inverter is used to restore the first accumulated value to a positive value, and obtain the internal charge q of the memristor n ; A sampling and holding circuit, wherein the input end is connected to the output end of the first inverter, and the output end is connected to the negative input end of the first inverting adder; A second inverter, wherein both a negative input terminal and an output terminal are connected to the sampling and holding circuit, and inputs a pulse voltage of opposite phase to the sampling and holding circuit; The second inverting adder is used to implement the following operation: V(t n )=(α-βq n )i(t n ), where α and β are memristor parameters, i(t n ) is the input current of the discrete memristor simulation circuit, v(t n ) is the output voltage of the discrete memristor analog circuit; Voltage follower, the positive input terminal is connected to the input power supply; The multiplier has an input end connected to the output end of the second inverting adder and the output end of the voltage follower.

2. The discrete memristor analog circuit according to claim 1, characterized in that: The first inverting adder comprises: a first operational amplifier; The positive input terminal of the first operational amplifier is grounded, the negative input terminal is connected to the first resistor, the second resistor and one end of the third resistor, and the input terminal of the first resistor is connected to the input power supply; The other end of the second resistor is connected to the output end of the sampling and holding circuit; The other end of the third resistor is connected to the output end of the first operational amplifier.

3. The discrete memristor analog circuit according to claim 2, characterized in that: The first inverter includes a second operational amplifier, a negative input terminal of the second operational amplifier is connected to a fourth resistor and one end of a fifth resistor; the other end of the fourth resistor is connected to an output terminal of the first operational amplifier; the other end of the fifth resistor is connected to the output terminal of the second operational amplifier; and the positive input terminal of the second operational amplifier is grounded.

4. The discrete memristor analog circuit according to claim 2 or 3, characterized in that: The sampling and holding circuit comprises two sampling and holding devices; the input end of the first sampling and holding device is connected to the output end of the second operational amplifier, the output end of the first sampling and holding device is connected to the input end of the second sampling and holding device; and the output end of the second sampling and holding device is connected to the second resistor.

5. The discrete memristor analog circuit according to claim 4, characterized in that: The second inverter includes a third operational amplifier, the negative input terminal of the third operational amplifier is connected to the sixth resistor and one end of the seventh resistor; the other end of the sixth resistor is connected to the control end of the first sample and holder; the other end of the seventh resistor is connected to the output end of the third operational amplifier; and the output end of the third operational amplifier is connected to the control end of the second sample and holder.

6. The discrete memristor analog circuit according to claim 5, characterized in that: The second inverting adder includes a fifth operational amplifier; the negative input terminal of the fifth operational amplifier is connected to the eighth resistor, the ninth resistor and one end of the tenth resistor; the other end of the eighth resistor is connected to the output terminal of the sampling and holding circuit; the other end of the ninth resistor is connected to a DC power supply; and the other end of the tenth resistor is connected to the output terminal of the fifth operational amplifier.

7. A memristor analog circuit design method, characterized in that: The discrete memristor simulation circuit according to any one of claims 1 to 6 is designed using the following memristor mathematical model: Where n = 0, 1, 2, 3, ..., +∞; Δq(t n )=q(t n+1 )-q(t n ); M(q(t n ))=α-βq(t n );k=1;q(t n ) is t n The internal charge at the moment, the initial value of the internal charge is set to zero; α = R off , D is the width of the memristor body, R off is the maximum resistance of the memristor, R on is the minimum resistance of the memristor, μ ν Represents the mobility of dopant ions.

8. The memristor analog circuit design method according to claim 7, characterized in that: The value of α is 0.1 and the value of β is 0.01.

Images