A voltage control method and apparatus for erasing 3D NAND memory

Abstract

This invention provides a voltage control method for erasing 3D NAND memory. When the bias voltage of the word line of a true memory cell is at the erase control voltage, the bias voltage of the well-doped region is raised to the erase working voltage and maintained. During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at a first preset voltage. Then, the word line of the pseudo memory cell is set to a floating state, wherein the first preset voltage is less than the first intermediate voltage. In this way, the voltage difference between the word line where the pseudo memory cell is located and the word line where the adjacent true memory cell is located is reduced, avoiding tunneling between the word line where the true memory cell is located and the word line where the pseudo memory cell is located, thereby avoiding threshold voltage drift of the pseudo memory cell, avoiding reduction of memory cell string current, and thus avoiding read errors of the true memory cell.

Description

[0001] This invention is a divisional application of the patent filed on November 29, 2019, with application number 201911203481.5, entitled "A Voltage Control Method and Apparatus for Erasing 3D NAND Memory". Technical Field

[0002] This disclosure relates to the field of integrated circuit design technology for memory, and in particular to a voltage control method and apparatus for erasing 3D NAND memory. Background Technology

[0003] NAND flash memory is a non-volatile storage product with low power consumption, light weight and high performance, and has been widely used in electronic products. In order to further improve storage capacity and reduce the storage cost per bit, 3D NAND memory has been proposed.

[0004] In 3D NAND flash memory, a memory array is formed by strings of memory cells, creating memory cells in a three-dimensional direction. Each string contains true memory cells used for storage and pseudo-memory cells not actually used for storage. During an erase operation, the word line containing the pseudo-memory cell is in a floating state. However, during the erase operation, the voltage of the word line containing the pseudo-memory cell is coupled very high by the voltage of the well-doped region, causing the threshold voltage of the pseudo-memory cell to drift. As the number of erase cycles increases, the threshold voltage of the pseudo-memory cell continues to drift, leading to a decrease in the current of the memory cell string and consequently, read errors in the true memory cells. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a voltage control method and apparatus for erasing 3D NAND memory, thereby reducing read errors in true memory cells.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A voltage control method for erasing a 3D NAND memory, the memory comprising a memory array composed of memory cell strings, each memory cell string comprising a bottom-level select device, a NAND memory device, and a top-level select device connected in series from bottom to top, the NAND memory device comprising a true memory cell and a pseudo memory cell, the control terminal of the memory device in the same layer being connected to a word line; the memory array is formed on a substrate, the bottom-level select device is formed on a common source region of the array, the common source region of the array being surrounded by a well-doped region having an opposite doping type;

[0008] The voltage control method during erasure includes:

[0009] When the bias voltage of the word line of the true memory cell is at the erase control voltage, the bias voltage of the well doped region is raised to the erase working voltage and maintained at the erase working voltage; while the bias voltage of the well doped region rises to the first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at the first preset voltage, which is less than the first intermediate voltage, and then the word line of the pseudo memory cell is set to a floating state.

[0010] Optionally, the voltage control method during erasure further includes:

[0011] During the period when the bias voltage of the well-doped region rises to the second intermediate voltage, the bias voltage of the word line of the top-layer select device is maintained at a second preset voltage, which is less than the second intermediate voltage, and then the bias voltage of the word line of the top-layer select device is set to a floating state; and / or, during the period when the bias voltage of the well-doped region rises to the third intermediate voltage, the bias voltage of the word line of the bottom-layer select device is maintained at a third preset voltage, which is less than the third intermediate voltage, and then the bias voltage of the word line of the bottom-layer select device is set to a floating state.

[0012] Optionally, the voltage values ​​of the first preset voltage, the second preset voltage, and the third preset voltage are greater than 0 volts and less than the erasure working voltage of the well doped region.

[0013] Optionally, the bias voltage of the well-doped region is increased to the erase operating voltage, including increasing the bias voltage of the well-doped region to the erase operating voltage in a stepwise manner.

[0014] Optionally, the bias voltage and floating state control methods for the well-doped region include:

[0015] An incremental voltage is generated based on a changing voltage control signal, and the incremental voltage is converted into a bias voltage for the well-doped region.

[0016] When the changing voltage control signal is a preset value, a floating control signal is generated, which is used to switch the floating state.

[0017] Optionally, the bias voltage and floating state control methods for the well-doped region include:

[0018] An incremental voltage is generated based on a changing voltage control signal, and this incremental voltage is converted into a bias voltage for the well-doped region.

[0019] The incremental voltage or the bias voltage of the well doped region is compared with a preset voltage. When the voltage is greater than the preset voltage, a floating control signal is output. The floating control signal is used to switch the floating state.

[0020] A voltage control device for erasing a 3D NAND memory, the memory comprising a memory array composed of memory cell strings, each memory cell string comprising a bottom-level select device, a NAND memory device, and a top-level select device connected in series from bottom to top, the NAND memory device comprising a true memory cell and a pseudo memory cell, the control terminal of the memory device on the same layer being connected to a word line; the memory array is formed on a substrate, the bottom-level select device is formed on a common source region of the array, the common source region of the array being surrounded by a well-doped region having an opposite doping type;

[0021] The voltage control device includes:

[0022] A well-doped region bias voltage control unit is used to raise the bias voltage of the well-doped region to the erase working voltage and maintain the erase working voltage when the bias voltage of the word line of the true memory cell is at the erase control voltage.

[0023] A floating state control unit is configured to maintain the bias voltage of the word line of the pseudo memory cell at a first preset voltage, which is less than the first intermediate voltage, during the period when the bias voltage of the well doped region rises to a first intermediate voltage, and then set the word line of the pseudo memory cell to a floating state.

[0024] Optionally, the floating state control unit is further configured to maintain the bias voltage of the word line of the top-layer select device at a second preset voltage, which is less than the second intermediate voltage, during the period when the bias voltage of the well-doped region rises to the second intermediate voltage, and then set the bias voltage of the word line of the top-layer select device to a floating state; and / or,

[0025] During the period when the bias voltage of the well-doped region rises to the third intermediate voltage, the bias voltage of the word line of the bottom-layer select device is maintained at a third preset voltage, which is less than the third intermediate voltage, and then the bias voltage of the word line of the bottom-layer select device is set to a floating state.

[0026] Optionally, the voltage values ​​of the first preset voltage, the second preset voltage, and the third preset voltage are greater than 0 volts and less than the erasure working voltage of the well doped region.

[0027] Optionally, in the well-doped region bias voltage control unit, raising the bias voltage of the well-doped region to the erase working voltage includes: raising the bias voltage of the well-doped region to the erase working voltage in a step-by-step manner.

[0028] Optionally, the well-doped region bias voltage control unit includes:

[0029] A control signal generation unit is used to generate a changing voltage control signal, and when the changing voltage control signal is a preset value, to generate a floating control signal, wherein the floating control signal is a switching signal for the floating state of the floating state control unit.

[0030] A voltage generation unit is used to generate an increasing voltage based on a changing voltage control signal;

[0031] A voltage conversion unit is used to convert the increasing voltage into a bias voltage for the well-doped region.

[0032] Optionally, the well-doped region bias voltage control unit includes:

[0033] A control signal generation unit is used to generate varying voltage control signals;

[0034] A voltage generation unit is used to generate an increasing voltage based on a changing voltage control signal;

[0035] A voltage conversion unit is used to convert the increasing voltage into a bias voltage for the well-doped region;

[0036] The comparator compares the incrementing voltage or the bias voltage of the well-doped region with a preset voltage. When the voltage is greater than the preset voltage, it outputs a floating control signal, which is a switching signal for the floating state of the floating state control unit.

[0037] A 3D NAND memory, the memory comprising:

[0038] A memory array consisting of strings of memory cells, each string of memory cells including a bottom-level select device, a NAND memory device and a top-level select device connected in series from bottom to top. The NAND memory device includes a true memory cell and a pseudo memory cell. The control terminals of the memory devices in the same layer are connected to word lines. The memory array is formed on a substrate. The bottom-level select device is formed on the array common source region. The array common source region is surrounded by a well-doped region with the opposite doping type.

[0039] Voltage control device as described in any of the above.

[0040] The voltage control method for erasing 3D NAND memory provided in this embodiment of the invention raises the bias voltage of the well-doped region to the erasure working voltage and maintains the erasure working voltage when the word line of the true memory cell is at the erasure control voltage. During the period when the bias voltage of the well-doped region rises to the first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at a first preset voltage, which is less than the first intermediate voltage. Then, the word line of the pseudo memory cell is set to a floating state. In this way, during the period when the bias voltage of the well-doped region rises to the first intermediate voltage, the bias voltage of the memory cell is maintained at the first preset voltage, which is less than the first intermediate voltage. During the coupling process, the voltage of the word line of the pseudo memory cell and the bias voltage of the well-doped region maintain a certain voltage difference. When the bias voltage of the well-doped region rises to the first intermediate voltage, the word line of the pseudo memory cell is set to a floating state. The voltage of the word line of the pseudo memory cell will not be coupled to a very high value by the voltage of the well-doped region, thereby reducing the voltage difference between the word line where the pseudo memory cell is located and the word line where the adjacent real memory cell is located. This avoids FN tunneling between the word line where the real memory cell is located and the word line where the pseudo memory cell is located, thereby avoiding threshold voltage drift of the pseudo memory cell, avoiding reduction of memory cell serial current, and thus avoiding read errors of the real memory cell. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A schematic diagram of the structure of a storage array of a 3D NAND memory according to an embodiment of the present invention is shown;

[0043] Figure 2-5 A schematic diagram of the voltage of the storage array during erasure of a 3D NAND memory according to an embodiment of the present invention is shown;

[0044] Figure 6 A schematic diagram showing the voltage rise in the well-doped region during erasure of a 3D NAND memory according to an embodiment of the present invention is shown.

[0045] Figure 7-10 A schematic diagram of the voltage control device for erasing a 3D NAND memory according to an embodiment of the present invention is shown. Detailed Implementation

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0048] As described in the background section, in 3D NAND memory, memory arrays are formed by strings of memory cells, thereby creating memory cells in a three-dimensional direction. Each string of memory cells includes memory cells that are not actually used for storage, but these are formed together with the memory cells used for storage and have essentially the same structure. For ease of description, in this application, NAND memory devices not actually used for storage are referred to as pseudo-memory cells, and NAND memory devices used for storage are referred to as true memory cells. Typically, pseudo-memory cells are positioned between the top-level select device and the true memory cells in the 3D NAND memory device, as well as between the bottom-level select device and the true memory cells, effectively avoiding interference from the top-level and bottom-level select devices to the memory cells during erase operations.

[0049] Currently, during the erase operation, the word line containing the true memory cell is set to 0-1 volt, while the word line containing the dummy memory cell is in a floating state. The voltage of the word line containing the dummy memory cell is coupled very high by the voltage of the well-doped region. This results in a significant voltage difference between the word line containing the dummy memory cell and the word line containing the adjacent true memory cell, causing FN tunneling (Fowler-Nordheim tunneling) between the two word lines, leading to a drift in the threshold voltage of the dummy memory cell. As the number of erase cycles increases, the threshold voltage of the dummy memory cell continues to drift, causing a decrease in the memory cell string current, which in turn leads to read errors in the true memory cell.

[0050] Therefore, this application proposes a voltage control method during the erasure of a 3D NAND memory. When the bias voltage of the word line of the true memory cell is at the erase control voltage, the bias voltage of the well-doped region is raised to the erase working voltage and maintained. During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, the bias voltage of the word line of the pseudo memory cell is maintained at a first preset voltage, which is less than the first intermediate voltage. Then, the word line of the pseudo memory cell is set to a floating state. Thus, during the period when the bias voltage of the well-doped region rises to the first intermediate voltage, the word line of the pseudo memory cell is maintained at the first preset voltage. Since the first preset voltage is less than the first intermediate voltage, in... During the coupling process, the voltage of the word line of the pseudo memory cell and the voltage of the well doped region will maintain a certain voltage difference. Moreover, when the bias voltage of the well doped region rises to the first intermediate voltage, the word line of the pseudo memory cell is set to a floating state. The voltage of the word line of the pseudo memory cell will not be coupled to a very high value by the voltage of the well doped region, thereby reducing the voltage difference between the word line where the pseudo memory cell is located and the word line where the adjacent real memory cell is located. This avoids FN tunneling between the word line where the real memory cell is located and the word line where the pseudo memory cell is located, thereby avoiding threshold voltage drift of the pseudo memory cell, avoiding reduction of memory cell serial current, and thus avoiding read errors of the real memory cell.

[0051] To facilitate understanding of the technical solution and effects of this application, the storage array of the 3D NAND memory will be described first.

[0052] refer to Figure 1 As shown, in a 3D NAND memory, the memory includes a memory array composed of memory cell strings. Each memory cell string includes a bottom select gate (BSG), a NAND memory device, and a top select gate (TSG) connected in series from bottom to top. The NAND memory device includes true memory cells and pseudo memory cells. The control terminals of memory devices in the same layer are connected to word lines (WL). For ease of description and understanding, in this application, word lines connecting true memory cells in the same layer are denoted as word lines WLi (i from 1 to n), and word lines connecting pseudo memory cells in the same layer are denoted as word lines DMY. In addition, the direction of the row in the array is the word line direction, and the direction of the column in the array is the bit line direction. The memory array is formed on a substrate, and the bottom select gate (BSG) of the memory cell string is formed on the array common source region (ACS). The array common source region (ACS) is surrounded by a well doped region (Well) with the opposite type. The well doped region (Well) is formed in the substrate.

[0053] In practical applications, in 3D NAND memory, the storage cells in each row of each layer are connected to the same word line (WL), and the storage cells in each column are connected to the same bit line (BL). Each word line can correspond to a page, multiple pages form a block, and further, multiple blocks can form a plane.

[0054] This application proposes a voltage control method for erasing 3D NAND memory, wherein the bias voltage of the word line WL of the true memory cell is at the erase control voltage V. c At this time, the bias voltage of the well-doped region is increased to the erase working voltage V. ers And maintain the erase working voltage V ers Furthermore, during the period when the bias voltage of the well doped region rises to the first intermediate voltage V1, the bias voltage of the word line DMY of the pseudo memory cell is maintained at the first preset voltage V. 10 The first preset voltage V 10 The voltage is less than the first intermediate voltage V1. Then, the word line DMY of the pseudo memory cell is set to a floating state, referencing... Figure 2 As shown.

[0055] Erase control voltage V c To erase data stored in a true memory cell, the voltage required for the word line WL connected to the true memory cell is such that the bias voltage of the word line WL of the true memory cell is at the erase control voltage V. c At this time, data erasure operations can be performed. Erasure operating voltage V ers The operating voltage required for the well-doped region during the erasure operation.

[0056] In this embodiment of the application, during the erase operation, the voltage required by the bottom select device BSG, the true memory cell, the pseudo memory cell, and the top select device TSG in the memory array can be controlled by the driving circuit. The driving circuit can include each driving circuit corresponding to the bottom select device BSG, the true memory cell, the pseudo memory cell, and the top select device TSG, so that the top select device TSG, the true memory cell, the pseudo memory cell, and the top selector TSG can respectively reach the voltage required for the erase operation.

[0057] It is understood that a memory includes a memory array and control circuitry coupled to and configured to control the memory array. To distinguish it from the controller of the memory system, the control circuitry can also be referred to as peripheral circuitry. Here, for 3D NAND memory, the driving circuitry for controlling the voltage is located in the peripheral circuitry of the memory.

[0058] Peripheral circuitry can be coupled to the memory array via bit lines, word lines, source lines, source select lines, and drain select lines. The peripheral circuitry can include any suitable analog, digital, and mixed-signal circuitry to perform logic operations on the memory array by applying or sensing voltage and / or current signals to each target memory cell via the bit lines, word lines, source lines, source select lines, and drain select lines. For example, the peripheral circuitry can include voltage generation circuitry, multiple driver circuits, driver lines, and sense lines.

[0059] In this embodiment, during the erase operation, a bias voltage is supplied to the word line WL of the true memory cell, so that the bias voltage of the word line WL of the true memory cell is at the erase control voltage V. c The erase control voltage V c Normally, the voltage is low. During the erase operation, the word line WL of the true memory cell is at the required voltage, while the bias voltage of the well-doped region is raised to the erase operating voltage V. ers The bias voltage of the well-doped region rises to the erase operating voltage V. ers And maintain the operating voltage required for the erase operation in the well-doped region, referencing Figure 2 As shown.

[0060] In this embodiment, reference Figure 2 and Figure 3 As shown, the bias voltage of the well-doped region gradually rises to the erase working voltage V. ers To avoid damaging the well by directly applying a large voltage to the well-doped region, the first intermediate voltage V1 is the voltage at which the bias voltage of the well-doped region rises to the erase working voltage V. ers For ease of description, the starting time of the rise of the bias voltage in the well-doped region is denoted as T0, the time when it rises to the first intermediate voltage V1 is denoted as T1, and the time when it rises to the erase working voltage V... ers The time is denoted as T2. During the period from T0 to T1, when the bias voltage of the well doped region rises to the first intermediate voltage V1, the bias voltage of the word line DMY of the pseudo memory cell is maintained at the first preset voltage V. 10 The first preset voltage V 10 This is the voltage before the word line DMY of the pseudo memory cell is floated. When the Well doped region rises to the first intermediate voltage V1, i.e., at time T1, the word line DMY of the pseudo memory cell is set to a floating state. In this embodiment, the first preset voltage V... 10 The voltage value can be greater than 0 volts and less than the erase working voltage V of the well doped region. ers For example, it can be 0-1 volts.

[0061] In this embodiment, reference Figure 2 and Figure 4 As shown, the bias voltage of the word line of the top-layer select device (TSG) can also be maintained at a second preset voltage V during the period when the bias voltage of the well doped region rises to the second intermediate voltage V2. 20 The second preset voltage V 20 The voltage is less than the second intermediate voltage V2, and then the bias voltage of the word line of the top-level select device TSG is set to a floating state; Reference Figure 2 and Figure 5 As shown, and / or during the period when the bias voltage in the well-doped region rises to the third intermediate voltage V3, the bias voltage of the word line of the bottom-layer select device BSG is maintained at the third preset voltage V. 30 The third preset voltage V 30 The voltage is less than the third intermediate voltage V3, and then the bias voltage of the word line of the bottom-level select device BSG is set to floating.

[0062] In this embodiment, the second intermediate voltage V2 is the voltage at which the bias voltage of the well-doped region rises to the erase working voltage V. ers During the process, the magnitude of the second intermediate voltage V2 can be the same as or different from the magnitude of the first intermediate voltage V1. For ease of description, the moment when the bias voltage of the well-doped region rises to the second intermediate voltage V2 is denoted as T. 11 T 11 T1 can be the same as or different from T1. For example, when the second intermediate voltage V2 is the same as the first intermediate voltage V1, the time T at which the bias voltage of the well-doped region rises to the second intermediate voltage V2 is different. 11 The time T1 when the bias voltage of the well-doped region rises to the first intermediate voltage V1 is the same as the time T1 when the bias voltage of the well-doped region rises to the second intermediate voltage V2 when the second intermediate voltage V2 is different from the first intermediate voltage V1. 11 The time T1 is different from the time when the bias voltage of the well doped region rises to the first intermediate voltage V1.

[0063] refer to Figure 2 and Figure 4 As shown, the bias voltage of the well-doped region rises to the second intermediate voltage V2 during the period from T0 to T... 11 During this period, the bias voltage of the top-level select device TSG is maintained at the second preset voltage V. 20 The second preset voltage V 20 With the first preset voltage V 10 The magnitudes can be the same or different, and the second preset voltage V 20 It is the voltage before the top-level selection device TSG is floated, which rises to the first intermediate voltage V1 in the well-doped region, i.e., at T11 At a certain time, the bias voltage of the word line of the top-level select device TSG is set to a floating state. In this embodiment, the second preset voltage V 20 The voltage value can be greater than 0 volts and less than the erase working voltage V of the well doped region. ers For example, it can be 0-1 volts.

[0064] In this embodiment, the third intermediate voltage V3 is a voltage during the rise of the bias voltage of the well-doped region. The magnitude of the third intermediate voltage V3 can be the same as or different from the magnitudes of the first intermediate voltage V1 and the second intermediate voltage V2. For ease of description, the time when the bias voltage of the well-doped region rises to the third intermediate voltage V3 is denoted as T. 12 T 12 With T1, T 11 They can be the same or different. For example, when the third intermediate voltage V3 is the same as the first intermediate voltage V1, the time T at which the bias voltage of the well-doped region rises to the third intermediate voltage V3 is... 12 The time T1 when the bias voltage of the well-doped region rises to the first intermediate voltage V1 is the same as the time T1 when the third intermediate voltage V3 is different from the first intermediate voltage V1. 12 The time T1 is different from the time when the bias voltage of the well doped region rises to the first intermediate voltage V1.

[0065] refer to Figure 2 and Figure 5 As shown, the bias voltage of the well-doped region rises to the third intermediate voltage V3 during the period from T0 to T... 12 During this period, the bias voltage of the word line of the underlying select device BSG is maintained at the third preset voltage V. 30 The third preset voltage V 30 Less than the third intermediate voltage V3, the third preset voltage V 30 It can be used with the first preset voltage V 10 They can be the same or different; the third preset voltage V 30 It is the voltage before the bottom-level selection device BSG is floated, and it rises to the third intermediate voltage V3 in the well-doped region, i.e., at T. 12 At any given time, the bias voltage of the word line of the underlying select device BSG is set to a floating state. In this embodiment, the value of the third preset voltage V3 can be greater than 0 volts and less than the erase operating voltage V of the well-doped region. ers For example, it can be 0-1 volts.

[0066] In this embodiment, during the period when the bias voltage of the well-doped region rises to the first intermediate voltage V1, the bias voltage of the word line DMY of the pseudo memory cell is maintained at the first preset voltage V. 10 During the period when the bias voltage of the well-doped region rises to the second intermediate voltage V2, the bias voltage of the word line of the top-layer select device TSG is maintained at the second preset voltage V. 20 During the period when the bias voltage of the well-doped region rises to the third intermediate voltage V3, the bias voltage of the word line of the underlying select device BSG is maintained at the third preset voltage V. 30 The magnitudes of the first intermediate voltage V1, the second intermediate voltage V2, and the third intermediate voltage V3 can be selected according to actual needs, or they can be the same. The first preset voltage V 10 Second preset voltage V 20 and the third preset voltage V 30 The voltage values ​​can be selected to be the same or different depending on individual needs. When the bias voltage of the well-doped region rises to the first intermediate voltage V1, the bias voltage of the word line DMY of the pseudo-memory cell is set to a floating state. When the bias voltage of the well-doped region rises to the second intermediate voltage V2, the bias voltage of the top-layer select device TSG is set to a floating state. When the bias voltage of the well-doped region rises to the third intermediate voltage V3, the bias voltage of the bottom-layer select device BSG is set to a floating state. In a specific embodiment, the first preset voltage V... 10 Second preset voltage V 20 and the third preset voltage V 30 The voltage value can be greater than 0 volts and less than the erase working voltage V of the well doped region. ers For example, it can be 0-1 volts.

[0067] In this embodiment, reference Figure 6 As shown, the bias voltage of the well-doped region can be increased to the erase operating voltage V in a stepwise manner. ers Specifically, the supply voltage to the well-doped region can be increased in n stages, with the voltage increase in each stage being ΔV1, ΔV2, ΔV3…ΔV n-1 ΔV n The voltage rise amplitude in each stage can be the same or different, i.e., ΔV1, ΔV2, ΔV3…ΔV n-1 and ΔV n The magnitudes can be the same or different, and the time required for the voltage rise in each stage is ΔT1, ΔT2, ΔT3…ΔT. n-1 ΔT n The time required for the voltage to rise in each stage can be the same or different, i.e., ΔT1, ΔT2, ΔT3…ΔTn-1 and ΔT n The values ​​can be the same or different. The bias voltage of the well-doped region is increased in a stepwise manner, so that the bias voltage of the well-doped region exhibits a slow upward trend, ensuring that the voltage of the well-doped region gradually rises to the erase working voltage V. ers This is to avoid excessive supply voltage damaging the well-doped region.

[0068] In some embodiments, the control method for the bias voltage and floating state of the well-doped region can be as follows: generating an incrementing signal based on the changing voltage control signal and converting the incrementing signal into the bias voltage of the well-doped region; when the changing voltage control signal is a preset value, generating a floating control signal, which is used for switching the floating state.

[0069] Specifically, by changing the voltage control signal, an incrementing signal is generated with each change in the voltage control signal. This incrementing signal is then converted into the voltage of the well-doped region. This allows the bias voltage of the well-doped region to be changed by altering the voltage control signal. Multiple changes in the voltage control signal generate multiple incrementing signals, continuously increasing the bias voltage of the well-doped region. This achieves a step-by-step increase in the bias voltage of the well-doped region to the erase operating voltage V. ers When the changing voltage control signal is at a preset value, a floating control signal is generated. The control circuit controls the drive circuit according to the floating control signal to achieve the switching of the floating state.

[0070] In other embodiments, an incrementing signal is generated based on the changing voltage control signal, and the incrementing voltage is converted into a bias voltage of the well doped region. The incrementing voltage or the bias voltage of the well doped region is compared with a preset voltage. When it is greater than the preset voltage, a floating control signal is output. The floating control signal is used for the transition of the floating state.

[0071] Specifically, this can be achieved by raising the bias voltage of the well-doped region to the erase operating voltage V. ersDuring operation, the control circuit controls the driving circuit corresponding to the well-doped region (Well) to generate an increasing voltage based on the changing voltage control signal. This increasing voltage is converted into a bias voltage for the well-doped region, thereby continuously increasing the supply voltage to the well-doped region. This ensures that the well-doped region reaches the voltage required for the erasure operation. As the voltage continuously increases, the bias voltage of the well-doped region continuously increases. After increasing to a certain extent, the increasing voltage can be compared with a preset voltage, which is the voltage value corresponding to the floating state. When the increasing voltage is greater than the preset voltage, a floating control signal is output. The control circuit controls the switching of the floating state based on the floating control signal. Alternatively, the bias voltage of the well-doped region can be compared with the preset voltage. When the bias voltage of the well-doped region is greater than the preset voltage, a floating control signal is output, and the control circuit controls the switching of the floating state based on the floating control signal.

[0072] The voltage control method for erasing 3D NAND memory readers according to embodiments of this application has been described in detail above. This application also provides a voltage control device for erasing 3D NAND memory to implement the above method. The memory includes a memory array composed of memory cell strings. Each memory cell string includes a bottom selection device (BSG), a NAND memory device, and a top selection device (TSG) connected in series from bottom to top. The NAND memory device includes true memory cells and pseudo memory cells. The control terminals of memory devices in the same layer are connected to word lines. The memory array is formed on a substrate. The bottom selection device (BSG) is formed on the array common source region (ACS). The array common source region (ACS) is surrounded by a well doped region (Well) with the opposite doping type.

[0073] The voltage control device includes:

[0074] Well bias voltage control unit 200 is used to raise the bias voltage of the well doped region to the erase working voltage and maintain the erase working voltage when the bias voltage of the word line WL of the true memory cell is at the erase control voltage.

[0075] The floating state control unit 201 is used to maintain the bias voltage of the word line of the dummy memory cell at a first preset voltage during the period when the bias voltage of the well doped region rises to a first intermediate voltage, and then sets the word line of the dummy memory cell to a floating state, referring to... Figure 7 As shown.

[0076] Furthermore, the floating state control unit 201 is also configured to maintain the bias voltage of the word line of the top-layer select device (TSG) at a second preset voltage during the period when the bias voltage of the well-doped region rises to a second intermediate voltage, and then set the bias voltage of the word line of the top-layer select device (TSG) to a floating state; and / or,

[0077] During the period when the bias voltage of the well doped region rises to the third intermediate voltage, the bias voltage of the word line of the bottom layer select device (BSG) is maintained at the third preset voltage, and then the bias voltage of the word line of the bottom layer select device (BSG) is set to a floating state.

[0078] Furthermore, the voltage values ​​of the first preset voltage, the second preset voltage, and the third preset voltage are in the range of 0-1 volts.

[0079] Furthermore, in the well-doped region bias voltage control unit 200, raising the bias voltage of the well-doped region to the erase working voltage includes raising the bias voltage of the well-doped region to the erase working voltage in a step-by-step manner.

[0080] Furthermore, the well bias voltage control unit 200 for the well-doped region includes:

[0081] The control signal generation unit 210 is used to generate a changing voltage control signal, and when the changing voltage control signal is a preset value, it generates a floating control signal, wherein the floating control signal is a floating state switching signal of the floating state control unit.

[0082] The voltage generating unit 220 is used to generate an increasing voltage according to the changing voltage control signal;

[0083] Voltage conversion unit 230 is used to convert the increasing voltage into a bias voltage for the well-doped region, referenced. Figure 8 As shown.

[0084] Furthermore, the well-doped region bias voltage control unit 200 includes:

[0085] The control signal generation unit 210 is used to generate a changing voltage control signal;

[0086] The voltage generating unit 220 is used to generate an increasing voltage according to the changing voltage control signal;

[0087] Voltage conversion unit 230 is used to convert the increasing voltage into a bias voltage for the well-doped region;

[0088] Comparator 240 compares the incrementing voltage or the bias voltage of the well-doped region with a preset voltage. When the voltage is greater than the preset voltage, it outputs a floating control signal. This floating control signal is a switching signal for the floating state of the floating state control unit. Figure 9 and 10 As shown.

[0089] This application also provides a 3D NAND memory comprising:

[0090] A memory array consisting of strings of memory cells, each string of memory cells including a bottom select device (BSG), a NAND memory device, and a top select device (TSG) connected in series from bottom to top. The NAND memory device includes true memory cells and pseudo memory cells. The control terminals of memory devices in the same layer are connected to word lines. The memory array is formed on a substrate. The bottom select device (BSG) is formed on the array common source region (ACS). The array common source region (ACS) is surrounded by well-doped regions with opposite doping types.

[0091] Voltage control device as described in any of the above.

[0092] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0093] The above description is merely a preferred embodiment of the present invention. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A voltage control method for erasing 3D NAND memory, characterized in that, The memory includes a memory array composed of memory cell strings. Each memory cell string includes a bottom-level select device, a NAND memory device, and a top-level select device connected in series from bottom to top. The NAND memory device includes a true memory cell and a pseudo memory cell. The control terminal of the memory device in the same layer is connected to the word line. The memory array is formed on the substrate, the bottom selection device is formed on the array common source region, and the array common source region is surrounded by a well doped region; The voltage control method during erasure includes: When an erase control voltage is applied to the word line of the selected true memory cell, a drive voltage is applied to the well doped region to increase the bias voltage of the well doped region. During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, a first preset voltage is applied to the word line of the pseudo memory cell, and the word line of the pseudo memory cell is kept at the first preset voltage; wherein the first preset voltage is less than the first intermediate voltage; When the bias voltage of the well-doped region rises to the first intermediate voltage, the word line of the pseudo memory cell is set to a floating state. The driving voltage is applied to the well-doped region to raise the bias voltage of the well-doped region to the erase working voltage; wherein the first intermediate voltage is less than the erase working voltage; The voltage control method during erasure further includes: During the period when the bias voltage of the well-doped region rises to the second intermediate voltage, a second preset voltage is applied to the word line of the top-layer select device, and the word line of the top-layer select device is maintained at the second preset voltage; wherein the second preset voltage is less than the second intermediate voltage; When the bias voltage of the well-doped region is at the second intermediate voltage, the word line of the top-level select device is set to a floating state; And / or, During the period when the bias voltage of the well-doped region rises to the third intermediate voltage, a third preset voltage is applied to the word line of the bottom-layer select device, and the word line of the bottom-layer select device is maintained at the third preset voltage; wherein the third preset voltage is less than the third intermediate voltage; When the bias voltage of the well-doped region is at the third intermediate voltage, the word line of the bottom-layer select device is set to a floating state.

2. The voltage control method according to claim 1, characterized in that, The voltage values ​​of the first preset voltage, the second preset voltage, and the third preset voltage are greater than 0 volts and less than the erasure working voltage of the well doped region.

3. The voltage control method according to any one of claims 1-2, characterized in that, The step of applying the driving voltage to the well-doped region includes: applying the driving voltage to the well-doped region in a step-increasing manner.

4. The voltage control method according to claim 3, characterized in that, The bias voltage and floating state control methods for the well-doped region include: An incremental voltage is generated based on a changing voltage control signal, and the incremental voltage is converted into a bias voltage for the well-doped region. When the changing voltage control signal is a preset value, a floating control signal is generated, which is used to switch the floating state.

5. The voltage control method according to claim 3, characterized in that, The bias voltage and floating state control methods for the well-doped region include: An incremental voltage is generated based on a changing voltage control signal, and this incremental voltage is converted into a bias voltage for the well-doped region. The incremental voltage or the bias voltage of the well doped region is compared with the voltage corresponding to the floating state. When the voltage is greater than the voltage corresponding to the floating state, a floating control signal is output. The floating control signal is used to switch the floating state.

6. The voltage control method according to claim 1, characterized in that, The voltage control method during erasure also includes: After the bias voltage of the well-doped region is at the erase working voltage, the bias voltage of the well-doped region is maintained at the erase working voltage.

7. A 3D NAND memory, characterized in that, The memory includes: A memory array consisting of strings of memory cells, each string of memory cells including a bottom-level select device, a NAND memory device and a top-level select device connected in series from bottom to top, wherein the NAND memory device includes a true memory cell and a pseudo memory cell, and the control terminal of the memory device in the same layer is connected to the word line; the memory array is formed on a substrate, the bottom-level select device is formed on the array common source region, and the array common source region is surrounded by a well-doped region; A control circuit is configured to apply a drive voltage to a well-doped region when an erase control voltage is applied to the word line of a selected true memory cell, thereby increasing the bias voltage of the well-doped region; wherein the control circuit is located between the memory device and the substrate; During the period when the bias voltage of the well-doped region rises to a first intermediate voltage, a first preset voltage is applied to the word line of the pseudo memory cell, and the word line of the pseudo memory cell is kept at the first preset voltage; wherein the first preset voltage is less than the first intermediate voltage; When the bias voltage of the well-doped region rises to the first intermediate voltage, the word line of the pseudo memory cell is set to a floating state. The driving voltage is applied to the well-doped region to raise the bias voltage of the well-doped region to the erase working voltage. During the period when the bias voltage of the well-doped region rises to the second intermediate voltage, a second preset voltage is applied to the word line of the top-layer select device, and the word line of the top-layer select device is maintained at the second preset voltage; wherein the second preset voltage is less than the second intermediate voltage; When the bias voltage of the well-doped region is at the second intermediate voltage, the word line of the top-level select device is set to a floating state; And / or, During the period when the bias voltage of the well-doped region rises to the third intermediate voltage, a third preset voltage is applied to the word line of the bottom-layer select device, and the word line of the bottom-layer select device is maintained at the third preset voltage; wherein the third preset voltage is less than the third intermediate voltage; When the bias voltage of the well-doped region is at the third intermediate voltage, the word line of the bottom-layer select device is set to a floating state.

Images