Data erasing method, storage device, and storage system

Abstract

Embodiments of the present application provide a data erasing method, a storage device and a storage system. The storage device includes a storage block having a plurality of storage strings, each of the storage strings being connected between a bit line and a source and including a plurality of storage cells connected in series, and the storage cells of a same storage layer being connected to a same word line. The data erasing method of the non-volatile storage device includes: applying an erasing voltage to the source, and applying a plurality of different voltages to the word lines of at least one storage layer in sequence within a time of applying the erasing voltage, wherein the plurality of different voltages include at least a first bias voltage and a compensation voltage having a voltage value greater than the first bias voltage. Embodiments of the present application can slow down the aging of the storage device due to the erasing operation.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor structure design and manufacturing, and more specifically, to a data erasure method, storage device and storage system. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase memory density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional memory architectures can address the density and performance limitations inherent in planar memory cells.

[0003] In three-dimensional memory, many layers of memory cells can be stacked vertically to significantly increase the storage density per unit area. To further increase storage density, multiple levels can be stacked vertically, with many vertically stacked memory cells in each level. For efficient reading, writing, and erasing in multi-level three-dimensional memory, each level can be processed as a separate memory block; that is, each level can be erased independently of the others. However, as the performance requirements for three-dimensional memory increase, and the erase speed demands become increasingly faster, the reliability of three-dimensional memory faces extremely high risks. Summary of the Invention

[0004] The embodiments of this application provide a data erasure method, storage device, and storage system that can at least partially solve the above-mentioned problems existing in the prior art.

[0005] One embodiment of this application provides a data erasure method for a non-volatile storage device, wherein the storage device includes a storage block having multiple storage strings, each storage string being connected between a bit line and a source, and including multiple storage cells connected in series, with storage cells of the same storage layer being connected to the same word line. For the storage block to be erased, the method includes: applying an erase voltage to the source, and, during the time the erase voltage is applied, sequentially applying multiple different voltages to the word line of at least one storage layer, wherein the multiple different voltages include at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage.

[0006] In some exemplary embodiments of this application, the voltage values ​​of the multiple different voltages applied sequentially show a decreasing trend from the compensation voltage to the first bias voltage.

[0007] In some exemplary embodiments of this application, the voltage values ​​of the multiple different voltages applied sequentially show a trend of decreasing from the compensation voltage to the first bias voltage and then increasing.

[0008] In some exemplary embodiments of this application, in the direction perpendicular to the storage layer, multiple storage layers are divided into multiple storage regions; sequentially applying multiple different voltages to the word lines of at least one storage layer includes: sequentially applying multiple different voltages to the word lines of the storage layer of the first storage region closest to the source in the multiple storage regions; the method further includes: applying a second bias voltage to the word lines of the storage layers of other storage regions besides the first storage region, the second bias voltage being less than a compensation voltage.

[0009] In some exemplary embodiments of this application, in the direction perpendicular to the storage layer, multiple storage layers are divided into multiple storage areas, and the word lines of the storage layers of at least two storage areas are subject to a compensation voltage and a first bias voltage, and the applied compensation voltage values ​​are different.

[0010] In some exemplary embodiments of this application, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the voltage value of the compensation voltage applied to the word line of the memory layer and the size of the portion of the channel structure surrounded by the control gate are negatively correlated in a cross-section parallel to the memory layer.

[0011] In some exemplary embodiments of this application, in the direction perpendicular to the storage layer, multiple storage layers are divided into multiple storage areas, and the word lines of the storage layers of at least two storage areas are subject to a compensation voltage and a first bias voltage, and the duration for which the first bias voltage is applied is different.

[0012] In some exemplary embodiments of this application, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the duration for which a first bias voltage is applied to the word line of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross section parallel to the memory layer.

[0013] In some exemplary embodiments of this application, the voltage value of the first bias voltage is greater than or equal to 0V and less than or equal to 1V.

[0014] In some exemplary embodiments of this application, the compensation voltage is less than the erase voltage.

[0015] In some exemplary embodiments of this application, the memory block further includes a bottom redundant transistor located between the memory cell and the source, and a top redundant transistor located between the memory cell and the bit line; during the time the erase voltage is applied, the word line connected to the top redundant transistor and the word line connected to the bottom redundant transistor are floated.

[0016] In some exemplary embodiments of this application, the memory block further includes a bottom select transistor located between the memory cell and the source, and a top select transistor located between the memory string and the bit line; during the time the erase voltage is applied, the word line connected to the top select transistor and the word line connected to the bottom select transistor are floated.

[0017] Another embodiment of this application provides a non-volatile memory device, comprising: a memory block including a plurality of memory strings, each memory string being connected between a bit line and a source, and including a plurality of memory cells connected in series, the memory cells of the same memory layer being connected to the same word line; peripheral circuitry coupled to the memory block and performing an erase operation on the memory cells in the memory block, the peripheral circuitry being configured to: apply an erase voltage to the source, and, during the time the erase voltage is applied, sequentially apply a plurality of different voltages to the word line of at least one memory layer, wherein the plurality of different voltages includes at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage.

[0018] In some exemplary embodiments of this application, in the direction of the vertical storage layer, multiple storage layers are divided into multiple storage regions; the peripheral circuit is configured to sequentially apply multiple different voltages to the word lines of the storage layer of the first storage region closest to the source in the multiple storage regions; the peripheral circuit is also configured to apply a second bias voltage to the word lines of the storage layers of other storage regions besides the first storage region, the second bias voltage being less than the compensation voltage.

[0019] In some exemplary embodiments of this application, in the direction perpendicular to the storage layer, multiple storage layers are divided into multiple storage areas, and the word lines of the storage layers of at least two storage areas are subject to a compensation voltage and a first bias voltage, and the applied compensation voltage values ​​are different.

[0020] In some exemplary embodiments of this application, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the voltage value of the compensation voltage applied to the word line of the memory layer and the size of the portion of the channel structure surrounded by the control gate are negatively correlated in a cross-section parallel to the memory layer.

[0021] In some exemplary embodiments of this application, in the direction perpendicular to the storage layer, multiple storage layers are divided into multiple storage areas, and the word lines of the storage layers of at least two storage areas are subjected to a compensation voltage and the first bias voltage, and the duration for which the first bias voltage is applied is different.

[0022] In some exemplary embodiments of this application, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the duration for which a first bias voltage is applied to the word line of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross section parallel to the memory layer.

[0023] Another embodiment of this application provides a non-volatile memory system, comprising: a non-volatile memory device including a memory block having a plurality of memory strings and peripheral circuitry coupled to the memory block, each memory string being connected between a bit line and a source and including a plurality of memory cells connected in series, memory cells of the same memory layer being connected to the same word line; and a controller coupled to the memory device and configured to control the memory device; wherein the peripheral circuitry is configured to: apply an erase voltage to the source, and during the time the erase voltage is applied, sequentially apply a plurality of different voltages to the word line of at least one memory layer, the plurality of different voltages including at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage.

[0024] According to one embodiment of this application, during the process of applying an erase voltage to the source, a compensation voltage with a larger value is applied to the word line of the storage layer to reduce the electric field strength at the channel structure, thereby reducing the pressure on the storage layer, reducing the possibility of breakdown, and thus reducing the probability of programming failure or erase failure, which can improve DPPM. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0026] Figure 1 This is a block diagram of a non-volatile storage device according to an embodiment of this application;

[0027] Figure 2 This is an equivalent circuit diagram of a storage block according to an embodiment of this application;

[0028] Figure 3 It is based on Figure 2 The equivalent circuit diagram of a portion of the memory block is shown;

[0029] Figure 4 It is based on Figure 3 A partial structural diagram of the storage string is shown;

[0030] Figure 5 These are voltage waveform diagrams of the erase operation methods for non-volatile memory devices in some processes;

[0031] Figure 6 This is a voltage waveform diagram of a non-volatile storage device according to some embodiments of this application;

[0032] Figure 7 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0033] Figure 8This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0034] Figure 9 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0035] Figure 10 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0036] Figure 11 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0037] Figure 12 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0038] Figure 13 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0039] Figure 14 This is a voltage waveform diagram of a non-volatile storage device according to another embodiment of this application;

[0040] Figure 15 This is a flowchart of a data erasure method for a non-volatile storage device according to one embodiment of this application;

[0041] Figure 16 This is a block diagram of a non-volatile memory system according to an embodiment of this application;

[0042] Figure 17 This is a schematic diagram of the structure of a non-volatile storage system according to an exemplary embodiment of this application;

[0043] Figure 18 This is a schematic diagram of the structure of another non-volatile storage system according to an exemplary embodiment of this application. Detailed Implementation

[0044] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0046] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0047] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0048] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0050] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0051] Figure 1 This is a schematic block diagram of a non-volatile storage device 10 according to an embodiment of this application. Figure 2 This is an equivalent circuit diagram of storage block BLK1 according to an embodiment of this application. Figure 3 It is based on Figure 2 The diagram shown is an equivalent circuit diagram of a portion of memory block BLK1. Figure 4 It is based on Figure 3The diagram shows a partial structural diagram of the storage string MS.

[0052] In some embodiments of this application, see Figure 1 The non-volatile storage device 10 may, for example, include storage blocks BLK1 to BLKz and peripheral circuitry 120. One or more storage blocks BLK1 to BLKz may form a storage cell array 110. See also... Figure 2 The memory blocks BLK1 to BLKz have multiple memory strings MS11 to MSnm, each memory string being connected to the bit line BL and the source (e.g., Figure 2 The common source line (CSL) is between the storage blocks and includes multiple memory cells (e.g., MC1 to MCk) connected in series. The memory cells MC in the same storage layer are connected to the same word line. The peripheral circuit 120 is coupled to the storage blocks BLK1 to BLKz and performs erase operations, programming operations, etc. on the memory cells (e.g., MC1 to MCk) in the storage blocks BLK1 to BLKz.

[0053] In some embodiments of this application, see Figure 1 and Figure 2 The peripheral circuitry 120 may include, for example, an address decoder 121, a page buffer 122, a control logic circuit 123, an I / O circuit 124, and a voltage generator 125.

[0054] The memory cell array 110 can be connected to the address decoder 121 via, for example, memory layer word lines (WL), top redundant word lines (TRL), bottom redundant word lines (BRL), top select word lines (TSL), and bottom select word lines (BSL), and to the page buffer 122 via, for example, bit lines (BL). Each memory block of the memory cell array 110 may include multiple pages. Exemplarily, the non-volatile memory device 10 performs erase operations on a block-by-block (BLK) basis and performs programming or read operations on a page-by-page basis.

[0055] Address decoder 121 can control word lines connected to memory cell array 110 in response to control logic circuit 123, such as memory layer word line WL, top redundant word line TRL, bottom redundant word line BRL, top select word line TSL, and bottom select word line BSL, wherein memory layer word line WL is connected to memory layer, top redundant word line TRL is connected to top redundant layer, bottom redundant word line BRL is connected to bottom redundant layer, top select word line TSL is connected to top select layer, and bottom select word line BSL is connected to bottom select layer. In other words, address decoder 121 can receive and decode address ADDR from control logic circuit 123, and select one of multiple memory blocks BLK1 to BLK2 in memory cell array 110 according to the decoded address ADDR. For example, one of multiple pages in the selected memory block can be selected. Each memory layer word line WL can be used to control one page. Address decoder 121 can provide the voltage required by memory layer word line WL from voltage generator 125 to the selected memory layer word line WL in the selected memory block BLK.

[0056] Page buffer 122 can function as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer 122 can provide a bit line voltage to the bit line BL of the memory cell array 110 corresponding to the data DATA to be programmed. The data DATA can be multiple bits of data to be programmed. In a read operation, page buffer 122 can sense the data stored in the selected memory cell via the bit line BL and output the sensed data DATA to the I / O circuit 124. Page buffer 122 may include multiple page buffers respectively connected to the bit line BL.

[0057] Control logic circuitry 123 can control address decoder 121, page buffer 122, and voltage generator 125 in response to commands CMD (e.g., programming commands and read commands) and address ADDR from I / O circuitry 124. Furthermore, control logic circuitry 123 can control the non-volatile memory device 10 to perform programming operations via a multi-step method. The multi-step method can execute programming operations multiple times to configure a desired programming state and may include pre / master programming methods, reprogramming methods, shadow programming methods, etc.

[0058] The voltage generator 125 can generate, under the control of the control logic circuit 123, the voltage required to be supplied to the memory layer word line WL, the top redundant word line TRL, the bottom redundant word line BRL, the top select word line TSL, and the bottom select word line BSL.

[0059] Those skilled in the art will understand that the operations performed by the address decoder 121, page buffer 122, control logic circuit 123, and voltage generator 125 described in this application can be executed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0060] In one embodiment of this application, see Figure 2 The memory block BLK1 includes multiple memory strings MS11 to MSnm. Memory strings MS11 to MSnm can be arranged in a two-dimensional array on the xy-plane. Each memory string MS can extend along the z-axis. Taking MS11 as an example, the memory string MS may include, for instance, top select transistors TST11 to TST12, top redundant transistors TRT1 to TRT4, memory cells MC1 to MCk, bottom redundant transistors BRT1 to BRT4, and bottom select transistors BST11 to BST12. That is, the memory string MS may include multiple memory cells MC connected in series between the bit line BL and the source. The memory string MS may also include: a bottom redundant transistor BRT located between the memory cell MC and the source, a top redundant transistor TRT located between the memory cell MC and the bit line BL, a bottom select transistor BST located between the memory cell MC and the source, and a top select transistor TST located between the memory cell MC and the bit line. Memory cells MC in the same memory layer are connected to the same word line (e.g., memory layer word line WL). The number of select transistors (TST / BST), redundant transistors (TRT / BRT), and memory cells (MC) on each memory string (MS) is not specifically limited in this application. Redundant transistors (TRT / BRT) and memory cells (MC) can be charge-trapping MOS transistors, capable of changing their threshold voltage using the tunneling effect, thereby placing memory cells (MC) and / or redundant transistors (TRT / BRT) in different storage states. Select transistors (TST / BST) can be conventional MOS transistors or charge-trapping MOS transistors; this application does not specifically limit their use. Furthermore, since the connection method of the top redundant transistor (TRT) and the bottom redundant transistor (BRT) is the same, this application... Figure 2 The redundant bottom transistor (BRT) and its corresponding structural numbering description have been omitted.

[0061] Multiple memory strings MS11 to MSnm on memory block BLK1 can be connected to the common source line CSL. For example, the source terminals of multiple bottom select transistors BST located at the ends of the multiple memory strings MS11 to MSnm can be connected to the common source line CSL.

[0062] The gates of memory cells MC1 to MCk located at the same or similar height from the common source line CSL in multiple memory strings MS11 to MSnm can be connected to the same memory layer word lines WL1 to WLk. According to the above description, memory cells MC connected to the same memory layer word line WL for simultaneous programming can constitute a page, and a memory block BLK can include multiple pages. Similarly, the gates of redundant transistors TRT / BRT located at the same or similar height from the common source line CSL in multiple memory strings MS11 to MSnm can be connected to the same redundant word line TRL / BRL.

[0063] In a plurality of memory strings (e.g., MS11 to MS1m) arranged along the y-axis, the gate of a top select transistor TST (e.g., TST2) located at the same or similar height from the common source line CSL can be connected to the same top select word line TSL21. Similarly, the gate of a bottom select transistor BST in a plurality of memory strings (e.g., MS11 to MS1m) arranged along the y-axis can be connected to the same bottom select word line BSL. As an alternative, such as Figure 2 As shown, multiple bottom select word lines (BSLs) located at the same or similar height from the common source line (CSL) can be connected to each other. In other words, similar to the memory layer word lines (WL) and redundant word lines (TRL / BRL), the gate terminals of bottom select transistors (BSTs) (e.g., BST2) in multiple memory strings (MS11 to MSnm) located at the same or similar height from the common source line (CSL) can be connected to the same bottom select word line (BSL).

[0064] Multiple memory strings MS11 to MSnm on memory block BLK1 can be connected to multiple bit lines BL1 to BLm. Specifically, the drain terminal of the top select transistor TST located at the same or similar height from the common source line CSL among the multiple memory strings (e.g., MS11 to MSn1) arranged in the x-axis direction can be connected to the same bit line BL.

[0065] It should be understood that this application uses storage block BLK1 as an example for detailed description. Storage block BLK1 may be the same as or similar to other storage blocks BLK2 to BLKz in the storage cell array 110.

[0066] In one embodiment of this application, Figure 3Multiple memory strings MS11 to MS71 connected to the same bit line BL1 are shown. The gates of the top select transistors TST11 to TST71 in memory strings MS11 to MS71 can be connected to the top select word lines TSL11 to TSL71, respectively, and the gates of the top select transistors TST12 to TST72 in memory strings MS11 to MS71 can be connected to the top select word lines TSL12 to TSL72, respectively.

[0067] Figure 4 This is a cross-sectional view of an exemplary storage string MS according to some embodiments of this application. Figure 3 The example shown is a storage string MS. Figure 4 As shown, the non-volatile memory device 10 also includes a well region (not shown) serving as the source of a memory string MS, located on the semiconductor layer 200. The memory string MS extends over the semiconductor layer 200 in a direction substantially perpendicular to the semiconductor layer 200. The semiconductor layer 200 may be a semiconductor substrate, which may include, for example, silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The semiconductor layer 200 may include, for example, a well region, which may be, for example, a P-well or an N-well, and this application is not limited thereto.

[0068] The memory string (MS) may, for example, include a channel structure 220, which may include, for example, a functional layer 221, a channel layer 222, and a channel filling layer 223. The functional layer 221 may include a barrier layer (not shown) that blocks charge outflow, a charge trapping layer (not shown) on the surface of the barrier layer to store charge during operation of the semiconductor structure, and a tunnel insulating layer (not shown) on the surface of the charge trapping layer. The functional layer 221 may include an oxide-nitride-oxide (ONO) structure. The channel layer 222 is capable of transporting the desired charge (electrons or holes). The channel filling layer 223 may include an oxide dielectric layer, such as silicon oxide.

[0069] In some embodiments, the channel structure 220 of the memory string MS extends vertically through a memory stack layer (not shown) having interleaved conductive layers (e.g., 210) and dielectric layers (not shown). The conductive layers (e.g., 210) may be, for example, divided into a top select layer, a top redundancy layer, a memory layer, a bottom redundancy layer, and a bottom select layer. According to some embodiments, the memory layer surrounding the channel structure 220 of the memory string MS is the control gate of the memory cells MC in the memory string MS. In the memory string MS, the memory cells MC may, for example, be arranged vertically in series. In some embodiments, each memory cell MC may, for example, include a control gate (i.e., a portion of the memory layer) and a portion of the channel structure 220 surrounded by the control gate. Similarly, the top select transistor TST includes a top select layer surrounding the channel structure 220 of the memory string MS and a portion of the channel structure 220 surrounded by the top select layer, the top select layer surrounding the channel structure 220 of the memory string MS being the control gate of the top select transistor TST. The top redundant transistor (TRT) includes a top redundant layer surrounding the channel structure 220 of the memory string MS and a portion of the channel structure 220 surrounded by the top redundant layer. The top redundant layer surrounding the channel structure 220 of the memory string MS is the control gate of the top redundant transistor TRT. The bottom select transistor (BST) includes a bottom select layer surrounding the channel structure 220 of the memory string MS and a portion of the channel structure 220 surrounded by the bottom select layer. The bottom select layer surrounding the channel structure 220 of the memory string MS is the control gate of the bottom select transistor BST. The bottom redundant transistor (BRT) includes a bottom redundant layer surrounding the channel structure 220 of the memory string MS and a portion of the channel structure 220 surrounded by the bottom redundant layer. The bottom redundant layer surrounding the channel structure 220 of the memory string MS is the control gate of the bottom redundant transistor BRT. The conductive layer forming the control gate (e.g., 210) is also referred to as a word line coupled to the memory string MS (e.g., ...). Figure 1 The memory layer (WL, TSL, TRL, BSL, and BRL) is capable of receiving word line bias voltages for controlling the operation of the memory cell MC, for example, through read, erase, and program operations. The conductor layer 210 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof.

[0070] It should be understood that, Figures 1 to 4 Taking a non-volatile storage device comprising two top select layers, four top redundancy layers, four bottom redundancy layers, and two bottom select layers as an example, its structure is illustrated. Without departing from this application, the number of each layer can be adjusted as needed, and this application does not impose any restrictions on this.

[0071] When the memory cell MC is programmed, electrons are stored in the portion of the charge trapping layer associated with the memory cell MC. These electrons are drawn from the channel in semiconductor layer 200 into the charge trapping layer and pass through the tunneling layer. The threshold voltage (Vth) of the memory cell MC increases proportionally to the amount of stored charge. When the memory cell MC is erased, electrons are driven back into the channel in semiconductor layer 200. In some processes, the voltage waveform of the erase operation method for non-volatile memory devices is shown in the figure. Figure 5 As shown. During the erase operation, an erase voltage V can be applied to the source, for example, through the common source line CSL. erase This makes the top redundancy layer, bottom redundancy layer, top selection layer, and bottom selection layer float, that is, the top redundancy word line TRL, bottom redundancy word line BRL, top selection word line TSL, and bottom selection word line BSL float, and ground all memory layer word lines WL.

[0072] However, due to current process limitations, as a result of deep-hole etching, the channel structure 220 of the memory string MS may, for example, include a non-uniform lateral dimension (e.g., diameter) along the y-direction. In some embodiments, the diameter of the channel structure 220 of the memory string MS increases from bottom to top. As the performance requirements of 3D memory become increasingly demanding, the erase speed requirement becomes faster, and the erase voltage also needs to be continuously increased. However, increasing the erase voltage will affect many performance aspects of the 3D memory. For example, it can easily lead to degradation of the functional layer of the bottom word line, causing leakage and resulting in memory block BLK failure. In addition, it can also cause degradation of the reliability and read window of the 3D memory, posing a very high risk to reliability. For example, because the bottom dimension of the channel structure 220 is small and the electric field strength is high, the bottom memory layer is subjected to greater pressure. After tens of thousands of programming and erasing operations, the 3D memory is prone to burnout, causing programming or erasing failures, resulting in a worsening of the defective parts per million (DPPM).

[0073] In some embodiments of this application, the peripheral circuit 120 is configured to: apply an erase voltage to the source, and sequentially apply a plurality of different voltages to the word lines of at least one memory layer during the time the erase voltage is applied. The plurality of different voltages includes at least a first bias voltage and a compensation voltage with a value greater than the first bias voltage.

[0074] According to the embodiments of this application, during the application of the erase voltage, the non-volatile memory device applies a larger compensation voltage to the word line of the memory layer to reduce the electric field strength at the channel structure, thereby reducing the pressure on the memory layer, reducing the possibility of breakdown, and thus reducing the probability of programming failure or erase failure, which can improve DPPM.

[0075] In some embodiments of this application, the peripheral circuit 120 may be configured to apply multiple different voltages to the word lines of the memory layer while applying an erase voltage to the source (e.g., the well region of the semiconductor layer 200) of the memory string MS.

[0076] It should be understood that, without departing from the teachings of this application, the peripheral circuit 120 may also be configured to sequentially apply multiple different voltages to the word lines of the memory layer within a preset time period after applying an erase voltage to the source (e.g., the well region of the semiconductor layer 200) of the memory string MS, wherein the preset time period may be, for example, on the order of milliseconds. Since the voltage rise of the semiconductor layer 200 requires a certain amount of time, the peripheral circuit 120 may be configured to apply multiple different voltages to the word lines of the memory layer before or after applying an erase voltage to the semiconductor layer 200, and this application does not limit this.

[0077] In one embodiment of this application, the voltage value of the first bias voltage is greater than or equal to 0V and less than or equal to 1V, so as to improve the data erasure speed.

[0078] In one embodiment of this application, the compensation voltage is greater than the first bias voltage and less than the erase voltage V. erase For example, the compensation voltage ranges from (0V, 3V) to [1V, 3V]. By applying a compensation voltage to the word lines of the memory layer, the voltage difference between the word lines and the semiconductor layer 200 is reduced, thereby reducing damage to the non-volatile memory device caused by a large voltage difference in the memory layer during the initial stage of data erasure. After applying the compensation voltage, a smaller first bias voltage is applied, which increases the voltage difference between the word lines and the semiconductor layer 200, thus enhancing the erasure efficiency.

[0079] It should be understood that, without departing from the teachings of this application, the value of the compensation voltage may be adjusted according to actual conditions, such as the design of the peripheral circuit of the non-volatile memory, and this application does not impose any restrictions on this.

[0080] In one embodiment of this application, the difference between the compensation voltage and the first bias voltage may be, for example, (0V, 3V). However, it is understood that the magnitude of the difference between the compensation voltage and the first bias voltage can be determined based on the voltage switching capability of the non-volatile memory device and the capability of the peripheral circuitry, and this application does not impose any limitations on this.

[0081] In one embodiment of this application, the voltage values ​​of the multiple different voltages applied sequentially follow a decreasing trend from the compensation voltage to the first bias voltage. By gradually reducing the voltage applied to the word lines of the storage layer, data erasure efficiency of the memory block BLK can be improved.

[0082] In one embodiment of this application, the voltage values ​​of the multiple different voltages applied sequentially exhibit a trend of decreasing from the compensation voltage to the first bias voltage and then increasing. The maximum voltage applied during the increasing phase may be less than or equal to the compensation voltage. Increasing the voltage applied to the word lines of the memory layer after the voltage applied to the word lines decreases to the first bias voltage reduces the voltage difference between the channel structure 220 and the semiconductor layer 200 during the later stages of the data erase operation, thus reducing the likelihood of excessively deep erasures.

[0083] In one embodiment of this application, during the time the erase voltage is applied, the word lines connected to the top redundant transistor TRT (i.e., top redundant word lines TRL) and the word lines connected to the bottom redundant transistor BRT (i.e., bottom redundant word lines BRL) are floated. It should be understood that when an element (or component, assembly, member, etc.) is referred to as floating, it is intended to indicate that the element (or component, assembly, member, etc.) does not form an electrical path with other elements (or components, assemblies, members, etc.).

[0084] In one embodiment of this application, during the time the erase voltage is applied, the word line connected to the top select transistor TST (i.e., the top select word line TSL) and the word line connected to the bottom select transistor BST (i.e., the bottom select word line BSL) are floated.

[0085] The following describes, by way of example, the process of applying a compensation voltage and a first bias voltage to a word line of at least one memory layer as described in the embodiments of this application.

[0086] Figures 6 to 14 This is a voltage waveform diagram of the non-volatile storage device 10 according to an embodiment of this application. It should be understood that... Figures 6 to 14 In the embodiment shown, the peripheral circuit 120 is configured to apply an erase voltage V to the source (i.e., the well region) of the memory string. erase The word lines connected to the top redundant transistor TRT (i.e., top redundant word line TRL), the word lines connected to the bottom redundant transistor BRT (i.e., bottom redundant word line BRL), the word lines connected to the top select transistor TST (i.e., top select word line TSL), and the word lines connected to the bottom select transistor BST (i.e., bottom select word line BSL) are floated.

[0087] In one embodiment of this application, the voltage waveform of the non-volatile memory device 10 is as follows: Figure 6 As shown. Figure 6 As shown, the peripheral circuit 120 is also configured to: when an erase voltage V is applied... erase Within a certain time period, a compensation voltage V is sequentially applied to the word line WL of at least one memory layer. offset and the first bias voltage V bias1The compensation voltage V applied to the word lines WL of each memory layer. offset The voltage values ​​can be the same.

[0088] It should be understood that, without departing from the teachings of this application, the non-volatile memory device 10 applies a first bias voltage V to the word lines WL of each memory layer. bias1 The voltage values ​​can be the same or different.

[0089] In another embodiment of this application, in the direction perpendicular to the storage layers, multiple storage layers are divided into multiple storage regions, wherein the storage region closest to the source is the first storage region. The voltage waveform diagram of the non-volatile storage device 10 is shown below. Figure 7 As shown. Figure 7 As shown, the peripheral circuit 120 is configured to: when an erase voltage V is applied... erase Within a certain time period, the word line WL of the storage layer in the first storage area... q1 Apply compensation voltage V sequentially offset and the first bias voltage V bias1 And to the word lines WL of the storage layers of storage areas other than the first storage area. q3 Apply a second bias voltage V bias2 .

[0090] It should be understood that, without departing from the teachings of this application, the second bias voltage V bias2 For example, it could be a low voltage that allows data stored in other memory layers to be stored. For instance, the second bias voltage could be a low voltage of [0V, 1V], such as the ground voltage of 0V, but this application does not limit this.

[0091] It should be understood that, without departing from the teachings of this application, the number of storage layers in the first storage area and the number of storage layers in other storage areas may be set according to the structure, size, etc. of the channel structure 220 in the non-volatile storage device 10, and this application does not impose any restrictions on this.

[0092] It should be understood that, without departing from the teachings of this application, the first bias voltage V bias1 Second bias voltage V bias2 The voltage values ​​can be the same or different, and this application does not impose any restrictions on this.

[0093] In another embodiment of this application, the peripheral circuit 120 is configured to: apply an erase voltage V erase Within a certain time period, multiple compensation voltages and a first bias voltage with different voltage values ​​are sequentially applied to the word line WL of at least one memory layer.

[0094] As an example, the voltage values ​​of the multiple different voltages applied sequentially show a decreasing trend from the compensation voltage to the first bias voltage. For example, the voltage waveform of the non-volatile memory device 10 is shown below. Figure 8 As shown. The peripheral circuit 120 is configured such that, at the erase voltage V... erase During different time segments of the duration, the word line WL to the storage layer of the first storage area q1 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Optionally, the peripheral circuit 120 is also configured to: when an erase voltage V is applied... erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 Data erasure efficiency can be improved by gradually reducing the voltage applied to the word lines of the storage layer to erase data in the memory block BLK.

[0095] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region is the same in each timing segment.

[0096] Optionally, a first bias voltage V is applied to the word lines WL of each memory layer in the first memory region. bias1 The voltage values ​​can be the same.

[0097] It should be understood that, Figure 8 Two compensation voltages (V) with different values ​​are sequentially applied to the word line WL of at least one memory layer. offset1 and V offset2 Taking this as an example, without departing from the teachings of this application, three or more compensation voltages with different voltage values ​​may be applied, and this application does not limit this.

[0098] As another example, the voltage values ​​of the multiple different voltages applied sequentially show a trend of decreasing from the compensation voltage to the first bias voltage and then increasing. For example, the voltage waveform of the non-volatile memory device 10 is shown below. Figure 9 As shown. The peripheral circuit 120 is configured such that, at the erase voltage V... erase During different time segments of the duration, the word line WL to the storage layer of the first storage area q1 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 First bias voltage V bias1 and the third bias voltage V bias2 Optionally, the peripheral circuit 120 is also configured to: when an erase voltage V is applied... eraseWithin a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 During the incremental phase, the maximum applied voltage can be less than or equal to the compensation voltage, i.e., V. bias3 ≤V offset1 After the voltage applied to the word line of the memory layer is reduced to the first bias voltage, the voltage applied to the word line of the memory layer is increased again. This can reduce the voltage difference between the channel structure 220 and the semiconductor layer 200 in the later stage of the data erase operation, and can reduce the possibility of excessive erasure.

[0099] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region is the same in each timing segment.

[0100] Optionally, a first bias voltage V is applied to the word lines WL of each memory layer in the first memory region. bias1 The voltage values ​​can be the same.

[0101] It should be understood that, Figure 9 Two compensation voltages (V) with different values ​​are sequentially applied to the word line WL of at least one memory layer. offset1 and V offset2 The increment phase includes a third bias voltage V. bias3 For example, without departing from the teachings of this application, three or more compensation voltages with different voltage values ​​may be applied, or more bias voltages with different voltage values ​​may be applied during the increment phase. This application does not limit this.

[0102] In another embodiment of this application, in the direction perpendicular to the memory layers, multiple memory layers are divided into multiple memory regions. At least two memory regions have their word lines WL of the memory layers subjected to a compensation voltage and a first bias voltage, and the applied compensation voltage values ​​are different. It should be understood that each memory region's memory layer can have one or more word lines, and the number of word lines in each memory region's memory layer can be the same or different; this application does not impose any limitations on this.

[0103] For example, the storage layer of the memory block BLK can be divided into three storage regions: storage region 1, storage region 2, and storage region 3. Storage regions 1 and 2 are the first storage regions closest to the source. The voltage value of the compensation voltage applied to the word line WL of the same storage layer remains unchanged. The voltage waveform diagram of the non-volatile memory device 10 is shown below. Figure 10 As shown. The peripheral circuit 120 is configured to: when an erase voltage V is applied... erase Within a certain time period, the word line WL of storage area 1 is sent. q1 Apply the first compensation voltage V offset1 and the first bias voltage V bias1Word line WL to storage area 2 q2 Apply a third compensation voltage V offset3 and the first bias voltage V bias1 V offset1 and V offset3 Different. For example, the memory string (MS) includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the voltage value of the compensation voltage applied to the word line of the memory layer and the size of the portion of the channel structure surrounded by the control gate are negatively correlated in terms of their dimensions parallel to the cross-section of the memory layer. In this example, the lateral dimension of memory region 1 is smaller than the lateral dimension of memory region 2, V offset1 >V offset3 For word lines WL of memory layers with large lateral dimensions in channel structure 220, a smaller compensation voltage is applied; for word lines WL of memory layers with small lateral dimensions in channel structure 220, a larger compensation voltage is applied, so that data erasure of each memory layer is more uniform.

[0104] Optionally, the peripheral circuit 120 is also configured to: when an erase voltage V is applied erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 .

[0105] For example, the storage layer of the memory block BLK can be divided into three storage regions: storage region 1, storage region 2, and storage region 3. Storage regions 1 and 2 are the first storage regions closest to the source. Multiple compensation voltages with different values ​​are applied to the word line WL of the same storage layer. The voltage waveform diagram of the non-volatile memory device 10 is shown below. Figure 11 As shown. The peripheral circuit 120 is configured to: when an erase voltage V is applied... erase Within a certain time period, the word line WL of storage area 1 is sent. q1 Apply the first compensation voltage V offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Word line WL to storage area 2 q2 Apply a third compensation voltage V offset3 Fourth compensation voltage V offset4 and the first bias voltage V bias1 V offset1 and V offset2 V offset3 The voltage values ​​are different, V offset3 and V offset4 The voltage values ​​are different. Optionally, the peripheral circuit 120 is also configured to: apply an erase voltage V... erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent.q3 Apply a second bias voltage V bias2 .

[0106] Optionally, the first bias voltage applied to the word lines WL of each memory layer in the first memory region can be the same or different. This application does not impose any limitation on this.

[0107] It should be understood that, Figure 10 and Figure 11 Taking the storage layer of the storage block BLK as an example, which is divided into 3 storage areas, it can also be divided into 4 or more storage areas without departing from the teachings of this application. This application does not limit this.

[0108] It should be understood that, without departing from the teachings of this application, the number of word lines (WL) in each storage area may be the same or different, and this application does not impose any restrictions.

[0109] In one embodiment of this application, the difference between the voltage values ​​of the compensation voltage applied to the word line WL of the first memory region can be, for example, [0V, 3V].

[0110] In one embodiment of this application, the voltage value of the compensation voltage applied to the word line WL of the memory layer and the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer are negatively correlated. For example, the dimension of the channel structure 220 in the x-direction (hereinafter referred to as the lateral dimension) at memory region 1 is smaller, while the lateral dimension of the channel structure 220 at memory region 2 is larger. offset1 >V offset3 .

[0111] For example, generally, the lateral dimension of the channel structure 220 is larger further away from the semiconductor layer 200 and smaller closer to the semiconductor layer 200. Due to the difference in the lateral dimensions of the channel structure 220, the initial electric field strength of the memory cell MC at different channel structures 220 may differ. For instance, the electric field strength of the memory cell MC with a larger lateral dimension in the included channel structure 220 is smaller, while the electric field strength of the memory cell MC with a smaller lateral dimension in the included channel structure 220 is larger. For the data erasure operation of the memory block BLK, it is usually necessary to erase the data in all memory cells MC of the entire memory block BLK. Therefore, the memory layers of the memory block BLK can be partitioned for control, i.e., the memory cells MC can be partitioned for control. For the word line WL of the memory layer with a larger lateral dimension in the channel structure 220, a smaller compensation voltage is applied; for the word line WL of the memory layer with a smaller lateral dimension in the channel structure 220, a larger compensation voltage is applied to ensure more uniform data erasure across all memory layers.

[0112] In another embodiment of this application, in the direction perpendicular to the memory layers, multiple memory layers are divided into multiple memory regions. At least two memory regions have their word lines WL of the memory layers subjected to a compensation voltage and a first bias voltage, and the duration for which the first bias voltage is applied is different. It should be understood that each memory region may have one or more word lines of its memory layer, and the number of word lines in each memory region may be the same or different; this application does not impose any limitations on this.

[0113] The following example illustrates how the storage layer of a storage block BLK can be divided into three storage areas: storage area 1, storage area 2, and storage area 3, with storage area 1 and storage area 2 being the first storage area closest to the source.

[0114] For example, a compensation voltage is applied to the word line WL of the storage layer in the first storage area, and the voltage waveform of the non-volatile storage device 10 is shown in the figure below. Figure 12 As shown. The peripheral circuit 120 is configured to: when an erase voltage V is applied... erase Within a certain time period, the word line WL of storage area 1 is sent. q1 and the word line WL of storage area 2 q2 Apply compensation voltage V offset and the first bias voltage V bias1 A second bias voltage V is applied to the word line of memory area 3. bias2 Among them, the peripheral circuit 120 connects to the word line WL of memory area 1. q1 and the word line WL of storage area 2 q2 The first bias voltage V applied bias1 The time lengths are t1 and t2, respectively. For example, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein, the duration for which a first bias voltage is applied to the word line of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer. In this example, the lateral dimension of memory region 1 is smaller than the lateral dimension of memory region 2, t1 < t2. For the word line WL of the memory layer with a larger lateral dimension of the channel structure 220, the applied first bias voltage time is longer; for the word line WL of the memory layer with a smaller lateral dimension of the channel structure 220, the applied first bias voltage time is shorter, so that the data erasure of each memory layer is more uniform.

[0115] For example, the word line WL of the storage layer in the first storage area is subjected to multiple compensation voltages with different values, and the voltage waveform of the non-volatile storage device 10 is shown in the figure below. Figure 13 As shown. The peripheral circuit 120 is configured to: when an erase voltage V is applied... erase Within a certain time period, the word line WL of storage area 1 is sent. q1 and the word line WL of storage area 2 q2 The first compensation voltage V is applied sequentially.offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 A second bias voltage V is applied to the word line of memory area 3. bias2 Among them, the word line WL to memory area 1 q1 and the word line WL of storage area 2 q2 The durations of the applied first bias voltage are t1 and t2, where t1 < t2. The word line WL of memory region 1 is then applied. q1 and the word line WL of storage area 2 q2 The duration for which the first compensation voltage and the second compensation voltage are applied can be the same or different. Here, we take the example of different durations to illustrate the point.

[0116] For example, at least two memory layers' word lines WL are subjected to multiple compensation voltages with different values, and the applied voltage values ​​are different for each memory layer in different memory regions. The voltage waveform diagram of the non-volatile memory device 10 is as follows: Figure 14 As shown. When an erase voltage V is applied... erase During the specified time period, the peripheral circuit 120 is configured to: apply an erase voltage V erase Within a certain time period, the word line WL of storage area 1 is sent. q1 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Word line WL to storage area 2 q2 The third compensation voltage V is applied sequentially. offset3 Fourth compensation voltage V offset4 and the first bias voltage V bias1 A second bias voltage V is applied to the word line of memory area 3. bias2 V offset1 and V offset2 V offset3 The voltage values ​​are different, V offset3 and V offset4 The voltage values ​​are different. The word line WL to memory area 1... q1 and the word line WL of storage area 2 q2 The durations of the first bias voltage applied are t1 and t2, where t1 < t2.

[0117] It should be understood that, for ease of understanding, the embodiments of this application are illustrated by taking the example that the voltage value of the first bias voltage applied to the word line WL of the storage layer of each first storage area is the same. In other embodiments, the voltage value of the first bias voltage applied to the word line WL of the storage layer of each first storage area may be different.

[0118] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region can be the same or different. If the compensation voltage applied to the word lines WL of each memory layer is different, the difference in voltage values ​​can be, for example, (0V, 3V). This application does not impose any limitations on this.

[0119] It should be understood that, Figure 12 , Figure 13 and Figure 14 Taking the storage layer of the storage block BLK as an example, which is divided into 3 storage areas, it can also be divided into 4 or more storage areas without departing from the teachings of this application. This application does not limit this.

[0120] It should be understood that, without departing from the teachings of this application, the number of word lines (WL) in each storage area may be the same or different, and this application does not impose any restrictions.

[0121] In one embodiment of this application, the duration for which a first bias voltage is applied to the word line WL of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer. For example, the lateral dimension of the channel structure 220 at memory region 1 is smaller, and the lateral dimension of the channel structure 220 at memory region 2 is larger, where t1 < t2.

[0122] For example, generally, the lateral dimension of the channel structure 220 is larger away from the semiconductor layer 200 and smaller closer to the semiconductor layer 200. Due to the difference in the lateral dimension of the channel structure 220, the data erasure speed of the memory cells MC at different channel structures 220 may differ. For instance, the data erasure speed of memory cells MC with larger lateral dimensions in the included channel structure 220 is slower, while the data erasure speed of memory cells MC with smaller lateral dimensions in the included channel structure 220 is faster. For the data erasure operation of the memory block BLK, it is usually necessary to erase the data of all memory cells MC in the entire memory block BLK. Therefore, the memory layers of the memory block BLK can be partitioned for control, that is, the memory cells MC can be partitioned for control. For the word line WL of the memory layer with a larger lateral dimension in the channel structure 220, the first bias voltage applied is applied for a longer time; for the word line WL of the memory layer with a smaller lateral dimension in the channel structure 220, the first bias voltage applied is applied for a shorter time, so that the data erasure of each memory layer is more uniform.

[0123] Figure 15 This is a flowchart of a data erasure method 3000 for a non-volatile storage device according to one embodiment of this application. See also... Figure 2The storage device includes a storage block MLK with multiple storage strings MS, the storage strings MS being connected between the bit line BL and the source, and including multiple storage cells MC connected in series, with storage cells MC of the same storage layer connected to the same word line. For example... Figure 15 As shown, for the storage block MLK to be erased, this application provides a data erasure method 3000 for a non-volatile storage device, including:

[0124] S31, apply an erase voltage to the source.

[0125] S32, during the time the erase voltage is applied, a plurality of different voltages are sequentially applied to the word lines of at least one memory layer. The plurality of different voltages include at least a first bias voltage and a compensation voltage with a value greater than the first bias voltage.

[0126] According to the embodiments of this application, during the application of the erase voltage, a compensation voltage with a larger voltage value is applied to the word line of the memory layer to reduce the electric field strength at the channel structure, thereby reducing the pressure on the memory layer, reducing the possibility of breakdown, and thus reducing the probability of programming failure or erase failure, which can improve DPPM.

[0127] In one embodiment of this application, while applying an erase voltage to the source of the memory string MS (e.g., the well region of the semiconductor layer 200), multiple different voltages can be sequentially applied to the word line WL of the memory layer.

[0128] It should be understood that, without departing from the teachings of this application, considering that the voltage rise of the semiconductor layer 200 requires a certain amount of time, multiple different voltages may be sequentially applied to the word line WL of the memory layer within a preset time after the erase voltage is applied to the source (e.g., the well region of the semiconductor layer 200) of the memory string MS. The preset time may be, for example, on the order of milliseconds or seconds. This application does not impose any limitations on this.

[0129] In one embodiment of this application, the voltage value of the first bias voltage is greater than or equal to 0V and less than or equal to 1V, so as to improve the data erasure speed.

[0130] In one embodiment of this application, the compensation voltage is greater than the first bias voltage and less than the erase voltage V. eraseFor example, the compensation voltage ranges from (0V, 3V) to [1V, 3V]. By applying a compensation voltage to the word line WL of the storage layer, the voltage difference between the word line WL and the semiconductor layer 200 is reduced, thereby reducing damage to the non-volatile storage device caused by a large voltage difference in the storage layer during the initial stage of data erasure. After applying the compensation voltage, a smaller first bias voltage is applied, which increases the voltage difference between the word line WL and the semiconductor layer 200, thus enhancing the erasure efficiency.

[0131] It should be understood that, without departing from the teachings of this application, the value of the compensation voltage may be adjusted according to actual conditions, such as the design of the peripheral circuit of the non-volatile memory, and this application does not impose any restrictions on this.

[0132] In one embodiment of this application, the difference between the compensation voltage and the first bias voltage may be, for example, (0V, 3V). However, it is understood that the magnitude of the difference between the compensation voltage and the first bias voltage can be determined based on the voltage switching capability of the non-volatile memory device and the capability of the peripheral circuitry, and this application does not impose any limitations on this.

[0133] In one embodiment of this application, the voltage values ​​of the multiple different voltages applied sequentially follow a decreasing trend from the compensation voltage to the first bias voltage. By gradually reducing the voltage applied to the word line WL of the storage layer to erase data in the storage block BLK, the data erasure efficiency can be improved.

[0134] In one embodiment of this application, the voltage values ​​of the multiple different voltages applied sequentially exhibit a trend of decreasing from the compensation voltage to the first bias voltage and then increasing. The maximum voltage applied during the increasing phase may be less than or equal to the compensation voltage. After the voltage applied to the word line WL of the memory layer decreases to the first bias voltage, increasing the voltage applied to the word line WL of the memory layer further reduces the voltage difference between the channel structure 220 and the semiconductor layer 200 during the later stages of the data erase operation, thereby reducing the possibility of excessively deep erasures.

[0135] In one embodiment of this application, during the time the erase voltage is applied, the word line connected to the top redundant transistor TRT (i.e., the top redundant word line TRL) and the word line connected to the bottom redundant transistor BRT (i.e., the bottom redundant word line BRL) are floated.

[0136] In one embodiment of this application, during the time the erase voltage is applied, the word line (i.e., top select word line TSL) connected to the top select transistor TST and the bottom select transistor BST (i.e., bottom select word line BSL) are floated.

[0137] The following describes, by way of example, the process of applying a compensation voltage and a first bias voltage to a word line of at least one memory layer as described in the embodiments of this application.

[0138] Figures 6 to 14 This is a voltage waveform diagram of the non-volatile storage device 10 according to an embodiment of this application. It should be understood that... Figures 6 to 14 In the embodiment shown, the non-volatile storage device 10 applies an erase voltage V to the source (i.e., the well region) of the storage string. erase The word lines connected to the top redundant transistor TRT (i.e., top redundant word line TRL), the word lines connected to the bottom redundant transistor BRT (i.e., bottom redundant word line BRL), the word lines connected to the top select transistor TST (i.e., top select word line TSL), and the word lines connected to the bottom select transistor BST (i.e., bottom select word line BSL) are floated.

[0139] In one embodiment of this application, the voltage waveform diagram of the non-volatile memory device 10 is shown below. Figure 6 The non-volatile storage device 10 applies an erase voltage V erase Within a certain time period, a compensation voltage V is sequentially applied to the word line WL of at least one memory layer. offset and the first bias voltage V bias1 The compensation voltage V applied to the word lines WL of each memory layer. offset The voltage values ​​can be the same.

[0140] It should be understood that, without departing from the teachings of this application, the non-volatile memory device 10 applies a first bias voltage V to the word lines WL of each memory layer. bias1 The voltage values ​​can be the same or different.

[0141] In another embodiment of this application, in the direction perpendicular to the storage layers, multiple storage layers are divided into multiple storage regions, wherein the storage region closest to the source is the first storage region. See the voltage waveform diagram of the non-volatile storage device 10. Figure 7 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of the storage layer in the first storage area... q1 Apply compensation voltage V sequentially offset and the first bias voltage V bias1 And to the word lines WL of the storage layers of storage areas other than the first storage area. q3 Apply a second bias voltage V bias2 .

[0142] It should be understood that, without departing from the teachings of this application, the second bias voltage V bias2For example, it could be a low voltage that allows data stored in other memory layers to be stored. For instance, the second bias voltage could be a low voltage of [0V, 1V], such as the ground voltage of 0V, but this application does not limit this.

[0143] It should be understood that, without departing from the teachings of this application, the number of storage layers in the first storage area and the number of storage layers in other storage areas may be set according to the structure, size, etc. of the channel structure 220 in the non-volatile storage device 10, and this application does not impose any restrictions on this.

[0144] It should be understood that, without departing from the teachings of this application, the magnitudes of the first bias voltage and the second bias voltage may be the same or different, and this application does not impose any restrictions on this.

[0145] In another embodiment of this application, the non-volatile storage device 10 applies an erase voltage V erase Within a certain time period, multiple compensation voltages and a first bias voltage with different voltage values ​​are sequentially applied to the word line WL of at least one memory layer.

[0146] As an example, the voltage values ​​of the multiple different voltages applied sequentially show a decreasing trend from the compensation voltage to the first bias voltage. For example, see the voltage waveform diagram of the non-volatile memory device 10. Figure 8 The non-volatile storage device 10 operates at an erase voltage V. erase During different time segments of the duration, the word line WL to the storage layer of the first storage area q1 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Optionally, the non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 Data erasure efficiency can be improved by gradually reducing the voltage applied to the word lines of the storage layer to erase data in the memory block BLK.

[0147] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region is the same in each timing segment.

[0148] Optionally, the first bias voltage applied to the word lines WL of each memory layer in the first memory region can also be the same.

[0149] It should be understood that, Figure 8 Two compensation voltages (V) with different values ​​are sequentially applied to the word line WL of at least one memory layer. offset1 and Voffset2 Taking this as an example, without departing from the teachings of this application, three or more compensation voltages with different voltage values ​​may be applied, and this application does not limit this.

[0150] As another example, the voltage values ​​of the multiple different voltages applied sequentially show a trend of decreasing from the compensation voltage to the first bias voltage and then increasing. For example, the voltage waveform of the non-volatile memory device 10 is shown below. Figure 9 As shown. The peripheral circuit 120 is configured such that, at the erase voltage V... erase During different time segments of the duration, the word line WL to the storage layer of the first storage area q1 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 First bias voltage V bias1 and the third bias voltage V bias2 Optionally, the peripheral circuit 120 is also configured to: when an erase voltage V is applied... erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 During the incremental phase, the maximum applied voltage can be less than or equal to the compensation voltage, i.e., V. bias3 ≤V offset1 After the voltage applied to the word line of the memory layer is reduced to the first bias voltage, the voltage applied to the word line of the memory layer is increased again. This can reduce the voltage difference between the channel structure 220 and the semiconductor layer 200 in the later stage of the data erase operation, and can reduce the possibility of excessive erasure.

[0151] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region is the same in each timing segment.

[0152] Optionally, a first bias voltage V is applied to the word lines WL of each memory layer in the first memory region. bias1 The voltage values ​​can be the same.

[0153] It should be understood that, Figure 9 Two compensation voltages (V) with different values ​​are sequentially applied to the word line WL of at least one memory layer. offset1 and V offset2 The increment phase includes a third bias voltage V. bias3 For example, without departing from the teachings of this application, three or more compensation voltages with different voltage values ​​may be applied, or more bias voltages with different voltage values ​​may be applied during the increment phase. This application does not limit this.

[0154] In another embodiment of this application, in the direction perpendicular to the memory layers, multiple memory layers are divided into multiple memory regions. At least two memory regions have their word lines WL of the memory layers subjected to a compensation voltage and a first bias voltage, and the applied compensation voltage values ​​are different. It should be understood that each memory region's memory layer can have one or more word lines, and the number of word lines in each memory region's memory layer can be the same or different; this application does not impose any limitations on this.

[0155] For example, the storage layer of the storage block BLK can be divided into three storage regions: storage region 1, storage region 2, and storage region 3. Storage regions 1 and 2 are the first storage regions closest to the source of the storage string MS. The voltage value of the compensation voltage applied to the word line WL of the same storage layer remains unchanged. See the voltage waveform diagram of the non-volatile storage device 10. Figure 10 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of storage area 1 is sent. q1 Apply the first compensation voltage V offset1 and the first bias voltage V bias1 Word line WL to storage area 2 q2 Apply a third compensation voltage V offset3 and the first bias voltage V bias1 V offset1 and V offset3 Different. For example, the memory string (MS) includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein the voltage value of the compensation voltage applied to the word line of the memory layer and the size of the portion of the channel structure surrounded by the control gate are negatively correlated in terms of their dimensions parallel to the cross-section of the memory layer. In this example, the lateral dimension of memory region 1 is smaller than the lateral dimension of memory region 2, V offset1 >V offset3 For word lines WL of memory layers with large lateral dimensions in channel structure 220, a smaller compensation voltage is applied; for word lines WL of memory layers with small lateral dimensions in channel structure 220, a larger compensation voltage is applied, so that data erasure of each memory layer is more uniform.

[0156] Optionally, the non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 .

[0157] For example, the storage layer of the storage block BLK can be divided into three storage areas: storage area 1, storage area 2, and storage area 3. Storage areas 1 and 2 are the first storage areas, located closest to the source of the storage string MS. Multiple compensation voltages with different values ​​are applied to the word line WL of the same storage layer. See the voltage waveform diagram of the non-volatile storage device 10. Figure 11 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of storage area 1 is sent. q1 Apply the first compensation voltage V offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Word line WL to storage area 2 q2 Apply a third compensation voltage V offset3 Fourth compensation voltage V offset4 and the first bias voltage V bias1 V offset1 and V offset2 V offset3 The voltage values ​​are different, V offset3 and V offset4 The voltage values ​​are different. Alternatively, the non-volatile storage device 10 can be used when an erase voltage V is applied. erase Within a certain time period, the word lines WL of the storage layers in the storage areas other than the first storage area are sent. q3 Apply a second bias voltage V bias2 .

[0158] Optionally, the first bias voltage applied to the word lines WL of each memory layer in the first memory region can be the same or different. This application does not impose any limitation on this.

[0159] It should be understood that, Figure 10 and Figure 11 Taking the storage layer of the storage block BLK as an example, which is divided into 3 storage areas, it can also be divided into 4 or more storage areas without departing from the teachings of this application. This application does not limit this.

[0160] It should be understood that, without departing from the teachings of this application, the number of word lines (WL) in each storage area may be the same or different, and this application does not impose any restrictions.

[0161] In one embodiment of this application, the range of the difference between the voltage values ​​of the compensation voltage applied to the word lines WL of each memory region of the first memory region may be, for example, [0V, 3V].

[0162] In one embodiment of this application, the voltage value of the compensation voltage applied to the word line WL of the memory layer and the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer are negatively correlated. For example, the dimension of the channel structure 220 in the x-direction (hereinafter referred to as the lateral dimension) at memory region 1 is smaller, while the lateral dimension of the channel structure 220 at memory region 2 is larger. offset1 >V offset3 .

[0163] For example, generally, the lateral dimension of the channel structure 220 is larger further away from the semiconductor layer 200 and smaller closer to the semiconductor layer 200. Due to the difference in the lateral dimensions of the channel structure 220, the initial electric field strength of the memory cell MC at different channel structures 220 may differ. For instance, the electric field strength of the memory cell MC with a larger lateral dimension in the included channel structure 220 is smaller, while the electric field strength of the memory cell MC with a smaller lateral dimension in the included channel structure 220 is larger. For the data erasure operation of the memory block BLK, it is usually necessary to erase the data in all memory cells MC of the entire memory block BLK. Therefore, the memory layers of the memory block BLK can be partitioned for control, i.e., the memory cells MC can be partitioned for control. For the word line WL of the memory layer with a larger lateral dimension in the channel structure 220, a smaller compensation voltage is applied; for the word line WL of the memory layer with a smaller lateral dimension in the channel structure 220, a larger compensation voltage is applied to ensure more uniform data erasure across all memory layers.

[0164] In another embodiment of this application, in the direction perpendicular to the memory layers, multiple memory layers are divided into multiple memory regions. At least two memory regions have their word lines WL of the memory layers subjected to a compensation voltage and a first bias voltage, and the applied compensation voltage values ​​are different. It should be understood that each memory region's memory layer can have one or more word lines, and the number of word lines in each memory region's memory layer can be the same or different; this application does not impose any limitations on this.

[0165] The following example illustrates how the storage layer of a storage block BLK can be divided into three storage areas: storage area 1, storage area 2, and storage area 3. Storage area 1 and storage area 2 are the first storage areas that are close to the source of the storage string MS.

[0166] For example, a compensation voltage is applied to the word line WL of the storage layer in the first storage area. See the voltage waveform diagram of the non-volatile storage device 10. Figure 12 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of storage area 1 is sent. q1 and the word line WL of storage area 2 q2 Apply compensation voltage V offset and the first bias voltage Vbias1 A second bias voltage V is applied to the word line of memory area 3. bias2 Among them, the non-volatile storage device 10 provides a word line WL to the storage area 1. q1 and the word line WL of storage area 2 q2 The first bias voltage V applied bias1 The time lengths are t1 and t2, respectively. For example, the memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate; wherein, the duration for which a first bias voltage is applied to the word line of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer. In this example, the lateral dimension of memory region 1 is smaller than the lateral dimension of memory region 2, t1 < t2. For the word line WL of the memory layer with a larger lateral dimension of the channel structure 220, the applied first bias voltage time is longer; for the word line WL of the memory layer with a smaller lateral dimension of the channel structure 220, the applied first bias voltage time is shorter, so that the data erasure of each memory layer is more uniform.

[0167] For example, multiple compensation voltages with different values ​​are applied to the word line WL of the storage layer in the first storage area. See the voltage waveform diagram of the non-volatile storage device 10. Figure 13 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of storage area 1 is sent. q1 and the word line WL of storage area 2 q2 The first compensation voltage V is applied sequentially. offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 A second bias voltage V is applied to the word line of memory area 3. bias2 Among them, the word line WL to memory area 1 q1 and the word line WL of storage area 2 q2 The durations of the applied first bias voltage are t1 and t2, where t1 < t2. The word line WL of memory region 1 is then applied. q1 and the word line WL of storage area 2 q2 The duration for which the first compensation voltage and the second compensation voltage are applied can be the same or different. Here, we take the example of different durations to illustrate the point.

[0168] For example, multiple compensation voltages with different values ​​are applied to the word lines WL of at least two memory layers, and the applied voltage values ​​are different for the word lines WL of each memory layer in different memory layers. See the voltage waveform diagram of the non-volatile memory device 10. Figure 14 The non-volatile storage device 10 applies an erase voltage V. erase Within a certain time period, the word line WL of storage area 1 is sent. q1 The first compensation voltage V is applied sequentially.offset1 Second compensation voltage V offset2 and the first bias voltage V bias1 Word line WL to storage area 2 q2 The third compensation voltage V is applied sequentially. offset3 Fourth compensation voltage V offset4 and the first bias voltage V bias1 A second bias voltage V is applied to the word line of memory area 3. bias2 V offset1 and V offset2 V offset3 The voltage values ​​are different, V offset3 and V offset4 The voltage values ​​are different. The word line WL to memory area 1... q1 and the word line WL of storage area 2 q2 The durations of the first bias voltage applied are t1 and t2, where t1 < t2.

[0169] It should be understood that, for ease of understanding, the embodiments of this application are illustrated by taking the example that the voltage value of the first bias voltage applied to the word line WL of the storage layer of each first storage area is the same. In other embodiments, the voltage value of the first bias voltage applied to the word line WL of the storage layer of each first storage area may be different. This application does not limit this.

[0170] Optionally, the compensation voltage applied to the word lines WL of each memory layer in the first memory region can be the same or different. If the compensation voltage applied to the word lines WL of each memory layer is different, the difference in voltage values ​​can be, for example, (0V, 3V). This application does not impose any limitations on this.

[0171] It should be understood that, Figure 12 , Figure 13 and Figure 14 Taking the storage layer of the storage block BLK as an example, which is divided into 3 storage areas, it can also be divided into 4 or more storage areas without departing from the teachings of this application. This application does not limit this.

[0172] It should be understood that, without departing from the teachings of this application, the number of word lines (WL) in each storage area may be the same or different, and this application does not impose any restrictions.

[0173] In one embodiment of this application, the duration for which a first bias voltage is applied to the word line WL of the memory layer is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer. For example, the lateral dimension of the channel structure 220 at memory region 1 is smaller, and the lateral dimension of the channel structure 220 at memory region 2 is larger, where t1 < t2.

[0174] For example, generally, the lateral dimension of the channel structure 220 is larger away from the semiconductor layer 200 and smaller closer to the semiconductor layer 200. Due to the difference in the lateral dimension of the channel structure 220, the data erasure speed of the memory cells MC at different channel structures 220 may differ. For instance, the data erasure speed of memory cells MC with larger lateral dimensions in the included channel structure 220 is slower, while the data erasure speed of memory cells MC with smaller lateral dimensions in the included channel structure 220 is faster. For the data erasure operation of the memory block BLK, it is usually necessary to erase the data of all memory cells MC in the entire memory block BLK. Therefore, the memory layers of the memory block BLK can be partitioned for control, that is, the memory cells MC can be partitioned for control. For the word line WL of the memory layer with a larger lateral dimension in the channel structure 220, the first bias voltage applied is applied for a longer time; for the word line WL of the memory layer with a smaller lateral dimension in the channel structure 220, the first bias voltage applied is applied for a shorter time, so that the data erasure of each memory layer is more uniform.

[0175] Figure 16 This is a block diagram of a non-volatile storage system according to an embodiment of this application. For example... Figure 16 As shown, the non-volatile storage system 40 includes a non-volatile storage device 10 and a controller 41.

[0176] Storage device 10 may be the same as the non-volatile storage device described in any of the embodiments above, and will not be described again in this application.

[0177] The controller 41 can control the storage device 10 via the channel CH, and the storage device 10 can perform operations based on the control of the controller 41 in response to a request from the host 50. The storage device 10 can receive a command CMD and an address ADDR from the controller 41 via the channel CH and access a region selected from the memory cell array in response to the address. In other words, the storage device 10 can perform internal operations corresponding to the command on the region selected by the address. More specifically, the controller 41 sends a command and an address ADDR via the channel CH to execute the data erasure method 3000 described in any of the embodiments above, causing the storage device 10 to execute the data erasure method 3000.

[0178] In such Figure 17In the example shown, the controller 41 and the single non-volatile storage device 10 can be integrated into the memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card may also include a memory card connector 42 that couples the memory card to the host 50.

[0179] In such Figure 18 In another example shown, the controller 41 and multiple non-volatile storage devices 10 can be integrated into a solid-state drive (SSD). The SSD may also include an SSD connector 43 that couples the SSD to a host (not shown). In some embodiments, the storage capacity and / or operating speed of the SSD is higher than... Figure 17 The storage capacity and / or operating speed of the memory card shown.

[0180] Although the structure of the non-volatile storage device 10 and the non-volatile storage system 40 has been described herein, it will be understood that one or more features may be omitted, substituted, or added from the non-volatile storage device 10 and the non-volatile storage system 40.

[0181] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for erasing data from a non-volatile storage device, wherein, The storage device includes a storage block having multiple storage strings, each storage string being connected between a bit line and a source, and including multiple storage cells connected in series, with storage cells in the same storage layer connected to the same word line. The method for the storage block to be erased includes: An erase voltage is applied to the source, and During the time the erase voltage is applied, multiple different voltages are sequentially applied to at least one word line of the memory layer. Among the plurality of different voltages, at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage are included. The storage string includes a channel structure, and the storage cell includes a control gate and a portion of the channel structure surrounded by the control gate; The voltage value of the compensation voltage applied to the word line of the memory layer and the dimension of the portion of the channel structure surrounded by the control gate in a cross section parallel to the memory layer are negatively correlated.

2. The method according to claim 1, wherein, The voltage values ​​of the plurality of different voltages applied sequentially show a decreasing trend from the compensation voltage to the first bias voltage.

3. The method according to claim 1, wherein, The voltage values ​​of the multiple different voltages applied sequentially show a trend of decreasing from the compensation voltage to the first bias voltage and then increasing.

4. The method according to any one of claims 1 to 3, wherein, In the direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage areas; Applying multiple different voltages sequentially to at least one word line of the memory layer includes: The plurality of different voltages are sequentially applied to the word lines of the memory layer of the first memory region closest to the source in the plurality of memory regions; The method further includes: A second bias voltage is applied to the word lines of the storage layers of storage areas other than the first storage area. The second bias voltage is less than the compensation voltage.

5. The method according to any one of claims 1 to 3, wherein, In a direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage regions, and the word lines of the storage layers in at least two of the storage regions are subject to the compensation voltage and the first bias voltage, and the applied compensation voltage values ​​are different.

6. The method according to any one of claims 1 to 3, wherein, In the direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage areas, and the word lines of the storage layers in at least two of the storage areas are subject to the compensation voltage and the first bias voltage, and the duration for which the first bias voltage is applied is different.

7. The method according to claim 6, wherein, The duration for which the word line of the memory layer is subjected to the first bias voltage is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer.

8. The method according to any one of claims 1 to 3, wherein, The voltage value of the first bias voltage is greater than or equal to 0V and less than or equal to 1V.

9. The method according to any one of claims 1 to 3, wherein, The compensation voltage is less than the erase voltage.

10. A non-volatile storage device, characterized in that, include: A memory block includes multiple memory strings, each memory string including a channel structure, each memory string being connected between a bit line and a source, and including multiple memory cells connected in series, memory cells in the same memory layer being connected to the same word line, each memory cell including a control gate and a portion of the channel structure surrounded by the control gate; Peripheral circuitry, coupled to the memory block and performing erase operations on the memory cells within the memory block, is configured as follows: An erase voltage is applied to the source, and During the time the erase voltage is applied, multiple different voltages are sequentially applied to at least one word line of the memory layer. Among the plurality of different voltages, at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage are included. The voltage value of the compensation voltage applied to the word line of the memory layer and the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer are negatively correlated.

11. The non-volatile storage device according to claim 10, wherein, In the direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage areas; The peripheral circuit is configured as follows: The plurality of different voltages are sequentially applied to the word lines of the memory layer of the first memory region closest to the source in the plurality of memory regions; The peripheral circuit is also configured to: A second bias voltage is applied to the word lines of the storage layers of storage areas other than the first storage area. The second bias voltage is less than the compensation voltage.

12. The non-volatile storage device according to claim 10, wherein, In a direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage regions, and the word lines of the storage layers in at least two of the storage regions are subject to the compensation voltage and the first bias voltage, and the applied compensation voltage values ​​are different.

13. The non-volatile storage device according to claim 10, wherein, In the direction perpendicular to the storage layers, the plurality of storage layers are divided into a plurality of storage areas, and the word lines of the storage layers in at least two of the storage areas are subject to the compensation voltage and the first bias voltage, and the duration for which the first bias voltage is applied is different.

14. The non-volatile storage device according to claim 13, wherein, The duration for which the word line of the memory layer is subjected to the first bias voltage is positively correlated with the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer.

15. A non-volatile storage system, characterized in that, include: A non-volatile memory device includes a memory block having multiple memory strings and peripheral circuitry coupled to the memory block. Each memory string is connected between a bit line and a source and includes multiple memory cells connected in series, with memory cells in the same memory layer connected to the same word line. as well as A controller coupled to the storage device and configured to control the storage device; The peripheral circuit is configured as follows: An erase voltage is applied to the source, and During the time the erase voltage is applied, a plurality of different voltages are sequentially applied to at least one word line of the memory layer, the plurality of different voltages including at least a first bias voltage and a compensation voltage with a voltage value greater than the first bias voltage; The memory string includes a channel structure, and the memory cell includes a control gate and a portion of the channel structure surrounded by the control gate. The voltage value of the compensation voltage applied to the word line of the memory layer and the dimension of the portion of the channel structure surrounded by the control gate in a cross-section parallel to the memory layer are negatively correlated.

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