Semiconductor device and method for manufacturing the same
By forming scribing grooves in the cutting path area during the integrated circuit manufacturing process and forming scribing grooves and windows in the same photocoat during the chip, the problem of edge collapse and damage caused by stress during the scribing system is solved, the product yield is improved and diffusion and contamination of dielectric layer elements is prevented.
Patent Information
- Application Number
- CN202210434954.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-24
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2042-04-24
AI Technical Summary
During the manufacturing process of integrated circuits, the saw blade of the scribe system is prone to chip edge collapse and chip damage due to stress when cutting the chip, resulting in a decrease in product yield.
By forming scribing grooves in the cutting path area, the cut cut is smaller, and forming scribing grooves and windows in the same photocoat, the photocoat is saved and an isolation layer covers the side walls of the scribing grooves are formed to prevent diffusion of the dielectric layer elements.
It effectively reduces the probability of chip edge collapse and chip damage due to cutting mechanical stress during scribing, improves product yield, and prevents diffusion and contamination of dielectric layer elements.
Smart Images

Figure CN114823315B_ABST
Abstract
Claims
1. A method for manufacturing a semiconductor device, It is characterized in that include: Providing a substrate, on which a dielectric layer is formed, the substrate comprising a chip functional area and a cutting track area, and at least one metal layer is embedded in the dielectric layer in the chip functional area; The dielectric layer is subjected to a photolithography process using the same photomask to form a scribe groove located in the cutting street area and a window located in the chip functional area, wherein the window exposes a portion of the top metal layer in the at least one metal layer as a pad; wherein a pattern corresponding to the scribe groove and the window is formed in the photomask; and a width of the scribe groove is smaller than a width of the cutting street area; An isolation layer is formed, wherein the isolation layer at least covers the sidewall of the dicing groove.
2. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that A passivation layer is also formed on the dielectric layer. In the photolithography process, the passivation layer and the dielectric layer are sequentially etched to form the scribe groove and the window.
3. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that A plurality of chip functional areas arranged in an array are arranged on the substrate, the cutting road area is provided between adjacent chip functional areas, and the dicing groove is arranged in the cutting road area.
4. The method for manufacturing a semiconductor device according to claim 3, It is characterized in that The substrate is provided with a plurality of rows and columns of chip functional areas, the row direction is perpendicular to the column direction, and the widths of the cutting road areas distributed along the row direction and the column direction are both 70 μm to 90 μm.
5. The method for manufacturing a semiconductor device according to claim 4, It is characterized in that The scribe grooves are formed in the middle regions of the scribe lanes distributed in the row direction and in the middle regions of the scribe lanes distributed in the column direction, and the scribe grooves are crossed to form a grid.
6. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The scribe groove is in a strip shape, and the width of the scribe groove is 20 μm to 30 μm.
7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, It is characterized in that The material of the dielectric layer includes fluorine-containing silicon glass, and the material of the isolation layer includes an oxide layer and / or a silicon nitride layer.
8. The method for manufacturing a semiconductor device according to claim 2, It is characterized in that Forming the isolation layer specifically includes: forming an isolation material layer, wherein the isolation material layer covers the sidewall and bottom of the dicing groove and the sidewall and bottom of the window, and also covers the surface of the passivation layer; The isolation material layer located at the bottom of the scribe groove, the bottom of the window and the surface of the passivation layer is removed by etching, and the remaining isolation material layer located at the sidewall of the scribe groove and the sidewall of the window serves as the isolation layer.
9. A semiconductor device, It is characterized in that include: A substrate, on which a dielectric layer is formed, the substrate comprising a chip functional area and a cutting track area, and at least one metal layer is embedded in the dielectric layer in the chip functional area; A scribe groove and a window, wherein the scribe groove is arranged in the cutting road area, the window is arranged in the chip functional area, and the window exposes a portion of the top metal layer in the at least one metal layer as a pad; the width of the scribe groove is smaller than the width of the cutting road area; An isolation layer at least covers a side wall of the dicing groove.
10. The semiconductor device according to claim 9, It is characterized in that The substrate is provided with a plurality of rows and columns of chip functional areas, and there is a cutting path area between adjacent chip functional areas. The middle area of the cutting path area distributed in the row direction and the middle area of the cutting path area distributed in the column direction are both formed with the dicing grooves, and the dicing grooves are crossed in a grid shape.
Citation Information
Patent Citations
Semiconductor structure, forming method thereof and wafer cutting method
CN112018027A
Semiconductor element and methods for manufacturing the same
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