A manufacturing process of an IGBT device

Abstract

The application provides a preparation process of an IGBT device. After groove etching is performed on a substrate, polysilicon doping and etching are performed to form a planar gate region. After the planar gate region is formed, P well and N well implantation are performed. The application has the beneficial effect of adopting a hybrid structure of a planar gate structure and a trench gate structure, so that higher short-circuit resistance and more optimized dynamic characteristics are achieved while static parameters of the device remain basically unchanged.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor devices, and particularly relates to a preparation process of an IGBT device. BACKGROUND

[0002] The front structure of the IGBT device in the prior art mainly adopts a trench gate structure, and the development trend is to adopt a higher trench density to reduce the forward conduction voltage drop of the device, but at the same time, the problems of excessive saturation current and poor short circuit capability are caused, and each supplier is trying to improve and optimize the device to improve the performance and the robustness of the device.

[0003] The cell structure of the existing trench gate IGBT device adopts a vertical channel, and some products adopt a micro trench structure, the target of which is to improve the current density, optimize the conduction characteristics of the device, and reduce the chip area. The mass production products of main manufacturers mainly adopt uniformly distributed trenches, and individual manufacturers adopt non-uniformly distributed cell layouts. However, due to the high trench density and high current density, the structure causes excessive saturation current and poor short circuit capability. SUMMARY

[0004] In view of the above problems, the present application provides a preparation process of an IGBT device to solve the above or other previous problems existing in the prior art.

[0005] To solve the above technical problems, the technical solution adopted by the present application is: a preparation process of an IGBT device, after trench etching on a substrate, polycrystalline silicon doping and etching are performed to form a planar gate region, after the formation of the planar gate region, P-well and N-well implantation is performed.

[0006] Further, in the step of performing polycrystalline silicon doping and etching to form a planar gate region, the following steps are included:

[0007] Performing polycrystalline silicon deposition and doping to form a polycrystalline silicon gate;

[0008] Performing photoetching on the polycrystalline silicon gate: sequentially performing glue coating, exposure and development to form a planar gate region;

[0009] Performing etching on the polycrystalline silicon gate to remove the exposed polycrystalline silicon of the planar part;

[0010] Removing the photoresist.

[0011] Further, in the step of performing polycrystalline silicon deposition and doping to form a polycrystalline silicon gate, the deposition and doping of the polycrystalline silicon are performed by a CVD method, the deposition thickness of the polycrystalline silicon is 3000-20000A, and the doping concentration is 1E16-1E22 cm-3.

[0012] Further, in the trench etching step, the trench etching and gate oxidation are performed to form a trench and a gate oxide layer on the side wall and the top plane of the trench, including the following steps:

[0013] Depositing a first dielectric layer on the substrate;

[0014] Trench layer photoetching: coating, exposing and developing on the first dielectric layer to form a trench area;

[0015] Etching the first dielectric layer to remove the first dielectric layer in the trench area;

[0016] Removing the photoresist in the trench layer photoetching;

[0017] Trench etching;

[0018] Removing the first dielectric layer;

[0019] Gate oxidation to form a gate oxide layer.

[0020] Further, in the trench etching step, the etching depth is 1-10um and the trench side wall angle is 85-95°.

[0021] Further, in the gate oxidation step, the gate oxide layer is formed by thermal oxidation or CVD, and the thickness of the gate oxide layer is 200-5000A.

[0022] Further, in the P-well and N-well implantation step, the P-well implantation includes the following steps:

[0023] P-well implantation with a dose of 1E12-1E16 and an implantation energy of 30keV-160keV;

[0024] P-well pushing to form a P-well with a certain depth, the depth range is 2-7um.

[0025] Further, after P-well pushing, N-well implantation is performed, including the following steps:

[0026] N-well photoetching: coating, exposing and developing in sequence to form an N-well area;

[0027] N-well implantation;

[0028] Removing the photoresist in the N-well photoetching.

[0029] Further, after N-well implantation, N-well activation and hole layer etching are performed, including the following steps:

[0030] Dielectric layer deposition;

[0031] N-well activation;

[0032] Pore layer photoetching, glue coating, exposure, development are sequentially performed to form a contact hole area;

[0033] Pore layer etching, etching is performed on the contact hole area to remove the photoresist of the pore layer photoetching.

[0034] Further, in the medium layer deposition step, the medium layer is deposited by thermal oxidation or CVD, the thickness of the medium layer is 2000-30000A, and the material of the medium layer is silicon dioxide, TEOS, PSG, BPSG or silicon nitride.

[0035] Further, in the N-well activation step, the N-well is activated by furnace tube or rapid annealing, the temperature is 800-1100℃, and the time is 30s-120min.

[0036] Further, after the pore layer etching, metal electrode deposition is performed, the metal electrode is deposited by evaporation or sputtering, and the thickness is 3000-80000A.

[0037] Further, after the metal electrode deposition, the back of the wafer is processed, including back doping, back activation and back electrode deposition, the back doping is performed by ion implantation to dope the doping elements, and the implantation energy is 30-120keV.

[0038] Further, in the back activation step, the back is activated by furnace tube, rapid annealing or laser annealing;

[0039] In the back electrode deposition step, the back metal electrode is deposited by evaporation or sputtering, and the thickness is 800-80000A.

[0040] With the technical scheme, the IGBT device adopts a hybrid structure of planar gate structure and trench gate structure, realizes optimization of short circuit capability and switching characteristics of the trench IGBT device, the plurality of trench gate structures are arranged on both sides of the planar gate structure, in the planar gate structure, a gate oxide layer, a polysilicon gate, a dielectric layer and a front metal are sequentially arranged on the substrate, a P well and an N well are arranged on both sides of the substrate, in the trench gate structure, a P well and an N well are arranged on both sides of the outside of the trench, a gate oxide layer is arranged on the sidewall in the trench, a polysilicon gate is arranged in the trench, and a dielectric layer and a front metal are arranged on the top of the trench, so that the device can be completely compatible with the existing product manufacturing line when the device is prepared, after the trench etching, the polysilicon doping and etching are performed to form the planar gate area, after the planar gate area is formed, the P well and the N well are implanted to form the planar gate structure and the trench gate structure, the higher short circuit resistance capability and the more optimized dynamic characteristics are achieved under the condition that the static parameters of the device are basically unchanged, the robustness of the device is improved, the thicknesses of the gate oxide layers of the planar gate structure and the trench gate structure are different, the threshold voltages are different, and the switching characteristics of the device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 FIG. 1 is a structure schematic diagram of an IGBT device of an embodiment of the present application (only the original cell structure is embodied, and the terminal voltage resistance structure is not embodied);

[0042] Figure 2 FIG. 2 is a structure schematic diagram of first dielectric layer deposition of an embodiment of the present application;

[0043] Figure 3 FIG. 3 is a structure schematic diagram of trench layer photoetching of an embodiment of the present application;

[0044] Figure 4 FIG. 4 is a structure schematic diagram of first dielectric layer etching of an embodiment of the present application;

[0045] Figure 5 FIG. 5 is a structure schematic diagram of trench layer photoetching and degumming of an embodiment of the present application;

[0046] Figure 6 FIG. 6 is a structure schematic diagram of trench etching of an embodiment of the present application;

[0047] Figure 7 FIG. 7 is a structure schematic diagram of first dielectric layer removal of an embodiment of the present application;

[0048] Figure 8 FIG. 8 is a structure schematic diagram of gate oxidation of an embodiment of the present application;

[0049] Figure 9 FIG. 9 is a structure schematic diagram of polysilicon gate deposition of an embodiment of the present application;

[0050] Figure 10 Figure 1 is a structural diagram of a polysilicon gate lithography according to an embodiment of the present application;

[0051] Figure 11 Figure 2 is a structural diagram of a polysilicon gate etching according to an embodiment of the present application;

[0052] Figure 12 Figure 3 is a structural diagram of a polysilicon gate lithography stripping according to an embodiment of the present application;

[0053] Figure 13 Figure 4 is a structural diagram of a P-well implantation according to an embodiment of the present application;

[0054] Figure 14 Figure 5 is a structural diagram of a P-well implantation according to an embodiment of the present application;

[0055] Figure 15 Figure 6 is a structural diagram of a P-well implantation according to an embodiment of the present application;

[0056] Figure 16 Figure 7 is a structural diagram of an N-well lithography according to an embodiment of the present application;

[0057] Figure 17 Figure 8 is a structural diagram of an N-well implantation according to an embodiment of the present application;

[0058] Figure 18 Figure 9 is a structural diagram of an N-well lithography stripping according to an embodiment of the present application;

[0059] Figure 19 Figure 10 is a structural diagram of a dielectric layer deposition according to an embodiment of the present application;

[0060] Figure 20 Figure 11 is a structural diagram of an N-well activation according to an embodiment of the present application;

[0061] Figure 21 Figure 12 is a structural diagram of a hole layer lithography according to an embodiment of the present application;

[0062] Figure 22 Figure 13 is a structural diagram of a hole layer etching according to an embodiment of the present application;

[0063] Figure 23 Figure 14 is a structural diagram of a front metal deposition according to an embodiment of the present application;

[0064] Figure 24 Figure 15 is a structural diagram of a back implantation according to an embodiment of the present application;

[0065] Figure 25 Figure 16 is a structural diagram of a back activation according to an embodiment of the present application;

[0066] Figure 26This is a schematic diagram of the back electrode deposition structure according to an embodiment of the present invention.

[0067] In the picture:

[0068] 1. Substrate; 2. P-well; 3. Polysilicon gate; 4. Trench; 5. N-well; 6. Gate oxide layer; 7. Dielectric layer; 8. Front metal; 9. Back metal; 10. First dielectric layer; 11. Photoresist; 100. Planar gate structure; 200. Trench gate structure. Detailed Implementation

[0069] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0070] Figure 1 The diagram shows a structural schematic of an embodiment of the present invention. This embodiment relates to a fabrication process of an IGBT device, which has a planar gate structure and a trench gate structure. By using a hybrid structure of planar gate cell structure and trench gate cell structure, the short-circuit capability and switching characteristics of the trench IGBT device are optimized. Different cell regions have different threshold voltages due to different gate oxide layer thicknesses, thereby improving the switching characteristics of the device.

[0071] An IGBT device fabrication process involves etching trenches 4 on a substrate 1, followed by polysilicon doping and etching to form a planar gate region. After the planar gate region is formed, P-wells 2 and N-wells 5 are implanted to form a planar gate structure 100 and multiple trench gate structures 200 on the front side of the substrate 1. The hybrid structure of the planar gate structure 100 and the trench gate structure 200 optimizes the short-circuit capability and switching characteristics of the IGBT device.

[0072] Specifically, the fabrication process of this IGBT device includes the following steps:

[0073] Trench etching is performed on substrate 1. In this step, trench etching and gate oxidation are performed to form trench 4, and a gate oxide layer 6 is formed on the sidewalls and top plane portion of trench 4. The steps include:

[0074] Provide a substrate 1;

[0075] Deposition of the first dielectric layer 10: such as Figure 2 As shown, a first dielectric layer 10 is deposited on the front side of the substrate 1. The first dielectric layer 10 can be deposited by thermal oxidation or CVD. The first dielectric layer 10 is a one-layer or multi-layer film structure. The material of the first dielectric layer 10 is silicon dioxide, TEOS, or silicon nitride, or other materials, which are selected according to actual needs and are not specifically required here. The thickness of the first dielectric layer 10 is 3000-20000 Å, which is selected and set according to actual needs and is not specifically required here.

[0076] Trench layer photolithography: such as Figure 3 As shown, a photoresist is applied, exposed, and developed on the first dielectric layer 10 to form a trench region. According to the design requirements, a suitable photomask is selected, and a photoresist is applied, exposed, and developed to form holes on the first dielectric layer 10. These holes are not covered by the photoresist 11 and expose the first dielectric layer 10. The exposed area of ​​the first dielectric layer 10 is the trench region, which is then used for subsequent trench etching.

[0077] The first dielectric layer 10 is etched, such as... Figure 4 As shown, the first dielectric layer 10 of the trench region is removed, so that the silicon surface of the trench region is exposed. When etching the first dielectric layer 10, the first dielectric layer 10 of the trench region is removed by dry etching, so that the silicon surface to be etched is exposed for subsequent trench etching.

[0078] Remove photoresist 11, such as Figure 5 As shown, the photoresist 11 applied during trench layer photolithography is removed by wet or dry stripping, exposing the first dielectric layer 10 covered by the photoresist 11.

[0079] Perform trench etching, such as Figure 6 As shown, in this step, the exposed silicon surface is etched with a dry etching device to form a trench 4 structure. During the trench etching process, the etching depth is 1um-10um and the trench sidewall angle is 85°-95°. The etching depth and trench sidewall angle are selected according to the requirements of the device design, and no specific requirements are made here.

[0080] Remove the first dielectric layer 10, such as Figure 7 As shown, after the trench etching is completed, the first dielectric layer 10 located on the planar portion at the top of the trench 4 is stripped off. The first dielectric layer 10 is removed by wet etching or dry etching. The stripping method is selected according to actual needs, and no specific requirements are made here. Preferably, in this embodiment, since the etching ratio of the wet etching process is high, the stripping method is the wet etching process.

[0081] Gate oxidation is performed to form gate oxide layer 6, such as Figure 8As shown in the step, the gate oxide layer 6 is formed by thermal oxidation or CVD, the thickness of the gate oxide layer 6 is 200-5000A, which is set according to actual needs and the west, and no specific requirements are made here, the gate oxide layer 6 is one or more layers of film structure, and the material of the gate oxide layer 6 is silicon dioxide or silicon nitride, which is selected according to actual needs. At the same time, in this step, the same thickness or different thickness of the gate oxide layer 6 is formed on the sidewall and top flat part of the trench 4 by selecting the crystal direction of the substrate 1 material, which is selected according to the design requirements of the device.

[0082] After the gate oxide layer 6 is formed on the sidewall and top flat part of the trench 4, polysilicon doping and etching are performed to form a planar gate region, including the following steps:

[0083] Polysilicon deposition and doping are performed to form a polysilicon gate 3, as shown in Figure 9 In this step, polysilicon deposition and doping are performed by CVD to form a polysilicon gate 3 for conduction, the polysilicon is deposited in the trench 4 and on the top flat part of the trench 4, covering the entire gate oxide layer 6, the thickness of the polysilicon deposition is 3000-20000A, and the doping concentration is 1E16-1E22cm-3, which is selected according to actual needs, and no specific requirements are made here.

[0084] The polysilicon gate 3 is subjected to photolithography, as shown in Figure 10 Gluing, exposure and development are sequentially performed to form a planar gate region, wherein the planar gate region is the region covered by the photoresist, and the region left by the photoresist is the polysilicon part of the subsequent planar gate.

[0085] The exposed polysilicon part of the polysilicon gate 3 is etched, as shown in Figure 11 The exposed polysilicon part is etched by a dry etching device, and the gate oxide layer 6 covered by the exposed polysilicon part is retained or not retained according to actual needs during dry etching, and no specific requirements are made here.

[0086] The photoresist is removed, as shown in Figure 12 The photoresist used in the photolithography of the polysilicon gate 3 is removed by wet or dry degumming method, and the polysilicon part of the planar gate region covered by the photoresist is exposed.

[0087] After the photolithography and degumming of the polysilicon gate 3, P well 2 and N well 5 implantation are performed, wherein the P well 2 implantation includes the following steps:

[0088] P well implantation, as shown in Figure 13 and 14As shown, the front surface of the wafer is implanted by an ion implanter, the implanted element is P-type impurity, such as boron, the implantation dose is 1E12-1E16, the implantation energy is 30keV-160keV, which is selected according to actual requirements, and no specific requirements are made here;

[0089] P well promotion, such as Figure 15 As shown, the P well 2 with a certain depth is formed by high-temperature diffusion promotion, and the depth range is 2um-7um.

[0090] After the P well is promoted, N well 5 implantation is performed, which includes the following steps:

[0091] N well 5 photoetching, in turn, glue coating, exposure, and development are performed to form an N well region, as shown in Figure 16 As shown, the region not covered by the photoresist is the N well region, and the region left by the photoresist is the region that does not need to form the N well;

[0092] N well implantation, as shown in Figure 17 The N well 5 is formed.

[0093] The photoresist is removed, as shown in Figure 18 The photoresist used in N well 5 photoetching is removed by wet or dry glue removal method, at this time, the gate oxide layer 6 of the trench gate region and the polysilicon part of the planar gate region are exposed.

[0094] N well implantation, as shown in

[0095] Dielectric layer 7 deposition, as shown in Figure 19 The dielectric layer 7 is deposited by thermal oxidation or CVD method, the dielectric layer 7 is one or more film structures, the dielectric layer 7 material is silicon dioxide, TEOS, PSG, BPSG or silicon nitride, the dielectric layer 7 thickness is 2000-30000A, which is selected and set according to actual requirements;

[0096] N well 5 activation, as shown in Figure 20 The N well 5 is activated by furnace tube or rapid annealing method, during the N well 5 activation process, the temperature is 800-1100℃, and the time is 30s-120min.

[0097] Hole layer photoetching, in turn, glue coating, exposure, and development are performed to form a contact hole region, as shown in Figure 21 As shown, the dielectric layer 7 region not covered by the photoresist is the contact hole region, and the dielectric layer 7 region covered by the photoresist is the region that does not need to form the contact hole;

[0098] Hole layer etching, as shown in Figure 22As shown, the exposed dielectric layer 7 is etched by a dry etching and / or wet etching process, and the dielectric layer 7 and the gate oxide layer 6 in the part where the contact hole is needed are etched to expose the silicon surface at the bottom of the gate oxide layer 6.

[0099] After the hole layer is etched, the metal electrode is deposited by evaporation or sputtering to form the front metal 8, as shown in the figure. Figure 23 As shown, the front metal 8 is a single layer or a multi-layer film structure, and the material of the front metal 8 is aluminum, titanium, aluminum-silicon, aluminum-silicon-copper, titanium nitride or titanium tungsten, and the thickness of the front metal 8 is 3000-80000A.

[0100] After the metal electrode deposition, the back of the wafer is processed (in this embodiment, the steps of photolithography, etching and the like of the metal electrode are omitted, and only the process structure of the unit cell area is embodied), the back of the wafer is thinned, the overall thickness of the thinned wafer is selected according to the device voltage withstand requirement, the thinning thickness is 40um-500um, and after the thinning, silicon etching is performed, the silicon etching is selected by wet etching, the etching removal amount is 3um-50um, and the overall back is ensured to meet the voltage withstand of the device, the processes of wafer back thinning and silicon etching are conventional processes, which can be selected and operated according to the existing processes, and further include back doping, back activation and back electrode deposition, wherein in the back doping step, the doping element is doped by ion implantation, the implantation energy is 30-120keV, and the doping element can be selected from boron and other P-type impurities.

[0101] In the back activation step, as shown in the figure, Figure 25 the back is activated by a furnace tube method, a rapid annealing method or a laser annealing method, and the P-type doping of the anode is activated, in which the temperature and time are controlled, and the temperature and time are selected according to the activation method, which is not specifically required here, and preferably, in this embodiment, the back is activated by the furnace tube method, the activation temperature is 350℃-500℃, and the activation time is 30min-120min.

[0102] In the back electrode deposition step, as shown in the figure, Figure 26 the back metal electrode is deposited by evaporation or sputtering to form the back metal 9, the thickness of the back metal 9 is 800-80000A, and the back metal 9 is a multi-layer film composite structure of aluminum, titanium, nickel and silver.

[0103] After the back electrode deposition is completed, the unit cell structure of the IGBT device is formed, as shown in the figure. Figure 1

[0104] A new type of IGBT device structure is prepared by using the above new type of IGBT device preparation process.

[0105] ​A novel IGBT device structure, comprising a substrate 1, a planar gate structure 100 and a plurality of trench gate structures 200, the plurality of trench gate structures 200 being arranged on both sides of the planar gate structure 100, and the planar gate structure 100 and the plurality of trench gate structures 200 being arranged on the front surface of the substrate 1. The planar gate structure 100 is arranged to optimize the device, so that higher short-circuit resistance and more optimized dynamic characteristics are achieved under the condition that the static parameters of the device are basically unchanged, the robustness of the device is improved, and the optimization of the short-circuit capability and switching characteristics of the trench IGBT device is realized through the mixed structure of the planar gate structure 100 and the trench gate structure 200.

[0106] The planar gate structure 100 comprises a gate oxide layer 6, a polysilicon gate 3, a dielectric layer 7 and a front metal 8, at least part of the gate oxide layer 6 is arranged on the substrate 1, the polysilicon gate 3 is arranged on the gate oxide layer 6, the dielectric layer 7 is arranged on the polysilicon gate 3, and the front metal 8 is arranged on the dielectric layer 7. On the substrate 1, the gate oxide layer 6, the polysilicon gate 3, the dielectric layer 7 and the front metal 8 are sequentially arranged from bottom to top in a direction away from the substrate 1.

[0107] The dielectric layer 7 is arranged on the other side of the polysilicon gate 3 opposite to the side in contact with the gate oxide layer 6 and on the circumferential side of the polysilicon gate 3, the dielectric layer 7 wraps the polysilicon gate 3 inside, and the length of the polysilicon gate 3 is less than the length of the gate oxide layer 6, the length of the dielectric layer 7 is consistent with the length of the gate oxide layer 6, the part of the dielectric layer 7 on both sides of the polysilicon gate 3 is in contact with the gate oxide layer 6, and the polysilicon gate 3 is wrapped inside by the dielectric layer 7 and the gate oxide layer 6.

[0108] The polysilicon gate 3 is formed by CVD deposition, the thickness of the polysilicon gate 3 is 3000-20000A, and the doping concentration is 1E16-1E22 cm-3, which is selected according to the actual device design requirements.

[0109] Both sides of the substrate 1 in contact with the gate oxide layer 6 are formed with P-well 2, and N-well 5 is formed in the P-well 2, the P-well 2 and the N-well 5 are sequentially arranged in a direction from the substrate 1 to one side edge of the substrate 1, the depth of the P-well 2 is greater than the depth of the N-well 5, and the P-well 2 and the N-well 5 are in contact with the gate oxide layer 6. At the same time, along the direction from the front surface to the back surface of the substrate 1, the N-well 5 and the P-well 2 are sequentially arranged, the substrate 1, the N-well 5 and the P-well 2 are arranged in the area covered below the gate oxide layer 6, and the N-well 5 and the P-well 2 are arranged on both sides of the substrate 1. The N-well 5 and the P-well 2 are arranged between the substrate 1 of the planar gate structure 100 and the trench 4 of the trench gate structure 200.

[0110] The depth of the P-well 2 is 2-7 um, which is selected according to the actual device design requirements.

[0111] The gate oxide layer 6 is a one or more layer film structure, the material of the gate oxide layer 6 is silicon dioxide or silicon nitride, the thickness of the gate oxide layer 6 is 200-5000 angstroms, which is selected according to actual needs, and no specific requirements are made here. The gate oxide layer 6 is formed by thermal oxidation or CVD.

[0112] The medium layer 7 is a one or more layer film structure, the material of the medium layer 7 is silicon dioxide, TEOS, PSG, BPSG or silicon nitride, the thickness of the medium layer 7 is 2000-30000 angstroms, which is selected according to actual needs, and no specific requirements are made here.

[0113] A plurality of trench gate structures 200 are symmetrically arranged on both sides of the planar gate structure 100, the number of the trench gate structures 200 is selected according to actual needs, and no specific requirements are made here, so that the IGBT device is a hybrid structure of the planar gate structure 100 and the trench gate structure 200, so as to realize the optimization of the short circuit capability and switching characteristics of the trench 4 IGBT device.

[0114] The trench gate structure 200 includes the front metal 8, the medium layer 7, the gate oxide layer 6, the trench 4 and the polysilicon gate 3, the gate oxide layer 6 is arranged on the side wall of the trench 4 and the planar part on the top of the trench 4, the polysilicon gate 3 is arranged inside the trench 4, and the polysilicon gate 3 is located in the internal space of the gate oxide layer 6 structure, the medium layer 7 is arranged on the gate oxide layer 6, and the medium layer 7 is in contact with the polysilicon gate 3 and the gate oxide layer 6, the front metal 8 is arranged on the medium layer 7, both sides of the trench 4 are formed with the P well 2, the N well 5 is formed in the P well 2, and the N well 5 and the P well 2 are sequentially arranged along the front-to-back direction of the substrate 1.

[0115] The thickness of the gate oxide layer 6 in the trench gate structure 200 is different from the thickness of the gate oxide layer 6 in the planar gate structure 100, so that the threshold voltage is different, and the switching characteristics of the device can be improved.

[0116] The trench 4 is formed by etching, the depth of the trench 4 is 1-10 um, and the side wall angle is 85°-95°, which is selected according to the design requirements of the device.

[0117] The front metal 8 is a one or more layer film structure, the material of the front metal 8 is aluminum, titanium, aluminum silicon, aluminum silicon copper, titanium nitride or titanium tungsten, and the thickness of the front metal 8 is 3000-80000 angstroms, which is selected according to actual needs, and no specific requirements are made here.

[0118] The back of the substrate 1 is provided with the back metal 9, and the thickness of the back metal 9 is 800-80000 angstroms, which is selected according to actual needs, and no specific requirements are made here.

[0119] The IGBT device prepared by the above-mentioned preparation process of the IGBT device has a short circuit capability improved by more than 20%.

[0120] According to the technical scheme, the IGBT device adopts the mixed structure of the planar gate structure and the trench gate structure, the short circuit capability and the switching characteristic of the trench IGBT device are optimized, the plurality of trench gate structures are arranged on the two sides of the planar gate structure, in the planar gate structure, the gate oxide layer, the polysilicon gate, the dielectric layer and the front metal are sequentially arranged on the substrate, the P well and the N well are arranged on the two sides of the substrate, in the trench gate structure, the P well and the N well are arranged on the two sides of the outside of the trench, the gate oxide layer is arranged on the sidewall in the trench, the polysilicon gate is arranged in the trench, and the dielectric layer and the front metal are arranged on the top of the trench, so that the device can be completely compatible with the existing product manufacturing line when the device is prepared, after the trench etching, the polysilicon doping and etching are performed to form the planar gate area when the device is prepared, the P well and the N well are injected to form the planar gate structure and the trench gate structure, the higher short circuit resistance and the more optimized dynamic characteristic are achieved under the condition that the static parameters of the device are basically unchanged, the robustness of the device is improved, the thickness of the gate oxide layer of the planar gate structure and the trench gate structure is different, the threshold voltage is different, and the switching characteristic of the device can be improved.

[0121] The above describes the embodiments of the present application in detail, but the content is only the preferred embodiments of the present application, and cannot be considered as limiting the scope of the present application. Any equivalent changes and improvements made according to the scope of the present application should still belong to the scope of the present application.

Claims

1. A process for fabricating an IGBT device, characterized by: After trench etching on the substrate, polycrystalline silicon doping and etching are performed to form a planar gate region, after forming the planar gate region, P-well and N-well implantation is performed, to form a planar gate structure and a plurality of trench gate structures on the front surface of the substrate, the plurality of trench gate structures are arranged on both sides of the planar gate structure; In the trench etching step on the substrate, trench etching and gate oxidation are performed to form a trench, and a gate oxide layer is formed on the side wall and top flat part of the trench, comprising the following steps: First dielectric layer deposition: depositing a first dielectric layer on the substrate; Trench layer photoetching: coating, exposing and developing on the first dielectric layer to form a trench area; Etching the first dielectric layer to remove the first dielectric layer in the trench area; Remove the photoresist in the trench layer photoetching; Trench etching; Remove the first dielectric layer; Gate oxidation to form the gate oxide layer; In the trench etching step, the etching depth is 1um-10um, and the trench side wall angle is 85°-95°; In the step of forming the gate oxide layer by gate oxidation, the gate oxide layer is formed by thermal oxidation or CVD method, and the thickness of the gate oxide layer is 200-5000A; In the step of polycrystalline silicon doping and etching to form a planar gate region, comprising the following steps: Polycrystalline silicon deposition and doping to form a polycrystalline silicon gate; Photoetching of the polycrystalline silicon gate: coating, exposing and developing in sequence to form a planar gate region; Etching the polycrystalline silicon gate to remove the exposed polycrystalline silicon in the planar part; Remove the photoresist; In the step of polycrystalline silicon deposition and doping to form a polycrystalline silicon gate, the deposition and doping of polycrystalline silicon are performed by CVD method, the deposition thickness of polycrystalline silicon is 3000-20000A, and the doping concentration is 1E16-1E22 cm-3; The thickness of the gate oxide layer in the trench gate structure is different from the thickness of the gate oxide layer in the planar gate structure.

2. The fabrication process of an IGBT device according to claim 1, wherein: In the P-well and N-well implantation step, the P-well implantation includes the following steps: P-well implantation with a dose of 1E12-1E16 and an implantation energy of 30keV-160keV; P-well boosting to form a P-well with a certain depth, the depth range is 2um-7um.

3. The fabrication process of an IGBT device according to claim 2, wherein: After P-well boosting, N-well implantation is performed, which includes the following steps: N-well photoetching: coating, exposing and developing in sequence to form an N-well region; N-well implantation; Remove the photoresist in the N-well photoetching.

4. The fabrication process of an IGBT device according to any one of claims 1-3, characterized in that: After N-well implantation, N-well activation and hole layer etching are performed, including the following steps: Dielectric layer deposition; N-well activation; Hole layer photoetching: coating, exposing and developing in sequence to form a contact hole region; Hole layer etching: etching the contact hole region to remove the photoresist in the hole layer photoetching.

5. The fabrication process of an IGBT device according to claim 4, wherein: In the dielectric layer deposition step, the dielectric layer is deposited by thermal oxidation or CVD method, the thickness of the dielectric layer is 2000-30000A, and the material of the dielectric layer is silicon dioxide, TEOS, PSG, BPSG or silicon nitride.

6. The fabrication process of an IGBT device according to claim 5, wherein: The N well activation is performed by a furnace tube method or a rapid annealing method, the temperature is 800-1100 DEG C, and the time is 30-120 min.

7. The fabrication process of an IGBT device according to claim 4, wherein: After the hole layer is etched, metal electrode deposition is performed, the metal electrode is deposited by evaporation or sputtering, and the thickness is 3000-80000 A.

8. The fabrication process of an IGBT device according to claim 7, wherein: After the metal electrode deposition, the back of the wafer is processed, including back doping, back activation and back electrode deposition, the back doping is performed by ion implantation to dope the doping element, and the implantation energy is 30-120 keV.

9. The fabrication process of an IGBT device according to claim 8, wherein: In the back activation step, the back activation is performed by a furnace tube method, a rapid annealing method or a laser annealing method. In the back electrode deposition step, the back metal electrode is deposited by evaporation or sputtering, and the thickness is 800-80000 A.

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