Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a layer to be etched; forming a buffer layer on the layer to be etched; forming a core layer on the buffer layer, the material of the core layer being different from that of the buffer layer, and a plurality of first openings being formed in the core layer, the first openings exposing a part of the surface of the buffer layer; forming sidewalls on the sidewalls of the first openings, the material of the sidewalls being different from that of the core layer and different from that of the buffer layer; etching the buffer layer using the core layer as a mask to form second openings in the buffer layer; after forming the second openings, removing the core layer and the sidewalls; after removing the core layer and the sidewalls, etching the layer to be etched using the buffer layer as a mask. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Currently, in the back end of line (BEOL) process of semiconductor devices, when manufacturing semiconductor integrated circuits, after the semiconductor device layer is formed, a metal interconnect layer needs to be formed on the semiconductor device layer. Each metal interconnect layer includes metal interconnect lines and an inter-layer dielectric (ILD). This requires manufacturing trenches and vias in the above-mentioned inter-layer dielectric layer, and then depositing metal in the above-mentioned trenches and vias. The deposited metal is the metal interconnect line.

[0003] However, there are still some problems to be improved in the process of manufacturing trenches and vias. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an etching layer to be etched; forming a buffer layer on the etching layer to be etched; forming a core layer on the buffer layer, the material of the core layer is different from that of the buffer layer, and there are several first openings in the core layer, and the first openings expose a part of the surface of the buffer layer; forming sidewalls on the sidewalls of the first openings, the material of the sidewalls is different from that of the core layer, and the material of the sidewalls is different from that of the buffer layer; etching the buffer layer with the core layer as a mask to form a second opening in the buffer layer; after forming the second opening, removing the core layer and the sidewalls; after removing the core layer and the sidewalls, etching the etching layer to be etched with the buffer layer as a mask.

[0006] Optionally, after forming the sidewalls and before etching the buffer layer with the core layer as a mask, it further includes: forming a filling layer in the sacrificial layer or in the core layer, and the filling layer is located between adjacent sidewalls.

[0007] Optionally, the method for forming the filling layer within the sacrificial layer or the core layer includes: forming a sacrificial layer within the first opening; forming a patterned mask structure on the sacrificial layer and on the core layer, the patterned mask structure exposing a part of the core layer surface or a part of the sacrificial layer surface; etching the sacrificial layer or the core layer using the patterned mask structure as a mask to form a third opening within the sacrificial layer or the core layer, with the sidewalls exposed on both sides of the third opening; forming a filling layer within the third opening, the filling layer penetrating through the sacrificial layer along a first direction parallel to the substrate surface, or the filling layer penetrating through the core layer between adjacent first openings along a first direction parallel to the substrate surface.

[0008] Optionally, after forming the filling layer, the sacrificial layer is removed; after removing the sacrificial layer, a part of the core layer is removed to form a fourth opening within the core layer.

[0009] Optionally, the method for forming the second opening further includes: etching the buffer layer using the core layer, the sidewalls, and the filling layer as a mask until the surface of the layer to be etched is exposed to form the second opening.

[0010] Optionally, after forming the second opening, when removing the core layer and the sidewalls, it further includes: removing the filling layer.

[0011] Optionally, the method for removing the core layer, the sidewalls, and the filling layer includes a first step and a second step after the first step; the first step removes the core layer, and the process for removing the core layer includes a dry etching process or a wet etching process. The etching gas for the dry etching process includes a plasma of nitrogen trifluoride and ammonia, and the etching solution for the wet etching process includes hydrofluoric acid; the second step removes the sidewalls and the filling layer, and the process for removing the sidewalls and the filling layer includes a wet etching process, and the etching solution for the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid. Optionally, the process for removing the core layer, the sidewalls, and the filling layer includes a wet etching process, and the etching solution for the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid.

[0012] Optionally, the material of the filling layer is the same as that of the sidewalls.

[0013] Optionally, the material of the sacrificial layer is different from that of the core layer, the material of the sacrificial layer is different from that of the sidewalls, and the material of the sacrificial layer is different from that of the buffer layer.

[0014] Optionally, the material of the sacrificial layer includes silicon nitride.

[0015] Optionally, the material of the sidewalls includes an oxide of metal titanium or an oxide of metal tantalum.

[0016] Optionally, the material of the core layer includes silicon oxide.

[0017] Optionally, the material of the buffer layer includes silicon.

[0018] Optionally, the thickness range of the buffer layer is: 300 Å to 1000 Å.

[0019] Optionally, before forming the buffer layer on the layer to be etched, it further includes: forming a first stop layer on the layer to be etched; the material of the first stop layer is different from the material of the buffer layer, and the material of the first stop layer is different from the material of the core layer.

[0020] Optionally, the layer to be etched includes a substrate, and the substrate includes: a base; a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.; a conductive layer located on the device layer, the conductive layer is electrically connected to the device structure; etching the conductive layer using the buffer layer as a mask until the surface of the device layer is exposed.

[0021] Optionally, the layer to be etched further includes: a second stop layer located on the substrate; a hard mask layer located on the second stop layer; a third stop layer located on the hard mask layer; the forming method further includes: etching the first stop layer, the third stop layer, the hard mask layer, the second stop layer and the conductive layer using the buffer layer as a mask until the surface of the device layer is exposed.

[0022] Optionally, the material of the first stop layer includes silicon nitride.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure in the technical solution of the present invention, by forming a buffer layer on the layer to be etched, the material of the buffer layer is different from the material of the core layer, etching the buffer layer using the core layer as a mask, forming a second opening within the buffer layer, after forming the second opening, removing the core layer and the sidewall. After the pattern of the core layer and the sidewall is transferred to the buffer layer, removing the core layer and the sidewall, so that the material of the core layer, the material of the sidewall, and the reaction by-products generated by the material during the formation of the core layer can be removed completely, thus avoiding the situation where the material of the core layer, the material of the sidewall, and the reaction by-products generated by the material during the formation of the core layer are transferred to the layer to be etched and affect the formed semiconductor structure, thereby improving the performance of the semiconductor structure. Description of the Drawings

[0025] Figure 1 and Figure 2 is a schematic diagram of the process of forming a semiconductor structure in an embodiment;

[0026] Figures 3 to 16 It is a schematic diagram of the process of forming a semiconductor structure in an embodiment of the present invention. Detailed implementation manners

[0027] As described in the background art, the processes for manufacturing trenches and via holes still need to be improved. Now, specific embodiments will be analyzed and described.

[0028] Figure 1 and Figure 2 is a schematic diagram of the process of forming a semiconductor structure in an embodiment.

[0029] Please refer to Figure 1 , which includes: providing an etching layer 100 to be etched; forming a first stop layer 101 on the etching layer 100 to be etched; forming a hard mask layer 102 on the first stop layer 101; forming a second stop layer 103 on the hard mask layer 102; forming a core layer 104 and a plurality of openings (not shown) located in the core layer 104 on the second stop layer 103; forming sidewalls 105 on the sidewalls of the core layer 104; after forming the sidewalls 105, forming a sacrificial layer (not shown) in the openings; after forming the sacrificial layer, removing a part of the core layer 104 to form a first groove (not shown) in the core layer 104; forming a first filling layer 106 in the first groove; removing a part of the sacrificial layer to form a second groove (not shown) in the sacrificial layer; forming a second filling layer 107 in the second groove.

[0030] Please refer to Figure 2 , using the core layer 104, sidewalls 105, first filling layer 106 and second filling layer 107 as masks to etch the second stop layer 103 and the hard mask layer 102, and forming a hard mask pattern 108 on the first stop layer 101.

[0031] During the process of forming the semiconductor structure, the materials of the core layer 104, sidewalls 105, first filling layer 106 and second filling layer 107 are different from each other, and at the same time, the materials of the core layer 104, sidewalls 105, first filling layer 106 and second filling layer 107 are different from the material of the hard mask layer 102. During the process of etching to form the hard mask pattern 108, the core layer 104, sidewalls 105, first filling layer 106 and second filling layer 107 are naturally consumed during the etching process. However, since the materials of the core layer 104, sidewalls 105, first filling layer 106 and second filling layer 107 are different from the material of the hard mask layer 102, a large amount of reaction by-products 109 will remain on the hard mask pattern 108 after forming the hard mask pattern 108. Subsequently, when the etching layer 100 to be etched is continuously etched using the hard mask pattern 108, the reaction by-products 109 remaining on the hard mask pattern 108 will also be transferred to the etching layer 100 to be etched, affecting the dimensional accuracy of the formed semiconductor structure, and further affecting the performance of the formed semiconductor structure.

[0032] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure. A buffer layer is formed on the layer to be etched. The material of the buffer layer is different from that of the core layer. The buffer layer is etched using the core layer as a mask, and a second opening is formed in the buffer layer. After the second opening is formed, the core layer and the sidewall are removed. After the patterns of the core layer and the sidewall are transferred to the buffer layer, the core layer and the sidewall are removed, so that the material of the core layer, the material of the sidewall, and the reaction by-products generated by the materials during the formation of the core layer can be removed completely, thereby avoiding the situation that the material of the core layer, the material of the sidewall, and the reaction by-products generated by the materials during the formation of the core layer are transferred to the layer to be etched and affect the formed semiconductor structure, and thus improving the performance of the semiconductor structure.

[0033] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0034] Figures 3 to 16 It is a schematic diagram of the process of forming a semiconductor structure in an embodiment of the present invention.

[0035] Please refer to Figure 3 , and a layer to be etched is provided.

[0036] The layer to be etched includes a substrate 200, and the substrate 200 includes: a base (not shown); a device layer (not shown) located on the base. The device layer includes an isolation structure and a device structure located within the isolation structure. The device structure includes a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure, etc.; a conductive layer (not shown) located on the device layer, and the conductive layer is electrically connected to the device structure.

[0037] In this embodiment, the material of the base is silicon.

[0038] In other embodiments, the material of the base includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0039] In this embodiment, the layer to be etched further includes: a second stop layer 201 located on the substrate 200; a hard mask layer 202 located on the second stop layer 201; a third stop layer 203 located on the hard mask layer 202.

[0040] The material of the second stop layer 201 is different from that of the hard mask layer 202; the material of the hard mask layer 202 is different from that of the third stop layer 203.

[0041] The second stop layer 201 is an etch stop layer for subsequent etching of the hard mask layer 202; the third stop layer 203 is used to transition between the hard mask layer 202 and the first stop layer 204 formed subsequently on the third stop layer 203, to avoid a large stress gap between the first stop layer 204 and the hard mask layer 202, and a poor bonding force due to direct contact between the first stop layer 204 and the hard mask layer 202.

[0042] In this embodiment, the material of the second stop layer 201 includes silicon oxide; the material of the hard mask layer 202 includes titanium nitride, titanium oxide, tantalum nitride, or tantalum oxide; the material of the third stop layer 203 includes silicon oxide.

[0043] Please refer to Figure 4 , and form a first stop layer 204 on the layer to be etched.

[0044] The material of the first stop layer 204 is different from that of the subsequently formed buffer layer, and the material of the first stop layer 204 is different from that of the subsequently formed core layer.

[0045] The first stop layer 204 is an etch stop layer for the subsequently formed buffer layer.

[0046] In this embodiment, the material of the first stop layer 204 includes silicon nitride.

[0047] Please continue to refer to Figure 4 , and form a buffer layer 205 on the first stop layer 204.

[0048] In this embodiment, the material of the buffer layer 205 includes silicon. The process for forming the buffer layer 205 includes chemical vapor deposition or atomic layer deposition.

[0049] In this embodiment, the thickness range of the buffer layer 205 is: 300 Å to 1000 Å.

[0050] The buffer layer 205 serves as a mask for subsequent etching of the layer to be etched after removing the core layer and the sidewall. If the thickness of the buffer layer 205 is too thin, it cannot effectively block the damage of the etching process when removing the core layer and the sidewall. If the thickness of the buffer layer 205 is too thick, it will cause an increase in the aspect ratio of the second opening formed subsequently in the buffer layer 205, which is not conducive to pattern transfer.

[0051] The material of the buffer layer 205 is different from the material of the subsequently formed core layer and the material of the subsequently formed sidewall. Thus, when the core layer and the sidewall are removed later, the removal process can cause less damage to the buffer layer 205, so that the pattern of the semiconductor structure can be continuously transferred from the buffer layer 205.

[0052] Please refer to Figure 5 and Figure 6 , Figure 5 is Figure 6 a schematic cross-sectional structure diagram along the direction of the section line AA1. Figure 6 is Figure 5 a top view of. A core layer 206 is formed on the buffer layer 205. The material of the core layer 206 is different from the material of the buffer layer 205. A plurality of first openings 207 are formed in the core layer 206, and the first openings 207 expose a part of the surface of the buffer layer 205.

[0053] The forming method of the first opening 207 includes: forming a core material layer (not shown) on the buffer layer 205; forming a patterned first mask layer (not shown) on the core material layer; etching the core material layer using the patterned first mask layer as a mask until the surface of the buffer layer 205 is exposed, to form the core layer 206 and the first openings 207 located in the core layer 206.

[0054] The material of the core layer 206 is different from the material of the buffer layer 205 and the material of the subsequently formed sidewall. The material of the core layer 206 is different from the material of the buffer layer 205, so that when etching the core material layer, the etching process can stop at the buffer layer 205.

[0055] In this embodiment, the material of the core layer 206 includes silicon oxide.

[0056] Please refer to Figure 7 and Figure 8 , Figure 7 is Figure 8 a schematic cross-sectional structure diagram along the direction of the section line BB1. Figure 8 is Figure 7 a top view of. Sidewalls 208 are formed on the sidewalls of the first openings 207. The material of the sidewalls 208 is different from the material of the core layer 206 and the material of the buffer layer 205.

[0057] The forming method of the sidewall 208 includes: forming a sidewall material layer (not shown) on the bottom surface and sidewall surface of the first opening 207 and the top surface of the core layer 206; back-etching the sidewall material layer until the surface of the core layer 206 and the surface of the buffer layer 205 at the bottom of the first opening 207 are exposed, thereby forming the sidewall 208.

[0058] In this embodiment, the material of the sidewall 208 includes titanium oxide or tantalum oxide.

[0059] Please continue to refer to Figure 7 and Figure 8 , after forming the sidewall 208, a sacrificial layer 209 is formed in the first opening 207.

[0060] The forming method of the sacrificial layer 209 includes: forming a sacrificial material layer (not shown) in the first opening 207 and on the core layer 206; planarizing the sacrificial material layer until the surface of the core layer 206 is exposed, thereby forming the sacrificial layer 209 in the first opening 207.

[0061] The material of the sacrificial layer 209 is different from that of the core layer 206, the material of the sacrificial layer 209 is different from that of the sidewall 209, and the material of the sacrificial layer 209 is different from that of the buffer layer 205. Thus, when the sacrificial layer 209 is removed subsequently, the removal process can cause less damage to the core layer 206, the sidewall 209, and the buffer layer 205.

[0062] In this embodiment, the material of the sacrificial layer 209 includes silicon nitride.

[0063] Please refer to Figure 9 and Figure 10 , Figure 9 is Figure 10 a schematic cross-sectional structure diagram along the direction of the section line CC1, Figure 10 is Figure 9 a top view of, a filling layer 210 is formed in the sacrificial layer 209 and the core layer 206, and the filling layer 210 is located between adjacent sidewalls 208.

[0064] In this embodiment, the filling layer 210 is located in the sacrificial layer 209 and the core layer 206. One filling layer 210 penetrates the sacrificial layer 209 along a first direction Y parallel to the substrate surface, and one filling layer 210 penetrates the core layer 206 between adjacent first openings 207 along the first direction Y.

[0065] In other embodiments, the filling layer penetrates the sacrificial layer along a first direction Y parallel to the substrate surface, or the filling layer penetrates the core layer between adjacent first openings along the first direction Y.

[0066] The method for forming the filling layer 210 within the sacrificial layer 209 includes: forming a patterned mask structure (not shown) on the sacrificial layer 209 and on the core layer 206, the patterned mask structure exposing a part of the surface of the sacrificial layer 209; etching the sacrificial layer 209 using the patterned mask structure as a mask to form a third opening (not shown) within the sacrificial layer 209, with the sidewalls 208 exposed on both sides of the third opening; forming a filling material layer (not shown) within the third opening; planarizing the filling material layer until the surface of the sacrificial layer 209 is exposed, thereby forming the filling layer 210 within the sacrificial layer 209.

[0067] The method for forming the filling layer 210 within the core layer 206 includes: forming a patterned mask structure (not shown) on the sacrificial layer 209 and on the core layer 206, the patterned mask structure exposing a part of the surface of the core layer 206; etching the core layer 206 using the patterned mask structure as a mask to form a third opening (not shown) within the core layer 206, with the sidewalls 208 exposed on both sides of the third opening; forming a filling material layer (not shown) within the third opening; planarizing the filling material layer until the surface of the core layer 206 is exposed, thereby forming the filling layer 210 within the core layer 206.

[0068] The material of the filling layer 210 is the same as that of the sidewall 208, that is, the material of the filling layer 210 is different from that of the sacrificial layer 209 and different from that of the core layer 206. Thus, when the sacrificial layer 209 is removed subsequently, the damage to the filling layer 210 is relatively small.

[0069] In this embodiment, the material of the filling layer 210 includes titanium oxide or tantalum oxide.

[0070] Please refer to Figure 11 and Figure 12 , Figure 11 is Figure 12 a schematic cross-sectional structure diagram along the direction of the section line DD1, Figure 12 is Figure 11 a top view of, after forming the filling layer 210, removing the sacrificial layer 209 to expose the first opening 207.

[0071] The process for removing the sacrificial layer 209 includes a dry etching process or a wet etching process.

[0072] The material of the sacrificial layer 209 is different from that of the core layer 206, different from that of the sidewall 209, and different from that of the buffer layer 205. Thus, when the sacrificial layer 209 is removed, the removal process can cause relatively little damage to the core layer 206, the sidewall 209, and the buffer layer 205.

[0073] Please continue to refer to Figure 11 and Figure 12 After removing the sacrificial layer 209, a part of the core layer 206 is removed, and a fourth opening 211 is formed in the core layer 206. The fourth opening 211 is located between two adjacent first openings 207, and exposes the sidewall 208 of the sidewall of the first opening 207 and the filling layer 210 in the core layer 206.

[0074] The method for removing a part of the core layer 206 includes: forming a patterned second mask layer (not shown) on the core layer 206, and the patterned second mask layer exposes a part of the surface of the core layer 206; etching the core layer 206 using the patterned second mask layer as a mask until the surface of the buffer layer 205 is exposed, and a fourth opening 211 is formed in the core layer 206.

[0075] The process of etching the core layer 206 includes a dry etching process or a wet etching process.

[0076] The material of the core layer 206 is different from that of the buffer layer 205, the material of the core layer 206 is different from that of the sidewall 208, and the material of the core layer 206 is different from that of the filling layer 210. Therefore, when etching the core layer 206, the etching process can stop on the buffer layer 205, and at the same time, the damage to the buffer layer 205, the sidewall 208 and the filling layer 210 is small, avoiding affecting the dimensional accuracy of the formed semiconductor structure pattern.

[0077] Please refer to Figure 13 and Figure 14 , Figure 13 For Figure 14 is a schematic cross-sectional structure diagram along the section line EE1, Figure 14 For Figure 13 is a top view of. After forming the fourth opening 211, the buffer layer 205 is etched using the core layer 206, the sidewall 208 and the filling layer 210 as masks until the surface of the first stop layer 205 is exposed, and a second opening 212 is formed in the buffer layer 205.

[0078] The process of etching the buffer layer 205 includes a dry etching process, and the dry etching process can form a pattern of a semiconductor structure with better sidewall morphology and higher dimensional accuracy, which is beneficial to the subsequent transfer of the semiconductor structure pattern.

[0079] Please refer to Figure 15 and Figure 16 , Figure 15 For Figure 16 is a schematic cross-sectional structure diagram along the section line FF1, Figure 16 For Figure 15In the top view, after forming the second opening 212, the core layer 206 and the sidewall 208 are removed.

[0080] In this embodiment, when removing the core layer 206 and the sidewall 208, it further includes: removing the filling layer 210.

[0081] In this embodiment, the method for removing the core layer 206, the sidewall 208, and the filling layer 210 includes a first step and a second step after the first step. The first step removes the core layer 206, and the second step removes the sidewall 208 and the filling layer 210.

[0082] The process for removing the core layer 206 includes a dry etching process or a wet etching process. The etching gas for the dry etching process includes plasma of nitrogen trifluoride or ammonia gas, and the etching solution for the wet etching process includes hydrofluoric acid. The etching rate of the process for removing the core layer 206 on the core layer 206 is greater than that on the buffer layer 205.

[0083] The process for removing the sidewall 208 and the filling layer 210 includes a wet etching process. The etching solution for the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid. The etching rate of the process for removing the sidewall 208 and the filling layer 210 on the sidewall 208 and the filling layer 210 is greater than that on the buffer layer 205.

[0084] The materials of the core layer 206 are different from those of the sidewall 208 and the filling layer 210. First, the core layer 206 is removed, and then the sidewall 208 and the filling layer 210 are removed by a wet etching process, so as to overcome the situation of the etching rate difference caused by the different materials of the core layer 206 and the sidewall 208 and the filling layer 210, so that the core layer 206, the sidewall 208, and the filling layer 210 can be removed cleanly, and the residue on the buffer layer 205 can be minimized.

[0085] In another embodiment, the process for removing the core layer, the sidewall, and the filling layer includes a wet etching process. The etching solution for the wet etching process includes a mixed solution of hydrogen peroxide and hydrofluoric acid. The wet etching process can remove the core layer, the sidewall, and the filling layer together, so as to save the process flow and improve the production efficiency.

[0086] After the patterns of the core layer 206, sidewall 208, and filling layer 210 are transferred to the buffer layer 205, the core layer 206, sidewall 208, and filling layer 210 are removed, so that the material of the core layer 206, the material of the sidewall 208, and the reaction by-products generated by the material during the formation of the core layer 206 can be removed completely, thereby avoiding the situation that the material of the core layer 206, the material of the sidewall 208, and the reaction by-products generated by the material during the formation of the core layer 206 are transferred to the layer to be etched and affect the formed semiconductor structure, and thus the dimensional accuracy of the semiconductor structure can be improved, and the performance of the semiconductor structure is improved.

[0087] After removing the core layer 206, sidewall 208, and filling layer 210, the layer to be etched is etched using the buffer layer 205 as a mask.

[0088] The method of etching the layer to be etched using the buffer layer 205 as a mask includes: etching the first stop layer 204, third stop layer 203, hard mask layer 202, second stop layer 201, and conductive layer using the buffer layer 205 as a mask until the surface of the device layer is exposed.

[0089] The process of etching the layer to be etched using the buffer layer 205 as a mask includes a dry etching process, and the dry etching process can form a semiconductor structure with a better sidewall morphology and higher dimensional accuracy, thereby improving the performance of the semiconductor structure.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a layer to be etched; Forming a buffer layer on the layer to be etched; Forming a core layer on the buffer layer, the material of the core layer being different from that of the buffer layer, and having a plurality of first openings in the core layer, the first openings exposing a part of the buffer layer surface; Forming sidewalls on the sidewalls of the first openings, the material of the sidewalls being different from that of the core layer and different from that of the buffer layer; Forming a sacrificial layer in the first openings; Forming a filling layer in the sacrificial layer or in the core layer, the filling layer being located between adjacent sidewalls; Etching the buffer layer using the core layer, sidewalls and filling layer as a mask to form second openings in the buffer layer; After forming the second openings, removing the filling layer, core layer and sidewalls; After removing the filling layer, core layer and sidewalls, etching the layer to be etched using the buffer layer as a mask.

2. The method for forming a semiconductor structure according to claim 1, wherein The method of forming a filling layer in the sacrificial layer or in the core layer includes: forming a patterned mask structure on the sacrificial layer and on the core layer, the patterned mask structure exposing a part of the core layer surface or a part of the sacrificial layer surface; etching the sacrificial layer or the core layer using the patterned mask structure as a mask to form third openings in the sacrificial layer or in the core layer, both sides of the third openings exposing the sidewalls; forming a filling layer in the third openings, the filling layer penetrating the sacrificial layer along a first direction parallel to the substrate surface, or the filling layer penetrating the core layer between adjacent first openings along a first direction parallel to the substrate surface.

3. The method for forming a semiconductor structure according to claim 1, wherein, After forming the filling layer, removing the sacrificial layer; after removing the sacrificial layer, removing a part of the core layer to form fourth openings in the core layer.

4. The method for forming a semiconductor structure according to claim 1, wherein The method of removing the core layer, sidewalls and filling layer includes a first step and a second step after the first step; the first step removes the core layer, and the process of removing the core layer includes a dry etching process or a wet etching process, the etching gas of the dry etching process including a plasma of nitrogen trifluoride and ammonia, and the etching solution of the wet etching process including hydrofluoric acid; the second step removes the sidewalls and the filling layer, and the process of removing the sidewalls and the filling layer includes a wet etching process, the etching solution of the wet etching process including a mixed solution of hydrogen peroxide and hydrofluoric acid.

5. The method for forming a semiconductor structure according to claim 1, wherein, The process of removing the core layer, sidewalls and filling layer includes a wet etching process, the etching solution of the wet etching process including a mixed solution of hydrogen peroxide and hydrofluoric acid.

6. The method for forming a semiconductor structure according to claim 1, wherein, The material of the filling layer is the same as that of the sidewalls.

7. The method for forming a semiconductor structure according to claim 2, wherein, The material of the sacrificial layer is different from that of the core layer, different from that of the sidewalls, and different from that of the buffer layer.

8. The method for forming a semiconductor structure according to claim 7, wherein The material of the sacrificial layer includes silicon nitride.

9. The method for forming a semiconductor structure according to claim 1, wherein, The material of the sidewalls includes an oxide of metal titanium or an oxide of metal tantalum.

10. The method for forming a semiconductor structure as claimed in claim 1, wherein, The material of the core layer includes silicon oxide.

11. The method for forming a semiconductor structure according to claim 1, wherein, The material of the buffer layer includes silicon.

12. The method for forming a semiconductor structure according to claim 1, wherein, The thickness range of the buffer layer is: 300 Å to 1000 Å.

13. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the buffer layer on the layer to be etched, further comprising: forming a first stop layer on the layer to be etched; the material of the first stop layer being different from that of the buffer layer and different from that of the core layer.

14. The method for forming a semiconductor structure according to claim 13, wherein The layer to be etched includes a substrate, and the substrate includes: a base; a device layer located on the base, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a diode, a triode, a capacitor or an inductor; a conductive layer located on the device layer, the conductive layer being electrically connected to the device structure; etching the conductive layer using the buffer layer as a mask until the surface of the device layer is exposed.

15. The method for forming a semiconductor structure according to claim 14, wherein The layer to be etched further includes: a second stop layer located on the substrate; a hard mask layer located on the second stop layer; a third stop layer located on the hard mask layer; the forming method further includes: etching the first stop layer, the third stop layer, the hard mask layer, the second stop layer and the conductive layer using the buffer layer as a mask until the surface of the device layer is exposed.

16. The method for forming a semiconductor structure as described in claim 13, wherein, The material of the first stop layer includes silicon nitride.

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