Chip units and 3D chips

Abstract

The embodiments of the present application provide a chip unit and a 3D chip, wherein the chip unit includes: a substrate layer; a metal layer, the metal layer including a first surface and a second surface arranged opposite to each other, the second surface of the metal layer being arranged on the substrate layer; a metal layer through-hole assembly arranged in the metal layer, the metal layer through-hole assembly including: a first conductor, a second conductor, and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed in the metal layer, the second conductor being connected to the first conductor via the conductor connection hole; a substrate through-hole, provided in the substrate layer and connected to the second conductor; and an inter-chip connection hole, connected to the first conductor and / or the second conductor. The chip unit reduces the difficulty of etching process, reduces the area occupied by the metal layer, reduces the resistance parasitic parameters and the capacitance parasitic parameters, shortens the preparation cycle of the chip unit, and reduces production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip unit and a 3D chip. Background Art

[0002] With the advancement of chip technology and the increasing demand for information technology, 3D chips are increasingly appearing in the integrated circuit industry. 3D chips can consist of multiple chip units stacked together. Due to signal transmission requirements, signal connections in 3D chips must pass through the chip units that make up the 3D chip. These signal connections are achieved through the entire chip from the front to the back using perforations, currently primarily achieved using through-silicon vias (TSVs).

[0003] Because TSVs must penetrate the entire chip, not only through the various materials that make up the stacked circuits but also through the very thick silicon substrate, they place high demands on the etching technology used to create the vias. Furthermore, the TSVs are large in diameter and length, resulting in a significant increase in chip area, high parasitic resistance and capacitance parameters, a long manufacturing cycle, and high costs. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0005] In view of this, according to the first aspect of an embodiment of the present application, a chip unit is proposed, comprising: a substrate layer; a metal layer, the metal layer comprising a first surface and a second surface arranged opposite to each other, the second surface of the metal layer being arranged on the substrate layer; a metal layer through-hole component, arranged in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor and a conductor connection hole, the first conductor being formed on the first surface of the metal layer, the second conductor being formed on the second surface of the metal layer, the conductor connection hole being formed in the metal layer, the second conductor being connected to the first conductor through the conductor connection hole, so that the signal can be transmitted to the first surface through the substrate layer; a substrate through-hole, opened on the substrate layer and connected to the second conductor; and an inter-chip connection hole, connected to the first conductor and / or the second conductor.

[0006] In a first possible implementation manner of the first aspect, the inter-chip connection hole includes: a conductor through-hole, and the conductor through-hole is connected to the first conductor component and / or the second conductor component.

[0007] In a second possible implementation manner of the first aspect, the conductor via is obtained through the first conductor member and / or the second conductor member by intermetallic growth.

[0008] In a third possible implementation of the first aspect, the inter-sheet connection holes are columnar.

[0009] In a fourth possible implementation of the first aspect, the inter-chip connection holes are used to connect metal layers of other chips.

[0010] In a fifth possible implementation of the first aspect, the inter-chip connection hole is used to connect to another chip unit.

[0011] In a sixth possible implementation manner of the first aspect, the inter-chip connection via is used to connect the first conductor and / or the second conductor of another chip unit.

[0012] In a seventh possible implementation of the first aspect, the inter-chip connection via is used to connect to an inter-chip connection via of another chip unit.

[0013] In an eighth possible implementation of the first aspect, the chip unit further includes: a conductive dielectric filling layer filled in the substrate through-hole.

[0014] In a ninth possible implementation of the first aspect, the inter-sheet connection hole is connected to the second conductor member through a conductor dielectric filling layer.

[0015] In a tenth possible implementation of the first aspect, the chip unit further includes: a lead, which is connected to the second conductor when the inter-chip connection hole is connected to the first conductor, and is connected to the first conductor when the lead connection hole is connected to the second conductor.

[0016] In an eleventh possible implementation of the first aspect, the chip unit further includes: a substrate conductor part, arranged in the substrate layer; the substrate through hole includes a bottom through hole and an intermediate connecting hole, the bottom through hole is opened at the bottom of the substrate and connected to the substrate conductor part, the intermediate connecting hole is located between the substrate conductor part and the second conductor part, and the substrate conductor part is connected to the second conductor part through the intermediate connecting hole.

[0017] In a twelfth possible implementation manner of the first aspect, the middle connecting hole is processed along the direction from the first surface to the substrate layer.

[0018] In a thirteenth possible implementation manner of the first aspect, the inter-chip connection via is connected to the second conductor component through the substrate conductor component.

[0019] In the fourteenth possible implementation of the first aspect, the metal layer through-hole assembly further includes: an on-chip conductor part, located between the first conductor part and the second conductor part; wherein, there are multiple conductor connection holes, the second conductor part is connected to the on-chip conductor part through some of the multiple conductor connection holes, and the on-chip conductor part is connected to the first conductor part through some of the multiple conductor connection holes.

[0020] In a fifteenth possible implementation of the first aspect, there are multiple on-chip conductor parts, and the multiple on-chip conductor parts are arranged at intervals between the first conductor part and the second conductor part, and adjacent on-chip conductor parts are connected through some of the multiple conductor connection holes.

[0021] In a sixteenth possible implementation of the first aspect, a conductor connection hole is provided between two adjacent on-chip conductor parts.

[0022] In a seventeenth possible implementation manner of the first aspect, a conductor connection hole is provided between the first conductor component and an adjacent on-chip conductor component.

[0023] In an eighteenth possible implementation manner of the first aspect, a conductor connection hole is provided between the second conductor component and an adjacent on-chip conductor component.

[0024] In a nineteenth possible implementation manner of the first aspect, a difference between the number of the conductor connection holes and the number of the conductor connection pieces is 1.

[0025] In a twentieth possible implementation of the first aspect, a cross-section of the substrate through hole along the substrate height direction is a polygon, and a length of a first side of the polygon close to the metal layer is less than a length of a second long side of the polygon away from the metal layer.

[0026] In a twenty-first possible implementation manner of the first aspect, a cross-section of the substrate through-hole along a height direction of the substrate is trapezoidal.

[0027] In a twenty-second possible implementation of the first aspect, the short side of the trapezoid is located on a side of the substrate layer close to the metal layer, and the long side of the trapezoid is located on a side of the substrate layer far from the metal layer.

[0028] In a twenty-third possible implementation of the first aspect, the substrate through hole is truncated cone-shaped.

[0029] In the twenty-fourth possible implementation of the first aspect, the frustum includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer close to the metal layer, and the second end face is located on the side of the substrate layer away from the metal layer.

[0030] In a twenty-fifth possible implementation of the first aspect, the conductor connection hole is columnar.

[0031] According to a second aspect of an embodiment of the present application, a 3D chip is provided, comprising: a chip unit according to any of the above technical solutions.

[0032] In a first possible implementation of the second aspect, the 3D chip further includes: an end chip, wherein the substrate layer of the end chip has not been subjected to a hole-digging process; the chip unit and the end chip are stacked, and the chip unit is connected to the metal layer of the end chip through an inter-chip connection hole.

[0033] In a second possible implementation manner of the second aspect, the end chip further includes an end chip connection hole, and the metal layer of the end chip is connected to the inter-chip connection hole through the end chip connection hole.

[0034] In a third possible implementation manner of the second aspect, the end chip connection holes and the inter-chip connection holes have the same or corresponding shapes.

[0035] In a fourth possible implementation manner of the second aspect, the end chip connection holes and the inter-chip connection holes have the same cross-sectional shape.

[0036] In a fifth possible implementation of the second aspect, the 3D chip includes: at least two stacked chip units; and two adjacent chip units of the at least two chip units are connected via an inter-chip connection hole.

[0037] In a sixth possible implementation of the second aspect, two adjacent chip units in the at least two chip units are connected through a same inter-chip connection hole.

[0038] In a seventh possible implementation of the second aspect, the inter-chip connection holes of two adjacent chip units in the at least two chip units are connected.

[0039] In an eighth possible implementation manner of the second aspect, shapes of the two inter-chip connection holes of two adjacent chip units are the same or corresponding.

[0040] In a ninth possible implementation of the second aspect, the cross-sectional shapes of the two inter-chip connection holes of two adjacent chip units are the same.

[0041] In a tenth possible implementation manner of the second aspect, two adjacent chip units are arranged in the same direction, and the first conductor on one of the two adjacent chip units is connected to the second conductor on the other chip unit through an inter-chip connection hole.

[0042] In an eleventh possible implementation manner of the second aspect, two adjacent chip units are arranged facing each other, and the first conductors of the two adjacent chip units are connected through an inter-chip connection hole.

[0043] In a twelfth possible implementation manner of the second aspect, two adjacent chip units are arranged facing each other, and the second conductor members of the two adjacent chip units are connected through an inter-chip connection hole.

[0044] In a thirteenth possible implementation manner of the second aspect, two adjacent chip units are arranged facing each other, and substrate conductor parts of the two adjacent chip units are connected through an inter-chip connection hole.

[0045] In a fourteenth possible implementation manner of the second aspect, two adjacent chip units are arranged in the same direction, and the substrate conductor on one of the two adjacent chip units is connected to the first conductor on the other chip unit through an inter-chip connection hole.

[0046] Compared with the prior art, the present invention has at least the following beneficial effects:

[0047] (1) The chip unit provided in the embodiment of the present application has a substrate through-hole formed in the substrate layer; a first conductor is formed on the first surface of the metal layer, and a second conductor is formed on the second surface of the metal layer, and the first conductor and the second conductor are connected through a conductor connection hole in the metal layer; the second surface of the metal layer is disposed on the substrate layer, and the substrate through-hole is connected to the second conductor. During operation of the chip unit, the signal access terminal can be disposed in the substrate through-hole and connected to the second conductor, and the signal can be transmitted to the first conductor through the conductor connection hole; the signal access terminal can also be connected to the first conductor, connected to the second conductor through the conductor connection hole, and then the signal is output through the substrate through-hole. This arrangement allows the signal to pass through the chip unit to produce a 3D chip and realize the functions of the 3D chip. The chip unit provided in the embodiment of the present application realizes signal transmission through the chip unit by sequentially connecting the first conductor part, the conductor connection hole, and the second conductor part from the top to the bottom of the chip unit. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole on the substrate and form a conductor connection hole in the metal layer to realize signal transmission through the chip unit. This greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit, and reducing production costs.

[0048] (2) In the chip unit provided in the embodiment of the present application, the inter-chip connection holes are connected to the first conductor and / or the second conductor, and the first conductor and the second conductor are connected through the conductor connection holes. Thus, the inter-chip connection holes can be used to input signals into the metal layer, to lead out signals from the metal layer through the inter-chip connection holes, and to transmit external signals through the substrate layer and the metal layer. This allows the chip unit to lead out the inter-chip connection holes through the front side of the chip unit and / or the back side of the chip unit, making the signal input and output of the chip unit more flexible, and in particular, can reduce the area of the front side of the chip unit occupied by the inter-chip connection holes, making the layout and arrangement of the leads simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which:

[0050] Figure 1 is a schematic structural diagram of a chip in an example;

[0051] Figure 2 A schematic structural diagram of a chip unit according to the first embodiment of the present application;

[0052] Figure 3 A schematic structural diagram of a chip unit according to a second embodiment of the present application;

[0053] Figure 4 A schematic structural diagram of a chip unit according to a third embodiment of the present application;

[0054] Figure 5 A schematic structural diagram of a chip unit according to a fourth embodiment of the present application;

[0055] Figure 6 A schematic structural diagram of a chip unit according to a fifth embodiment of the present application;

[0056] Figure 7 A schematic structural diagram of a chip unit according to a sixth embodiment of the present application;

[0057] Figure 8 A schematic structural diagram of a chip unit according to a seventh embodiment of the present application;

[0058] Figure 9 A schematic structural diagram of a chip unit according to an eighth embodiment of the present application;

[0059] Figure 10 This is a schematic structural diagram of a 3D chip according to the first embodiment of the present application;

[0060] Figure 11 This is a schematic structural diagram of a 3D chip according to the second embodiment of the present application;

[0061] Figure 12 A schematic structural diagram of a 3D chip according to a third embodiment of the present application;

[0062] Figure 13 A schematic structural diagram of a 3D chip according to a fourth embodiment of the present application;

[0063] Figure 14 A schematic structural diagram of a 3D chip according to a fifth embodiment of the present application;

[0064] Figure 15 This is a schematic structural diagram of a 3D chip according to a sixth embodiment of the present application;

[0065] Figure 16 This is a schematic structural diagram of a 3D chip according to a seventh embodiment of the present application;

[0066] Figure 17 This is a schematic structural diagram of a 3D chip according to an eighth embodiment of the present application;

[0067] Figure 18 This is a schematic structural diagram of a 3D chip according to a ninth embodiment of the present application;

[0068] Figure 19 This is a schematic structural diagram of a 3D chip according to a tenth embodiment of the present application;

[0069] Figure 20 This is a schematic structural diagram of a 3D chip according to the eleventh embodiment of the present application.

[0070] in, Figures 1 to 20 The corresponding relationship between the reference numerals and component names is as follows:

[0071] 100' through silicon via, 200' metal layer, 300' substrate layer;

[0072] 100 chip units, 200 end chips;

[0073] 1 substrate layer, 2 metal layer, 3 first conductor, 4 second conductor, 5 substrate through hole, 6 conductor connection hole, 7 intra-chip conductor, 8 substrate conductor, 10 lead, 11 metal filling layer, 12 conductor dielectric filling layer, 14 metal layer through-hole component, 15 inter-chip connection hole, 16 end chip connection hole;

[0074] 501 bottom through hole, 502 middle connecting hole;

[0075] 601 first through hole, 602 second through hole, 60N Nth through hole;

[0076] 701 is the first internal conductor, 702 is the second internal conductor, and 70M is the Mth internal conductor. DETAILED DESCRIPTION

[0077] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0078] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0079] like Figure 1 As shown, in some examples, signal transmission through the chip unit can be achieved by opening a through-silicon via 100' (TSV) that penetrates the metal layer 200' and the substrate layer 300'. However, because the TSV 100' needs to pass through the entire chip unit, the diameter and length (or height) of the TSV 100' are relatively large, which may lead to problems such as high etching technology requirements, a very large chip area, large resistance parasitic parameters and capacitance parasitic parameters, a long manufacturing cycle, and high cost.

[0080] In response to the above problems, an embodiment of the present application provides a chip unit that solves the problems of the chip through-hole structure having high requirements for etching technology, occupying a very large chip area, large resistance parasitic parameters and capacitance parasitic parameters, a long manufacturing cycle and high cost.

[0081] like Figures 2 to 9 As shown, an embodiment of the present invention provides a chip unit, including: a substrate layer 1 , a metal layer 2 , a metal layer through-hole component 14 and a substrate through-hole 5 .

[0082] Among them, the metal layer 2 includes a first surface and a second surface arranged opposite to each other, and the second surface of the metal layer 2 is arranged on the substrate layer 1; the metal layer perforation component 14 is arranged in the metal layer 2, and the metal layer perforation component 14 includes: a first conductor 3, a second conductor 4 and a conductor connection hole 6, the first conductor 3 is formed on the first surface of the metal layer 2, the second conductor 4 is formed on the second surface of the metal layer 2, the conductor connection hole 6 is formed in the metal layer 2, and the second conductor 4 is connected to the first conductor 3 through the conductor connection hole 6, so that the signal can be transmitted to the first surface through the substrate layer 1; the substrate through hole 5 is opened on the substrate layer 1 and connected to the second conductor 4; the inter-sheet connection hole 15 is connected to the first conductor 3 and / or the second conductor 4. It should be noted here that the metal layer 2 refers to the part above the substrate layer 1; the second surface of the metal layer 2 refers to the side close to the substrate layer 1, and the first surface of the metal layer 2 refers to the side away from the substrate layer 1, and the following parts are the same.

[0083] like Figure 2 As shown, the inter-sheet connection hole 15 is connected to the first conductor 3; Figure 3 As shown, the inter-sheet connection hole 15 is connected to the second conductor 4; Figure 4 As shown, the inter-chip connection holes 15 are connected to the first conductive component 3 and the second conductive component 4 .

[0084] In the chip unit 100 provided in the embodiment of the present application, during operation, the signal access end can be set in the substrate through hole 5 and connected to the second conductor part 4, and the signal can be transmitted to the first conductor part 3 through the conductor connection hole 6; based on the same principle, the signal access end can also be connected to the first conductor part 3, connected to the second conductor part 4 through the conductor connection hole 6, and then the signal is output through the substrate through hole 5. This setting allows the signal to pass through the chip unit 100, facilitating the formation and construction of the 3D chip.

[0085] The chip unit 100 provided in the embodiment of the present application realizes signal passing through the chip unit 100 by sequentially connecting the first conductor part 3, the conductor connection hole 6, and the second conductor part 4 from the top to the bottom of the chip unit 100. There is no need to set up a through-silicon via. It is only necessary to open a substrate through hole 5 on the substrate and a metal layer perforation component 14 in the metal layer 2, which greatly reduces the diameter and length of the hole, thereby reducing the difficulty of the etching process, reducing the area occupied by the metal layer 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit 100, and reducing the production cost.

[0086] like Figures 2 to 9 As shown, in some examples, the conductor connection holes 6 can be multiple, Figures 2 to 20 The middle dot indicates the conductor connection hole 6 which is partially omitted. Figures 2 to 20 The middle conductor connection hole 6 includes a first through hole 601 , a second through hole 602 , and an Nth through hole 60N. The first conductor 3 is connected to the second conductor 4 through the first through hole 601 , the second through hole 602 , and the Nth through hole 60N in sequence.

[0087] In some examples, the chip unit 100 may be a component composed of multiple planar chips, or may be a single planar chip.

[0088] In some examples, the first conductor 3 may be a metal wire or a metal surface formed on the first surface of the metal layer 2 ; the second conductor 4 may be a metal wire or a metal surface formed on the second surface of the metal layer 2 .

[0089] In some examples, the conductor connection hole 6 may include a through hole and a connection column, wherein the through hole is opened in the metal layer 2 and the connection column is a metal column filled in the through hole. The first conductor 3 and the second conductor 4 can be connected by the metal column to achieve signal transmission.

[0090] It is understood that the thickness of the substrate layer 1 is usually greater than the thickness of the metal layer 2. Figures 2 to 9 The thickness of the middle metal layer 2 is greater than that of the substrate layer 1 in order to clearly show the internal structure of the metal layer 2 .

[0091] like Figures 2 to 9As shown, in the chip unit 100 provided in the embodiment of the present application, the inter-chip connection holes 15 are connected to the first conductor 3 and / or the second conductor 4, and the first conductor 3 and the second conductor 4 are connected via the conductor connection holes 6. In this way, the signal input into the metal layer 2 is realized through the inter-chip connection holes 15, the signal inside the metal layer 2 is led out through the inter-chip connection holes 15, and the external signal is transmitted through the substrate layer 1 and the metal layer 2. The chip unit 100 can lead out the inter-chip connection holes 15 through the front surface of the chip unit 100 and / or the back surface of the chip unit 100, making the signal input and output of the chip unit 100 more flexible, and in particular, it can reduce the area of the front surface of the chip unit 100 occupied by the inter-chip connection holes 15, save the area of the metal layer 2 on the front surface of the chip unit 100, and make the layout and arrangement of the inter-chip connection holes 15 simpler.

[0092] The front side of the chip unit 100 refers to the first surface of the metal layer 2 , and the back side of the chip unit 100 refers to the side of the substrate layer 1 facing away from the second surface.

[0093] It can be understood that during the preparation process of the chip unit 100 provided in the embodiment of the present application, an oxide layer can be formed on the first surface of the metal layer 2 or in the substrate through hole 5 of the substrate layer 1, and a groove can be formed on the oxide layer through an etching process. A metal through hole can be grown in the groove to form an inter-chip connection hole 15. After the inter-chip connection hole 15 is formed, the remaining oxide layer can be removed by an etching process, or the oxide layer can be retained to support the inter-chip connection hole 15.

[0094] It is understandable that the chip unit 100 is connected to other chips through the provision of the inter-chip connection holes 15 . The inter-chip connection holes 15 have stronger mechanical strength than traditional lead connection methods and can better support stacked chips.

[0095] In some examples, metal pillars may be formed in the inter-chip connection holes 15 , and signal transmission may be achieved by connecting to other chips through the metal pillars.

[0096] In some examples, the inter-chip connection holes 15 include: conductor through-holes, which are connected to the first conductor component 3 and / or the second conductor component 4 .

[0097] In this embodiment, the inter-chip connection holes 15 include conductor through-holes. Through the provision of the conductor through-holes, the conductor through-holes are connected to the first conductor member 3 and / or the second conductor member 4. The first conductor member 3 and the second conductor member 4 are connected via the conductor connection holes 6. In this way, the conductor through-holes enable signal input into the metal layer 2, enable signal extraction from the metal layer 2 via the conductor through-holes, and enable transmission of external signals through the substrate layer 1 and the metal layer 2. This allows the chip unit 100 to extract the conductor through-holes via the front surface of the chip unit 100 and / or the back surface of the chip unit 100, making the signal input and output of the chip unit 100 more flexible. In particular, it can reduce the area of the front surface of the chip unit 100 occupied by the conductor through-holes, save the area of the metal layer 2 on the front surface of the chip unit 100, and simplify the layout and arrangement of the conductor through-holes.

[0098] In some examples, the conductor via is obtained by metal growth through the first conductor 3 and / or the second conductor 4 . That is, the conductor via is obtained by metal growth on the first conductor 3 and / or the second conductor 4 .

[0099] In this embodiment, the conductor through-hole can be obtained through metal growth via the first conductor part 3 and / or the second conductor part 4. The obtained conductor through-hole can be used for signal transmission. At the same time, the conductor through-hole can have a certain mechanical strength and better deformation resistance than the lead connection method, and can better support the stacked chips.

[0100] like Figures 2 to 9 As shown, in some examples, the inter-chip connection holes 15 are columnar.

[0101] In this embodiment, the inter-chip connection hole 15 is columnar, and the shapes of both ends of the columnar inter-chip connection hole 15 are roughly the same, so that the inter-chip connection hole 15 transmits signals more smoothly, facilitating accurate acquisition of the chip unit 100 and accurate transmission of signals.

[0102] like Figures 10 to 20 As shown, in some examples, the inter-chip connection holes 15 are used to connect the metal layers 2 of other chips, that is, to stack planar chips to form a 3D chip.

[0103] In this embodiment, the signal passes through the chip unit 100 by sequentially connecting the first conductor part 3, the conductor connection hole 6, and the second conductor part 4 from the top to the bottom of the chip unit 100. The inter-chip connection hole 15 is connected to the metal layer 2 of other chips, so that the signal passing through the chip unit 100 can be transmitted to the metal layer 2 of other chips, thereby realizing cross-chip transmission of the signal.

[0104] In this embodiment, the inter-chip connection holes 15 are connected to the metal layer 2 of other chips. The signals generated in the metal layer 2 of the chip unit 100 can also be transmitted to the metal layer 2 of other chips through the metal layer perforation component 14 and the inter-chip connection holes 15, so that the signals generated inside the chip unit 100 can be sent to other chips, making the signal transmission more flexible and improving the performance of the chip unit 100.

[0105] like Figures 12 to 20 As shown, in some examples, the inter-chip connection via 15 is used to connect to another chip unit 100 .

[0106] In this embodiment, the two chip units 100 provided in the embodiments of the present application can be connected through the inter-chip connection holes 15, so that the two chip units 100 can communicate through the inter-chip connection holes 15, which can further improve the signal processing capability of the chip unit 100.

[0107] like Figure 10 and Figure 12 As shown, in some examples, the inter-chip connection vias 15 are used to connect the first conductor 3 and / or the second conductor 4 of another chip unit 100 .

[0108] In this embodiment, during the connection process of two chip units 100 provided in the embodiments of the present application, the same signal can share one inter-chip connection hole 15 for connection. This design method can reduce the number of inter-chip connection holes 15, improve the smoothness of signal transmission, and reduce the production cost of the chip unit 100.

[0109] like Figure 11 As shown, in some examples, the inter-chip connection via 15 is used to connect to the inter-chip connection via 15 of another chip unit 100 .

[0110] In this embodiment, the inter-chip connection holes 15 are used to connect to the inter-chip connection holes 15 of another chip unit 100 . This design can make the connection mode of the chip units 100 more flexible.

[0111] like Figure 5 As shown, in some examples, the chip unit 100 further includes: a conductor dielectric filling layer 12 filled in the substrate through hole 5 .

[0112] like Figure 5 As shown, in this embodiment, a conductive dielectric filling layer 12 is further included. The heat dissipation dielectric is filled in the substrate through-hole 5. The heat generated in the metal layer 2 can be transferred to the heat dissipation dielectric layer, and the heat can be dispersed through the heat dissipation dielectric layer. In this way, the chip unit 100 can be cooled and cooled, thereby improving the performance of the chip unit 100.

[0113] like Figure 5 As shown, in some examples, the inter-sheet connection hole 15 is connected to the second conductor member 4 through the conductor dielectric filling layer 12 .

[0114] In this embodiment, when the substrate through hole 5 is filled with a conductor dielectric filling layer 12, the inter-chip connection hole 15 can be connected to the second conductor part 4 through the conductor dielectric filling layer 12. In this way, the inter-chip connection hole 15 can be formed in the conductor dielectric filling layer 12, and the inter-chip connection hole 15 does not need to be sunken in the substrate through hole 5, which can further reduce the production cost of the chip unit 100.

[0115] like Figure 6 and Figure 7 As shown, in some examples, the chip unit 100 also includes: a lead 10, when the inter-chip connection hole 15 is connected to the first conductor part 3, the lead 10 is connected to the second conductor part 4, and when the lead 10 connection hole is connected to the second conductor part 4, the lead 10 is connected to the first conductor part 3.

[0116] In this embodiment, when the inter-chip connection hole 15 is connected to the first conductor part 3, the lead 10 is connected to the second conductor part 4. When the lead 10 connection hole is connected to the second conductor part 4, the lead 10 is connected to the first conductor part 3. The lead 10 can be used in combination with the inter-chip connection hole 15, which can enable the chip unit 100 to have a variety of signal lead-out or signal input connection methods, and can further improve the applicability of the chip unit 100.

[0117] like Figure 6 and Figure 7 As shown, in this embodiment, a metal filling layer 11 is further included. The metal filling layer 11 is arranged on the first conductor 3 or the second conductor 4. The arrangement of the metal filling layer 11 facilitates the arrangement of the lead 10, making the fixation of the lead 10 more stable.

[0118] like Figure 6 and Figure 7 As shown, in some examples, when the lead 10 is connected to the metal filling layer 11 , the lead 10 and the metal filling layer 11 constitute a pad structure.

[0119] like Figure 8 As shown, in some examples, the chip unit 100 also includes: a substrate conductor part 8 (the substrate conductor part 8 here can be similar to the buried metal in the chip manufacturing process), which is arranged in the substrate layer 1; the substrate through hole 5 includes a bottom through hole 501 and an intermediate connection hole 502, the bottom through hole 501 is opened at the bottom of the substrate and is connected to the substrate conductor part 8, the intermediate connection hole 502 is located between the substrate conductor part 8 and the second conductor part 4, and the substrate conductor part 8 is connected to the second conductor part 4 through the intermediate connection hole 502.

[0120] like Figure 8 As shown, the substrate conductor 8 is disposed in the substrate layer 1. The substrate through-hole 5 includes a bottom through-hole 501 and a middle connecting hole 502.

[0121] like Figure 8 As shown, during the operation of the chip unit 100, the signal input end can be set in the bottom through hole 501 and connected to the substrate conductor 8, which is connected to the second conductor 4 through the intermediate connection hole 502, and the second conductor 4 is connected to the first conductor 3; the signal input end can also be connected to the first conductor 3, which is connected to the second conductor 4, and the second conductor 4 is further connected to the substrate conductor 8 through the intermediate connection hole 502. This arrangement allows the signal to pass through the chip unit 100, facilitating the formation and construction of 3D chips. Even flat chips (single chip units 100) can be stacked into a 3D chip.

[0122] In some examples, the intermediate connection hole 502 is processed along the first surface toward the substrate layer 1 .

[0123] like Figure 8 As shown, the substrate conductor 8 is arranged in the substrate, dividing the substrate through hole 5 into a bottom through hole 501 and an intermediate connection hole 502. The intermediate connection hole 502 is processed along the first surface toward the substrate layer 1 to facilitate the opening of the intermediate connection hole 502. Figure 8 The substrate through hole 5 can reduce the length and diameter of the substrate through hole 5, thereby reducing the difficulty of the etching process, reducing the area of the metal layer 2 chip occupied (the plane area of the chip), reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit 100, and reducing the production cost.

[0124] It is understandable that in the entire chip unit 100, the thickness of the substrate is usually very large, so the height of the substrate through hole 5 is much greater than the height of the conductor connection hole 6. By adding a buried metal layer, the height of the bottom through hole 501 can be greatly reduced.

[0125] In this embodiment, the substrate layer 1 typically requires thinning before perforation. However, by providing the substrate conductor 8 in this embodiment, the substrate layer 1 does not need to be thinned very much, and even bottom via 501 can be processed without thinning. Furthermore, because bottom via 501 does not need to pass through the entire substrate layer 1, perforation time is reduced, costs are reduced, and perforation yield and reliability are improved.

[0126] like Figure 8As shown, the substrate through hole 5 is divided into a bottom through hole 501 and an intermediate connection hole 502 by the substrate conductor 8 , which further reduces the depth of the bottom through hole 501 and facilitates the opening of the bottom through hole 501 .

[0127] In some examples, the middle connection hole 502 may be a connection hole formed by an etching process.

[0128] In some examples, the middle connection hole 502 may include a through hole and a connection pillar disposed in the through hole, wherein the connection pillar is a metal pillar. The second conductor 4 and the substrate conductor 8 may be connected via the metal pillar.

[0129] like Figure 8 As shown, in some examples, the inter-chip connection via 15 is connected to the second conductor 4 through the substrate conductor 8 .

[0130] In this embodiment, when a substrate conductor part 8 is provided in the substrate through hole 5, the inter-chip connection hole 15 can be connected to the second conductor part 4 through the substrate conductor part 8. The inter-chip connection hole 15 is set in this way and can be formed on the substrate conductor part 8, which can reduce the sinking depth of the inter-chip connection hole 15, that is, reduce the depth of the inter-chip connection hole 15 in the substrate through hole 5 (the other parts of the text are the same), and further reduce the production cost of the chip unit 100.

[0131] like Figures 2 to 9 As shown, in some examples, the metal layer through-hole component 14 further includes: an on-chip conductor part 7, which is arranged in the metal layer 2 and is located between the first conductor part 3 and the second conductor part 4; wherein, there are multiple conductor connection holes 6, the second conductor part 4 is connected to the on-chip conductor part 7 through some of the multiple conductor connection holes 6, and the on-chip conductor part 7 is connected to the first conductor part 3 through some of the multiple conductor connection holes 6.

[0132] like Figures 2 to 9 As shown, the on-chip conductor 7 is disposed between the first conductor 3 and the second conductor 4. The second conductor 4 is connected to the on-chip conductor 7 via a conductor connection hole 6, and the on-chip conductor 7 is connected to the first conductor 3 via a conductor connection hole 6. During operation of the chip unit 100, an external signal input terminal can be disposed within the substrate through-hole 5 and transmitted to the second conductor 4. The second conductor 4 is then connected to the on-chip conductor 7 and then to the first conductor 3. Alternatively, an external signal input terminal can be connected to the first conductor 3 and then transmitted to the second conductor 4 via the conductor connection hole 6 and the on-chip conductor 7. This arrangement allows signals to pass through the chip unit 100, facilitating the formation and construction of 3D chips.

[0133] like Figures 2 to 9As shown, the on-chip conductor part 7 is arranged between the first conductor part 3 and the second conductor part 4, so that the first conductor part 3 and the second conductor part 4 can be connected to the on-chip conductor part 7 through multiple conductor connection holes 6, further shortening the length of the conductor connection hole 6, and reducing the diameter of the conductor connection hole 6, further reducing the difficulty of the etching process, reducing the area occupied by the metal layer 2, reducing the resistance parasitic parameters and the capacitance parasitic parameters, shortening the preparation cycle of the chip unit 100, and reducing the production cost.

[0134] In some examples, such as Figure 9 As shown, there may be multiple conductor connection holes 6 and multiple conductor parts 7 on the chip. Figure 9 The middle dots represent the conductor connection holes 6 and the conductor parts 7 in the chip that are partially omitted. Figure 9 The conductor connection holes 6 include a first through-hole 601, a second through-hole 602, and finally an Nth through-hole 60N. The on-chip conductive components 7 include a first on-chip conductive component 701, a second on-chip conductive component 702, and finally an Mth on-chip conductive component 70M. One side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 4 via the first through-hole 601, and the other side of the first on-chip conductive component 701 is connected to the second on-chip conductive component 702 via the second through-hole 602. This arrangement is repeated, with adjacent on-chip conductive components 7 connected via the conductor connection holes 6 until the Mth on-chip conductive component 70M is connected to the first conductive component 3 via the Nth through-hole 60N. This connects the first conductive component 3 to the second conductive component 4, enabling signal transmission through the chip unit 100. M = N-1.

[0135] In some examples, the conductor connection hole 6 may include a through-hole and a connection pillar. The through-hole is provided in the metal layer 2, and the connection pillar is a metal pillar filled in the through-hole. The first conductor 3 and the on-chip conductor 7 can be connected via the metal pillar; the second conductor 4 and the on-chip conductor 7 can be connected via the metal pillar; and adjacent on-chip conductors 7 can be connected via the metal pillar.

[0136] In some examples, the on-chip conductor 7 may be a metal line or a metal surface formed in the metal layer 2 .

[0137] It is understandable that Figures 2 to 20 The three dots in FIG. 7 represent omitted on-chip conductor parts 7 and conductor connection holes 6 .

[0138] like Figures 2 to 9 As shown, in some examples, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are arranged at intervals between the first conductor part 3 and the second conductor part 4, and adjacent on-chip conductor parts 7 are connected through some of the multiple conductor connection holes 6.

[0139] like Figures 2 to 9As shown, there are multiple on-chip conductor parts 7, and the multiple on-chip conductor parts 7 are spaced apart between the first conductor part 3 and the second conductor part 4. The second conductor part 4 is connected to the first conductor part 3 through the multiple on-chip conductor parts 7 and the multiple conductor connection holes 6, which can further shorten the length and diameter of each conductor connection hole 6, further reduce the difficulty of the etching process, reduce the area occupied by the metal layer 2, reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the chip unit 100, and reduce the production cost.

[0140] It should be noted that, in practice, the first conductor 3 , the second conductor 4 and the multiple on-chip conductors 7 are different metal layers 2 in the chip, and the conductor connection holes 6 are connection through holes between different metal layers 2 .

[0141] In some examples, a conductor connection hole 6 is provided between two adjacent on-chip conductor members 7 .

[0142] like Figures 2 to 9 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit 100; on the other hand, the two adjacent on-chip conductor parts 7 can transmit and receive signals through a conductor connection hole 6 to ensure the stability of signal transmission and reception.

[0143] In some examples, a conductor connection hole 6 is provided between the first conductor 3 and the adjacent on-chip conductor 7 .

[0144] like Figures 2 to 9 As shown, the first conductor part 3 is connected to the on-chip conductor part 7 adjacent to the first conductor part 3 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit 100; on the other hand, the first conductor part 3 and the on-chip conductor part 7 can transmit and receive signals through the conductor connection hole 6, which can ensure the stability of signal transmission and reception.

[0145] In some examples, a conductor connection hole 6 is provided between the second conductor 4 and the adjacent on-chip conductor 7 .

[0146] like Figures 2 to 9 As shown, the second conductor part 4 is connected to the on-chip conductor part 7 adjacent to the second conductor part 4 through a conductor connection hole 6. On the one hand, it is convenient for processing the conductor connection hole 6 and preparing the chip unit 100; on the other hand, the second conductor part 4 and the on-chip conductor part 7 can transmit and receive signals through a conductor connection hole 6, which can ensure the stability of signal transmission and reception.

[0147] In some examples, the difference between the number of conductor connection holes 6 and the number of conductor connection members is .

[0148] like Figures 2 to 9 As shown, a conductor connection hole 6 is provided between each two adjacent on-chip conductor parts 7, a conductor connection hole 6 is provided between the first conductor part 3 and the on-chip conductor part 7, and a conductor connection hole 6 is provided between the second conductor part 4 and the on-chip conductor part 7. The difference between the number of conductor connection holes 6 and the number of conductor connectors is such that the metal layer perforation component 14 can be arranged along the height direction of the metal layer 2, which can reduce the space occupied by the metal layer perforation component 14, further reduce the resistance parasitic parameters and the capacitance parasitic parameters, shorten the preparation cycle of the chip unit 100, and reduce the production cost.

[0149] In some examples, the cross-section of the substrate through hole 5 along the substrate height direction is a polygon, and the length of the first side of the polygon close to the metal layer 2 is shorter than the length of the second long side of the polygon away from the metal layer 2 .

[0150] like Figures 2 to 9 As shown, the cross-section of the substrate through hole 5 is a polygon, and the length of the first side of the polygon close to the metal layer 2 is smaller than the length of the second long side of the polygon away from the metal layer 2, so that one end of the substrate through hole 5 is a flared end and the other end is a closed end, and the closed end is arranged toward the side of the metal layer 2, which is convenient for the opening of the substrate through hole 5 and the filling of the conductor dielectric filling layer 12 into the substrate through hole 5. It can be understood that the conductor dielectric filling can dissipate heat for the chip unit 100.

[0151] In some examples, the cross-section of the through substrate via 5 along the substrate height direction is trapezoidal.

[0152] like Figures 2 to 9 As shown, the cross section of the substrate through hole 5 is trapezoidal, which further facilitates the opening of the substrate through hole 5 .

[0153] In some examples, the short side of the trapezoid is located on a side of the substrate layer 1 close to the metal layer 2 , and the long side of the trapezoid is located on a side of the substrate layer 1 far from the metal layer 2 .

[0154] like Figures 2 to 9 As shown, the short side of the trapezoid is located on the side of the substrate layer 1 close to the metal layer 2, and the long side of the trapezoid is located on the side of the substrate layer 1 away from the metal layer 2. When the conductor dielectric filling layer 12 is filled into the substrate through hole 5, the flared end is set away from the side of the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield of the chip unit 100.

[0155] In some examples, the substrate through hole 5 is truncated cone-shaped, which facilitates the excavation of the substrate through hole 5 and makes the anisotropy of the substrate through hole 5 substantially uniform, thereby further improving the performance of the chip unit 100 .

[0156] In some examples, the truncated cone includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, the first end face is located on the side of the substrate layer 1 close to the metal layer 2, and the second end face is located on the side of the substrate layer 1 away from the metal layer 2.

[0157] like Figures 2 to 9 As shown, the truncated cone shape includes a first end face and a second end face, the diameter of the first end face is smaller than the diameter of the second end face, so that the first end face is a closed end and the second end face is a flared end, and the closed end of the truncated cone is arranged toward the metal layer 2, which is convenient for setting the conductor dielectric filling material into the substrate through hole 5, and at the same time can improve the filling rate of the filling material, which can further ensure the yield of the chip unit 100.

[0158] In some examples, the conductor connection hole 6 is columnar.

[0159] like Figures 2 to 9 As shown, the conductor connection hole 6 is columnar. On the one hand, it is convenient for the production and processing of the conductor connection hole 6. On the other hand, the conductor connection hole 6 serves as a carrier for connecting two adjacent on-chip conductor parts 7, the on-chip conductor part 7 and the first conductor part 3, and the on-chip conductor part 7 and the second conductor part 4. The columnar design can make the signal transmission capabilities at both ends of the conductor connection hole 6 consistent, thereby ensuring the stability of the signal transmission of the chip unit 100.

[0160] like Figures 10 to 20 As shown, according to a second aspect of an embodiment of the present application, a 3D chip is provided, including: the chip unit 100 of any of the above embodiments.

[0161] The 3D chip of the embodiment of the present application includes the chip unit 100 of any of the above embodiments, and therefore has all the beneficial effects of the chip unit 100 of any of the embodiments of the present invention, which will not be described in detail here.

[0162] like Figure 10 and Figure 11 As shown, in some examples, the 3D chip also includes: an end chip 200, wherein the substrate layer of the end chip 200 has not been processed by drilling; the chip unit 100 and the end chip 200 are stacked, and the chip unit 100 is connected to the metal layer 2 of the end chip 200 through the inter-chip connection hole 15.

[0163] In this embodiment, the chip unit 100 is connected to the end chip 200 via the inter-chip connection vias 15. The signals generated in the end chip 200 can be transmitted to the inter-chip connection vias 15 through the metal layer 2. The inter-chip connection vias 15 can transmit the signals to the signal unit through the metal layer through-hole assembly 14. The inter-chip connection vias 15 can also transmit the signals through the chip unit 100 through the metal layer through-hole assembly 14. Considering that the end chip 200 does not need to transmit signals across the chip, it is not necessary to drill holes in the substrate layer 1. The absence of substrate through-holes 5 in the substrate layer 1 of the end chip 200 can reduce the production cost of the end chip 200, thereby reducing the manufacturing cost of the 3D chip.

[0164] like Figure 11 As shown, in some examples, the terminal chip 200 further includes a terminal chip connection hole 16 , and the metal layer 2 of the terminal chip 200 is connected to the inter-chip connection hole 15 through the terminal chip connection hole 16 .

[0165] In this embodiment, an end chip connection hole 16 can be provided on the metal layer 2 of the end chip 200, and the end chip 200 is connected to the inter-chip connection hole 15 of the chip unit 100, so that communication between the chip unit 100 and the end chip 200 can be achieved. In this way, a 3D chip can be built, which can improve the signal processing capability.

[0166] like Figure 11 As shown, in some examples, the end chip connection holes 16 have the same or corresponding shapes as the inter-chip connection holes 15 .

[0167] In this embodiment, the shapes of the end chip connection holes 16 and the inter-chip connection holes 15 of the end chip 200 can be the same or corresponding to each other, so as to facilitate the connection between the end chip connection holes 16 and the inter-chip connection holes 15, which can further reduce the production cost of the 3D chip.

[0168] It is understood that the shapes of the end chip connection holes 16 and the inter-chip connection holes 15 correspond to each other in that the connection ends of the end chip connection holes 16 match the connection ends of the inter-chip connection holes 15 to facilitate connection between the end chip connection holes 16 and the inter-chip connection holes 15. For example, the connection ends of the end chip connection holes 16 and the connection ends of the inter-chip connection holes 15 have the same structure.

[0169] like Figure 11 As shown, in some examples, the cross-sectional shape of the end chip connection via 16 and the inter-chip connection via 15 is the same.

[0170] In this embodiment, the cross-sectional shape of the end chip connection hole 16 is the same as that of the inter-chip connection hole 15. On the one hand, the specifications of the end chip connection hole 16 and the inter-chip connection hole 15 are similar or the same, and the chip unit 100 and the end chip 200 can be prepared through the same production line, which can reduce the production cost of the 3D chip; on the other hand, the signal transmission capacity of the end chip connection hole 16 and the inter-chip connection hole 15 is similar or the same, which can make the communication between the chip unit 100 and the end chip 200 more stable and reliable.

[0171] like Figures 12 to 20 As shown, in some examples, the 3D chip includes: at least two stacked chip units 100 ; two adjacent chip units 100 of the at least two chip units 100 are connected via an inter-chip connection hole 15 .

[0172] In this embodiment, there are multiple chip units 100, and the multiple chip units 100 are stacked. Two adjacent chip units 100 are connected through the inter-chip connection holes 15, so that the multiple chip units 100 can communicate through the inter-chip connection holes 15, which can improve the signal processing capability. At the same time, through the setting of the inter-chip connection holes 15, the inter-chip connection holes 15 have a certain anti-deformation ability and a certain mechanical strength, which can improve the anti-deformation ability of the 3D chip, thereby improving the service life of the 3D chip.

[0173] like Figure 12 As shown, in some examples, two adjacent chip units 100 in at least two chip units 100 are connected through the same inter-chip connection hole 15 .

[0174] In this embodiment, two adjacent chip units 100 are connected through the same inter-chip connection hole 15, that is, the two adjacent inter-chip connection holes 15 share one inter-chip connection hole 15, which can reduce the number of inter-chip connection holes 15, and at the same time make the signal transmission distance shorter, which can improve the smoothness of signal transmission and reduce the production cost of 3D chips.

[0175] like Figure 13 and Figure 20 As shown, in some examples, the inter-chip connection holes 15 of two adjacent chip units 100 in at least two chip units 100 are connected.

[0176] In this embodiment, the inter-chip connection holes 15 of two adjacent chip units 100 in at least two chip units 100 are connected, that is, the connection side of each chip unit 100 has an inter-chip connection hole 15. In this way, there is no need to consider the setting position of the inter-chip connection hole 15 during the preparation process of the chip unit 100. For example, inter-chip connection holes 15 can be set on both sides of the chip unit 100. During the 3D chip construction (or stacking) process, the two adjacent chip units 100 are connected through the two inter-chip connection holes 15, which can make the preparation process of multiple chip units 100 basically the same, can reduce the requirements of 3D chip production on the product line, and can greatly reduce the production cost of 3D chips.

[0177] like Figure 13 As shown, in some examples, the shapes of the two inter-chip connection holes 15 of two adjacent chip units 100 are the same or corresponding.

[0178] In this embodiment, the shapes of the two inter-chip connection holes 15 of two adjacent chip units 100 are the same or corresponding, so as to facilitate the connection of the inter-chip connection holes 15 of the two adjacent chip units 100 and further reduce the production cost of the 3D chip.

[0179] It is understood that the shapes of the two inter-chip connection holes 15 correspond to the connection ends of the end chip connection holes 16 of the two inter-chip connection holes 15 being adapted to facilitate the connection between the two inter-chip connection holes 15. For example, the connection ends of the two inter-chip connection holes 15 have the same structure.

[0180] like Figure 14 As shown, in some examples, the cross-sectional shapes of the two inter-chip connection holes 15 of two adjacent chip units 100 are the same.

[0181] In this embodiment, the cross-sectional shapes of the two inter-chip connection holes 15 of two adjacent chip units 100 are the same. On the one hand, the specifications of the inter-chip connection holes 15 of the two chip units 100 are similar or the same, and the chip units 100 can be manufactured through the same production line, which can reduce the production cost of the 3D chip; on the other hand, the signal transmission capabilities of the inter-chip connection holes 15 of the two chip units 100 are similar or the same, which can make the communication of the 3D chip more stable and reliable.

[0182] like Figure 13 and Figure 15 As shown, in some examples, two adjacent chip units 100 are arranged in the same direction, and the first conductor 3 on one chip unit 100 of the two adjacent chip units 100 is connected to the second conductor 4 of the other chip unit 100 through the inter-chip connection hole 15.

[0183] In this embodiment, two adjacent chip units 100 can be arranged in the same direction, facilitating the construction (or stacking, the same applies to the rest of the text) of the 3D chip, reducing the requirements for the robot control program during the 3D chip production process, and improving the yield rate of 3D chip production. Furthermore, the chip units 100 arranged in the same direction can maintain chip consistency, facilitate process control, and further improve the yield rate of 3D chip production.

[0184] like Figure 14 As shown, in some examples, two adjacent chip units 100 are arranged facing each other, and the first conductors 3 of the two adjacent chip units 100 are connected through the inter-chip connection holes 15 .

[0185] In this embodiment, two adjacent chip units 100 are arranged facing each other, and the first conductors 3 of the two adjacent chip units 100 are connected through the inter-chip connection holes 15, that is, the front of one chip unit 100 in the two adjacent chip units 100 faces the front of the other chip unit 100, and is connected through the inter-chip connection holes 15, so that the fronts of the two chip units 100 can be connected to each other, which facilitates signal transmission between the two chip units 100. The front faces of the two chip units 100 are connected face to face because the inter-chip connection holes 15 are made on the first conductor 3 of the metal layer 2. Compared with opening the substrate through hole 5, the reliability is higher, the processing is simpler, and the yield rate is higher. Figure 16 As shown, in some examples, two adjacent chip units 100 are arranged facing each other, and the second conductor members 4 of the two adjacent chip units 100 are connected through the inter-chip connection holes 15 .

[0186] In this embodiment, two adjacent chip units 100 are arranged facing each other, and the second conductor parts 4 of the two adjacent chip units 100 are connected through the inter-chip connection holes 15, that is, the back side of one chip unit 100 of the two adjacent chip units 100 faces the back side of the other chip unit 100, and they are connected through the inter-chip connection holes 15, so that the back sides of the two chip units 100 can be connected to each other, which facilitates signal transmission between the two chip units 100.

[0187] like Figure 19 As shown, in some examples, two adjacent chip units 100 are arranged facing each other, and the substrate conductor parts 8 of the two adjacent chip units 100 are connected through the inter-chip connection holes 15.

[0188] In this embodiment, when a substrate conductor part 8 is provided in the substrate through hole 5 of the chip unit 100, the back side of one chip unit 100 in two adjacent chip units 100 faces the back side of the other chip unit 100, and the two adjacent substrate conductor parts 8 can be connected through the inter-chip connection hole 15, which can reduce the sinking depth of the inter-chip connection hole 15, that is, reduce the depth of the inter-chip connection hole 15 in the substrate through hole 5 (the other parts of the text are the same), and can reduce the production cost of the 3D chip.

[0189] like Figure 18 As shown, in some examples, two adjacent chip units 100 are arranged in the same direction, and the substrate conductor 8 on one chip unit 100 of the two adjacent chip units 100 is connected to the first conductor 3 of the other chip unit 100 through the inter-chip connection hole 15.

[0190] In this embodiment, when two adjacent chip units 100 are arranged in the same direction and a substrate conductor part 8 is provided in the substrate through hole 5 of the chip unit 100, the front side of one chip unit 100 of the two adjacent chip units 100 faces the back side of the other chip unit 100, and the adjacent first conductor part 3 and the substrate conductor part 8 can be connected through the inter-chip connection hole 15, so that the communication between the two chip units 100 can be achieved, which facilitates the construction of 3D chips.

[0191] In the description of the present invention, the term "plurality" refers to two or more than two. Unless otherwise expressly defined, the orientations or positional relationships indicated by the terms "upper" and "lower" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention. The terms "connect," "install," and "fix" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0192] In the description of the present invention, the terms "one embodiment," "some embodiments," "specific embodiments," etc., mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In the present invention, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0193] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip unit, characterized in that: include: substrate layer; a metal layer, the metal layer comprising a first surface and a second surface opposite to each other, the second surface of the metal layer being disposed on the substrate layer; a metal layer through-hole component, disposed in the metal layer, the metal layer through-hole component comprising: a first conductor, a second conductor, and a conductor connection hole, wherein the first conductor is formed on the first surface of the metal layer, the second conductor is formed on the second surface of the metal layer, the conductor connection hole is formed in the metal layer, and the second conductor is connected to the first conductor through the conductor connection hole, so that a signal can be transmitted through the substrate layer to the first surface; a substrate through hole, formed on the substrate layer and connected to the second conductor; inter-chip connection holes, connected to the first conductive member and / or the second conductive member; A substrate conductor member, disposed in the substrate layer; The substrate through hole includes a bottom through hole and an intermediate connecting hole, wherein the bottom through hole is opened at the bottom of the substrate and connected to the substrate conductor member, and the intermediate connecting hole is located between the substrate conductor member and the second conductor member, and the substrate conductor member is connected to the second conductor member through the intermediate connecting hole, wherein the cross-section of the substrate through hole along the height direction of the substrate is a polygon, the length of the first side of the polygon close to the metal layer is less than the length of the second long side of the polygon away from the metal layer, one end of the substrate through hole is a flared end, and the other end is a closed end, and the closed end is arranged toward the metal layer side; The inter-chip connection hole is connected to the second conductive part through the substrate conductive part.

2. The chip unit according to claim 1, characterized in that: The inter-chip connection holes include: A conductor through-hole connected to the first conductor member and / or the second conductor member.

3. The chip unit according to claim 2, characterized in that: The conductor via is obtained by intermetallic growth via the first conductor member and / or the second conductor member.

4. The chip unit according to claim 1, characterized in that: Also includes: The conductor dielectric filling layer is filled in the substrate through hole.

5. The chip unit according to claim 4, characterized in that: The inter-sheet connection hole is connected to the second conductor member through the conductor dielectric filling layer.

6. A 3D chip, characterized in that: include: The chip unit according to any one of claims 1 to 5.

7. The 3D chip according to claim 6, characterized in that: Also includes: An end chip, wherein the substrate layer of the end chip is not subjected to a hole-digging process; The chip unit and the end chip are stacked and connected to the metal layer of the end chip through the inter-chip connection hole.

8. The 3D chip according to claim 7, characterized in that: include: At least two of the chip units are stacked; Two adjacent chip units among the at least two chip units are connected via the inter-chip connection holes.

Images