Semiconductor device

Abstract

A semiconductor device according to the present disclosure is a chip scale package type semiconductor device mounted face down, and is used for current control of instantaneous discharge of 1 A or more in a discharge circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series connection circuit formed by a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous discharge, connected in series without passing through other elements. The thickness of the semiconductor device is 250 μm or more, and all the elements constituting the series connection circuit are formed on the silicon substrate.

Description

[0001] This application is a divisional application of a patent application with the Chinese Patent Application No. 201980011546.8 (International Application No. PCT / JP2019 / 002567) and the invention title of "Semiconductor Device", which was filed on January 25, 2019. Technical Field

[0002] The present disclosure relates to a semiconductor device, and particularly to a CSP (Chip Size Package) type semiconductor device. Background Art

[0003] A conventionally known semiconductor device for discharge control has one transistor element and one resistance element for limiting the current during discharge (for example, refer to Patent Document 1).

[0004] (Prior Art Documents)

[0005] (Patent Documents)

[0006] Patent Document 1: International Publication No. WO2015 / 166654

[0007] In the conventional semiconductor device, there is only one resistance element for discharge current control, and on the semiconductor device, the heat generation position during discharge control only exists in the local area where the resistance element is arranged. In this case, if the temperature of this local area exceeds the allowable operating temperature of the semiconductor device, it will cause damage to the semiconductor device. In addition, when dissipating the generated heat, it is not easy to transfer the heat generated in the local area to its surrounding areas, so the heat dissipation efficiency is poor. Summary of the Invention

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device that can reduce the maximum temperature of heat generation of the resistance element during discharge control compared to the prior art and can dissipate heat more efficiently than the prior art.

[0009] A semiconductor device according to the present disclosure is a face-down mounted chip size package type semiconductor device, which is used for current control of instantaneous discharge of 1 A or more in the discharge circuit of a battery, and the semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series connection circuit, which is formed by connecting a plurality of resistance elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous discharge in series without passing through other elements. The thickness of the semiconductor device is 250 μm or more, and all the elements constituting the series connection circuit are formed on the silicon substrate.

[0010] A semiconductor device related to the present disclosure is a face-down mounted chip scale package type semiconductor device, which is used for current control of instantaneous discharge of more than 1A in the discharge circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series connection circuit, which is formed by connecting a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous discharge in series without passing through other elements. The volume of the semiconductor device is 1.94 mm 3 or more, and all the elements constituting the series connection circuit are formed on the silicon substrate.

[0011] A semiconductor device related to the present disclosure is a face-down mounted chip scale package type semiconductor device, which is used for current control of instantaneous charge of more than 1A in the charging circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series connection circuit, which is formed by connecting a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous charge in series without passing through other elements. The thickness of the semiconductor device is 250 μm or more, and all the elements constituting the series connection circuit are formed on the silicon substrate.

[0012] A semiconductor device related to the present disclosure is a face-down mounted chip scale package type semiconductor device, which is used for current control of instantaneous charge of more than 1A in the charging circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series connection circuit, which is formed by connecting a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous charge in series without passing through other elements. The volume of the semiconductor device is 1.94 mm 3 or more, and all the elements constituting the series connection circuit are formed on the silicon substrate.

[0013] A semiconductor device related to the present disclosure is a chip - scale package - type semiconductor device mounted face - down, having transistor elements and a plurality of first resistance elements. The transistor elements have a first electrode, a second electrode, and a control electrode for controlling the conduction state between the first electrode and the second electrode. One electrode of each of the plurality of first resistance elements is electrically connected to the second electrode. The semiconductor device has one or more external resistance terminals, an external first terminal electrically connected to the first electrode, and an external control terminal electrically connected to the control electrode. The other electrodes of the plurality of first resistance elements are each in contact connection with any one of the one or more external resistance terminals. The one or more external resistance terminals, the external first terminal, and the external control terminal are external connection terminals formed on the surface of the semiconductor device.

[0014] With this configuration, since a plurality of first resistance elements, which are heat - generating sources, are arranged in parallel, during discharge control, the heat - generating positions are dispersed at the positions where the plurality of first resistance elements are arranged, and the maximum temperature of heat generation in each first resistance element can be reduced compared with the prior art. Thus, both the destruction of the semiconductor device during discharge control can be prevented, and the heat generated by the semiconductor device can be dissipated more efficiently than in the past.

[0015] With the semiconductor device related to the present disclosure, both the destruction of the semiconductor device during discharge control can be prevented, and the heat generated by the semiconductor device can be dissipated more efficiently than in the past. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is an external view of the semiconductor device according to the embodiment.

[0017] Figure 2 is a circuit diagram of the semiconductor device according to the embodiment.

[0018] Figure 3 is a top perspective view of the semiconductor device according to the embodiment.

[0019] Figure 4 is a cross - sectional view of the semiconductor device according to the embodiment.

[0020] Figure 5 is a top perspective view of the semiconductor device according to the embodiment.

[0021] Figure 6 is a circuit diagram of the semiconductor device according to the embodiment.

[0022] Figure 7 is a cross - sectional view of the semiconductor device according to the embodiment.

[0023] Figure 8It is a cross-sectional view of a semiconductor device according to an embodiment.

[0024] Figure 9 It is a cross-sectional view of a semiconductor device according to an embodiment.

[0025] Figure 10 It is a top perspective view of a semiconductor device according to an embodiment.

[0026] Figure 11 It is a cross-sectional view of a semiconductor device according to an embodiment.

[0027] Figure 12 It is a top perspective view of a semiconductor device according to an embodiment.

[0028] Figure 13 It is a schematic diagram showing how a semiconductor device according to an embodiment is installed.

[0029] Figure 14A It is a top view of a semiconductor device according to an embodiment.

[0030] Figure 14B It is a top view of a semiconductor device according to an embodiment.

[0031] Figure 15 It is a schematic diagram showing a charge and discharge circuit according to an embodiment.

[0032] Figure 16 It is a graph showing the temperature simulation results of a semiconductor device according to an embodiment.

[0033] Figure 17 It is a graph showing the relationship between the length of each side and the volume of a semiconductor device according to an embodiment when it satisfies specified temperature conditions.

[0034] Symbol Explanation

[0035] 1, 1A to 1H semiconductor devices

[0036] 10, 210, 410A, 410B, 810 external first terminals

[0037] 11, 211, 411A, 411B, 811 first electrodes

[0038] 20, 220, 420 external second terminals

[0039] 21, 221, 421 drain external electrodes

[0040] 30, 30A to 30F, 230, 230A to 230F, 430, 430A to 430E, 830, 830A to 830G external resistance terminals

[0041] 31, 31A to 31F, 231A to 231F, 431A to 431C, 831, 831A to 831G resistor electrodes

[0042] 40, 240, 440, 840 external control terminals

[0043] 41, 241, 441, 841 third electrodes

[0044] 51, 81 semiconductor substrates

[0045] 52 first low-concentration impurity layer

[0046] 53 body region

[0047] 54 source region

[0048] 55, 84 gate conductors

[0049] 56 gate insulating film

[0050] 57 high-concentration impurity layer

[0051] 61 insulating layer

[0052] 62 passivation layer

[0053] 71 metal layer

[0054] 82 source internal electrode

[0055] 83 drain internal electrode

[0056] 100, 100A to 100C transistor elements

[0057] 110, 110A to 110F, 310A to 310L, 510, 510A to 510J, 910, 910A, 910B first resistor elements

[0058] 111, 311, 511 contacts

[0059] 120, 120A to 120F, 121, 122, 123, 320A to 320G, 321, 322A to 322D, 520A, 520B, 521, 522, 523, 921, 922A to 922G, 923 metal wirings

[0060] 150, 350, 550, 950 transistor element regions

[0061] 160, 360, 560 drain lift regions

[0062] 170, 370, 570, 970 Zener diode regions

[0063] 190 Zener diode

[0064] 280, 280A, 280B First terminal area

[0065] 290, 290A, 290B Second terminal area

[0066] 300 Substrate wiring

[0067] 610, 710, 930, 930A, 930B Second resistor element

[0068] 1010 Battery

[0069] 1020 Control IC Detailed implementation manners

[0070] In addition, the implementation manners described below are all specific examples showing the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, arrangement positions of the constituent elements, connection forms, etc. shown in the following implementation manners are examples, and the gist is not to limit the present disclosure. In addition, among the constituent elements in the following implementation manners, the constituent elements for which the technical solutions showing the most general concept are not described are described as optional constituent elements.

[0071] In the present disclosure, "A is electrically connected to B" includes the case where A is directly connected to B via wiring, the case where A is directly connected to B without passing through wiring, and the case where A is indirectly connected to B via a resistance component (resistor element, resistance wiring).

[0072] (Embodiment)

[0073] <Structure with a vertical MOS transistor>

[0074] The structure of the semiconductor device 1 according to the present embodiment will be described below. The semiconductor device 1 is a CSP chip incorporating one vertical MOS (Metal Oxide Semiconductor) transistor and a plurality of resistor elements, and may also be a BGA (Ball Grid Array)-type, LGA (Land Grid Array)-type, or other type of CSP chip.

[0075] The vertical MOS transistor is a power transistor, that is, a trench MOS type field effect transistor.

[0076] Figure 1 It is an external view of the semiconductor device 1.

[0077] As Figure 1As shown, the semiconductor device 1 has the following as external connection terminals on its surface: an external first terminal 10, an external second terminal 20, external resistance terminals 30A to 30F (hereinafter sometimes referred to as external resistance terminals 30), and an external control terminal 40. The semiconductor device 1 is mounted face-down so that the external connection terminals are joined to the mounting surface of the mounting substrate.

[0078] Figure 2 is the circuit diagram of the semiconductor device 1.

[0079] As Figure 2 shown, the semiconductor device 1, in addition to having the external connection terminals, further includes a vertical MOS transistor, i.e., a transistor element 100, first resistance elements 110A to 110F (hereinafter referred to as first resistance elements 110), and a Zener diode 190 for ESD protection. In the transistor element 100, a body diode BD exists as a parasitic element between the source and the drain.

[0080] One electrode of each of the first resistance elements 110 is electrically connected to the external second terminal 20. The other electrode of each of the first resistance elements 110 is respectively electrically connected to the corresponding external resistance terminals 30 and can be short-circuited to each other.

[0081] Figure 3 is a top perspective view of the semiconductor device 1, Figure 4 is a cross-sectional view of the semiconductor device 1 showing the cut surface along the Figure 3 A1 - A2 line in

[0082] Hereinafter, the internal structure of the semiconductor device 1 will be described using Figure 3 and Figure 4 as illustrations.

[0083] As Figure 4 and Figure 3 shown, the semiconductor device 1 includes a semiconductor substrate 51, a first low-concentration impurity layer 52, a high-concentration impurity layer 57, an insulating layer 61, a passivation layer 62, a metal layer 71, a transistor element 100, a drain external electrode 21, a resistance electrode 31, first resistance elements 110, and metal wirings 120 to 123.

[0084] The semiconductor substrate 51 is made of silicon containing an impurity of a first conductivity type, and can be, for example, an N-type silicon substrate. Here, the first conductivity type is N-type and the second conductivity type is P-type.

[0085] The first low-concentration impurity layer 52 is formed on the upper surface of the semiconductor substrate 51 ( Figure 4is formed in contact with the upper main surface), and the concentration of the impurity of the first conductivity type included in the first low-concentration impurity layer 52 is lower than the concentration of the impurity of the first conductivity type of the semiconductor substrate 51. The first low-concentration impurity layer 52 is formed on the semiconductor substrate 51 by epitaxial growth, for example.

[0086] The high-concentration impurity layer 57 is formed in contact with the upper surface of the semiconductor substrate 51. The concentration of the impurity of the first conductivity type included in the high-concentration impurity layer 57 is higher than the concentration of the impurity of the first conductivity type of the first low-concentration impurity layer 52, and is formed in the drain boost region 160 of the first low-concentration impurity layer 52. The high-concentration impurity layer 57 can be formed by implanting an impurity of the first conductivity type in the drain boost region 160.

[0087] In addition, the high-concentration impurity layer 57 is not essential in the semiconductor device 1. This part can become the first low-concentration impurity layer 52. In this case, an additional implantation process of the impurity of the first conductivity type is not required, and the semiconductor device 1 can be manufactured at low cost.

[0088] The insulating layer 61 is an insulating layer formed in contact with the upper surface of the first low-concentration impurity layer 52, can be silicon dioxide, and can be formed by CVD (Chemical Vapor Deposition) method.

[0089] The passivation layer 62 is a protective layer formed on the surface of the semiconductor device 1, can be silicon nitride, and can be formed by CVD method.

[0090] The metal layer 71 is formed in contact with the lower surface of the semiconductor substrate 51 ( Figure 4 the lower main surface) and is made of a metal material.

[0091] The transistor element 100 is formed in the transistor element region 150, and has a first electrode 11 (hereinafter sometimes referred to as the source electrode) that acts as a source electrode, a semiconductor substrate 51 (hereinafter sometimes referred to as the drain electrode) that acts as a drain electrode, and a gate conductor 55 that acts as a control electrode. The gate conductor 55 controls the conduction state between the first electrode 11 (source electrode) and the semiconductor substrate 51 (drain electrode).

[0092] In the first low-concentration impurity layer 52 in the transistor element region 150, a body region 53 is formed, and the body region 53 contains an impurity of a second conductivity type different from the first conductivity type. A source region 54, a gate conductor 55, and a gate insulating film 56 containing an impurity of the first conductivity type are formed in the body region 53.

[0093] The first electrode 11 is in contact connection with the source region 54 and the body region 53, and its upper surface is exposed on the surface of the semiconductor device 1 through the opening of the passivation layer 62 to serve as the external first terminal 10.

[0094] The drain external electrode 21 is in contact connection with the high-concentration impurity layer 57, and its upper surface is exposed on the surface of the semiconductor device 1 through the opening of the passivation layer 62 to serve as the external second terminal 20.

[0095] The resistance electrodes 31 (31A to 31F) are in contact connection with the other electrodes of the first resistance elements 110 (110A to 110F), and their upper surfaces are exposed on the surface of the semiconductor device 1 through the openings of the passivation layer 62 to serve as the external resistance terminals 30 (30A to 30F). Here, there are multiple resistance electrodes 31, first resistance elements 110, and external resistance terminals 30, which correspond to each other one by one. In addition, the respective resistance electrodes 31 are electrically connected by the metal wiring 122.

[0096] The third electrode 41 (refer to Figure 3 )(hereinafter sometimes referred to as the gate electrode) is electrically connected to the gate conductor 55 (refer to Figure 3 ) through the metal wiring 121 (refer to Figure 4 ). The upper surface of the third electrode 41 is exposed on the surface of the semiconductor device 1 through the opening of the passivation layer 62 to serve as the external control terminal 40.

[0097] The first resistance element 110 is formed in the insulating layer 61 and is made of polysilicon doped with impurities, and can be formed by, for example, the CVD method. The sheet resistance of the polysilicon can be determined by the type and dose of the impurities, etc.

[0098] The metal wirings 120 (120A to 120F) are respectively formed on the insulating layer 61, and the drain external electrode 21 is electrically connected to one of the electrodes of the first resistance elements 110 (110A to 110F).

[0099] The Zener diode 190 is shown as the Zener diode region 170 in Figure 3 , and one of its electrodes is electrically connected to the first electrode 11 through the metal wiring 123, and the other electrode is electrically connected to the third electrode 41.

[0100] The first electrode 11, the drain external electrode 21, the resistance electrodes 31, the third electrode 41, the metal layer 71, and the metal wirings 120 to 123 are not limited, and as an example, they can be made of a metal material containing any one or more of aluminum, copper, gold, and silver.

[0101] The above-described semiconductor device 1 is configured such that the first conductivity type is N-type and the second conductivity type is P-type. However, the semiconductor device according to this embodiment is not limited to this configuration, and it may also be configured such that the first conductivity type is P-type and the second conductivity type is N-type. In this case, the forward direction of the body diode existing as a parasitic element between the source and drain is opposite to the forward direction of the body diode BD of the semiconductor device 1. In addition, the impurity of the first conductivity type may be, for example, arsenic or phosphorus, and the impurity of the second conductivity type may be, for example, boron.

[0102] The above-described semiconductor device 1 is configured to include a plurality of external resistance terminals 30 having the same number as the plurality of first resistance elements 110 and the same number of resistance electrodes 31. The semiconductor device according to this embodiment is not limited to this configuration. As long as there is one or more external resistance terminals 30 and the number of resistance electrodes 31 is less than or equal to the number of external resistance terminals 30 with respect to the plurality of first resistance elements 110. For example, in the case of the above-described semiconductor device 1 (the number of the first resistance elements 110 is 6), the number of the external resistance terminals 30 may be 1 to 5, or 7 or more, and the number of the resistance electrodes 31 may be less than or equal to the number of the external resistance terminals 30. At this time, the other electrode of the first resistance element 110 may be in contact connection with any one of the resistance electrodes 31. In addition, in the following Figure 5 the numerical relationship between the first resistance elements 510A to 510J (hereinafter sometimes referred to as the resistance elements 510), the external resistance terminals 430A to 430E (hereinafter sometimes referred to as the external resistance terminals 430), and the resistance electrodes 431A to 431C (hereinafter sometimes referred to as the resistance electrodes 431) is illustrated.

[0103] In the above-described semiconductor device 1, the shape of the external resistance terminal 30 is circular in a plan view of the semiconductor device 1. However, the semiconductor device according to this embodiment is not limited to a circular shape, and the shape of the external resistance terminal may be an ellipse, a polygon, or the like.

[0104] The semiconductor device 1, with the above configuration, when the potential of the gate electrode becomes above the threshold with respect to the potential of the source electrode and the transistor element 100 is in the conducting state (hereinafter sometimes referred to as the conducting time), can cause the conducting current to flow from the external resistance terminal 30 to the external first terminal 10. The path of this conducting current is from the external resistance terminal 30 to the external first terminal 10, passing through the resistance electrode 31, the first resistance element 110, the metal wiring 120, the drain external electrode 21, the high-concentration impurity layer 57, the semiconductor substrate 51, the first low-concentration impurity layer 52, the body region 53, the source region 54, and the first electrode 11 in sequence. At this time, the current flowing into the first resistance element 110 is divided among the respective first resistance elements 110, so the position of heat generation during conduction is dispersed to the positions where each first resistance element 110 is arranged, and the highest temperature at which each first resistance element generates heat becomes lower according to the degree of current division of the conducting current. Thus, with the semiconductor device 1, the highest temperature of heat generation during conduction can be reduced, and heat dissipation can be performed efficiently.

[0105] In addition, the regions where the first resistance element 110 is in contact connection with the metal wiring 120 and the regions where the first resistance element 110 is in contact connection with the resistance electrode 31 are referred to as the contact points 111, and Figure 3 these contacts are illustrated with common hatching in. The other electrode of the first resistance element 110 is directly in contact connection with the resistance electrode 31 through the contact point 111, so the heat generated in the first resistance element 110 can be transferred from the resistance electrode 31 made of a metal material through the external resistance terminal 30 to the mounting substrate only by the heat conduction path of the metal material. Thus, with the semiconductor device 1, the heat generated during conduction can be efficiently dissipated.

[0106] The other electrodes of the respective first resistance elements 110 are all short-circuited to each other within the semiconductor device 1. Thus, with the semiconductor device 1, even when a part of the external resistance terminals 30, due to mounting failures or the like, is in a state of poor bonding open with respect to the mounting substrate, the resistance value required for discharge control set between the external first terminal 10 and the external resistance terminal 30 can be ensured.

[0107] Preferably, the resistance values of the respective first resistance elements 110 are the same. Thus, the amount of heat generated in each first resistance element 110 is equalized, and the highest temperature of heat generation in each first resistance element can be unified to the lowest value. Thus, with the semiconductor device 1, the highest temperature of heat generation during conduction can be reduced, and in addition, heat dissipation can be performed efficiently. Here, the same resistance value means the same within the production deviation range in the manufacturing process.

[0108] When viewed in plan view of the semiconductor device 1, each external resistance terminal 30 is arranged radially around the external second terminal 20. Here, being arranged radially means that when the semiconductor device 1 is viewed in plan view, from the inside to the outside, the external second terminal 20 is arranged on the inside, and the external resistance terminals 30 are arranged on the outside. In this case, the heat generated in the first resistance element 110 is dissipated from the resistance electrode 31 in contact connection with the contact 111, through the external resistance terminal 30, to a wider area of the mounting substrate, so that heat accumulation at a partial position within the semiconductor device 1 can be suppressed. Thus, the semiconductor device 1 can efficiently dissipate the heat generated during conduction. In addition, in Figure 5 which will be described later, the positional relationship of the arrangement of the external second terminal 420 and the external resistance terminals 430A to 430E (hereinafter sometimes referred to as the external resistance terminal 430) is illustrated.

[0109] In addition, as a condition for being arranged radially, as long as more than half of the radially arranged objects (here, the external resistance terminals 30) satisfy the radial arrangement condition, the same satisfaction condition can be applied to the subsequent description of the radial arrangement.

[0110] When viewed in plan view of the semiconductor device 1, each first resistance element 110 is arranged radially around the external second terminal 20. Thus, the heat generated in the area of the first resistance element 110 is generated in a wider area of the semiconductor device 1, and heat accumulation at a partial position within the semiconductor device 1 can be suppressed. Thus, the semiconductor device 1 can suppress the heat generated during conduction more than before and can efficiently dissipate the heat. In addition, in Figure 5 which will be described later, the positional relationship of the arrangement of the external second terminal 420 and the first resistance terminals 510A to 510J (hereinafter sometimes referred to as the resistance terminal 510) is illustrated.

[0111] When viewed in plan view of the semiconductor device 1, the closest distance of at least one external resistance terminal 30 to the outer periphery of the semiconductor device 1 can be equal to or less than the closest distance of the first resistance element 110 in contact connection with the resistance electrode 31 including the external resistance terminal 30 to the outer periphery of the semiconductor device 1. Thus, heat accumulation within the semiconductor device 1 can be suppressed. Thus, the semiconductor device 1 can efficiently dissipate the heat generated during conduction.

[0112] When viewing the semiconductor device 1 in plan view, the closest distance between the center point of at least one external resistance terminal 30 and the outer periphery of the semiconductor device 1 can be equal to or less than the closest distance between the center point of the first resistance element 110 that is in contact connection with the resistance electrode 31 including the external resistance terminal 30 and the outer periphery of the semiconductor device 1. Thereby, heat accumulation in the semiconductor device 1 can be suppressed. Thus, through the semiconductor device 1, heat generated during conduction can be efficiently dissipated.

[0113] The external second terminal 20 is arranged at a position on the central side relative to other external connection terminals when viewing the semiconductor device 1 in plan view. (It is sufficient that other external connection terminals surround the external second terminal 20.) When the semiconductor device 1 is mounted on the mounting substrate by reflow soldering, the semiconductor device 1 sometimes experiences chip warpage due to heating during the mounting process. The reason for this chip warpage is that the linear expansion coefficient of the metal constituting the metal layer 71 is greater than the linear expansion coefficient of silicon constituting the semiconductor substrate 51, the first low-concentration impurity layer 52, etc., and the central side of the semiconductor device 1 warps away from the mounting substrate. As a result, regarding the possibility of void defects occurring in the bonding portion on the mounting substrate, the external connection terminals arranged on the central side of the semiconductor device 1 are higher than the external connection terminals arranged on the peripheral side. On the other hand, as shown in the application circuit example described later Figure 15 , the external second terminal 20 is sometimes not used in the actual application circuit. Thus, when viewing the semiconductor device 1 in plan view, the external second terminal 20 is arranged on the central side compared to other external connection terminals. Therefore, when the external second terminal 20 is not used in the application circuit, even if void defects occur in the bonding portion of the external terminals on the central side of the semiconductor device 1 during reflow soldering, no actual damage to the application circuit occurs. In addition, the positional relationship between the external second terminal 420, the external first terminals 410A to 410B, the external control terminal 440, and the external resistance terminal 430 is illustrated in Figure 5 .

[0114] When a plurality of first resistance elements 110 that can be considered as heat sources are adjacently arranged in one-to-one correspondence with independent external resistance terminals 30 respectively, the heat dissipation performance is determined by the relationship between the number of external resistance terminals 30 provided in the semiconductor device and the number of the external first terminal 10, the external second terminal 20, and the external control terminal 40 (hereinafter, these three external connection terminals may be collectively referred to as external non-resistance terminals). In other words, the more the number of external resistance terminals 30 as actual discrete heat dissipation sources, the higher the heat dissipation effect. For the sake of simple consideration, it is assumed that the external connection terminals are arranged in a matrix on the surface of the semiconductor device, and considering the case of a minimum configuration of external connection terminals, a 4-terminal case of 2 rows and 2 columns is considered. In this case, a configuration without the external second terminal 20 described later is applied, the number of external resistance terminals 30 is set to 2, and the number of external non-resistance terminals is set to 2 (the external first terminal 10 and the external control terminal 40) to achieve a match. In this case, the external resistance terminals 30 (and the first resistance elements 110 arranged adjacently at the same time) are arranged in an area approximately 1 / 2 of the planar view area of the semiconductor device. (When considering the area ratio of the occupied external connection terminals in the planar view area of the semiconductor device) In the conventional semiconductor device, the number of external connection terminals is 4, and the number of external resistance terminals adjacent to which the resistance elements for discharge current control are arranged is 1. Therefore, even in such a case, the maximum temperature rise during conduction can be reduced, and heat dissipation can be efficiently performed.

[0115] In addition, in the case of the above-mentioned semiconductor device 1, the number of external connection terminals is 9, the number of external resistance terminals 30 is 6, and the external resistance terminals 30 are arranged in an area approximately 2 / 3 of the planar view area of the semiconductor device 1, which can further reduce the maximum temperature rise during conduction, and in addition, heat dissipation can be efficiently performed.

[0116] <Configuration where the first resistance element and the external resistance terminal are not in one-to-one correspondence>

[0117] Figure 5 is a top perspective view of the semiconductor device 1E according to the present embodiment, Figure 6 is a circuit diagram of the semiconductor device 1E.

[0118] Hereinafter, for the same constituent elements in the semiconductor device 1E as those in the semiconductor device 1, the same reference numerals are given as the already described parts, and the detailed description is omitted, and the description will be centered on the differences from the semiconductor device 1.

[0119] In Figure 5 and Figure 6Among them, the external first terminals 410A to 410B, the external second terminal 420, the external resistance terminal 430, and the external control terminal 440 are the same external connection terminals as the external first terminal 10, the external second terminal 20, the external resistance terminal 30, and the external control terminal 40 of the semiconductor device 1, except for the different shapes.

[0120] When the semiconductor device 1E is viewed in plan, each external resistance terminal 430 is arranged radially with the external second terminal 420 as the center.

[0121] Each first resistance element 510 is the same resistance element as the first resistance element 110 of the semiconductor device 1. When the semiconductor device 1E is viewed in plan, it is arranged radially with the external second terminal 420 as the center.

[0122] When the semiconductor device 1E is viewed in plan, the external second terminal 420 is arranged at a position on the central side of the semiconductor device 1E relative to other external connection terminals.

[0123] The first electrodes 411A to 411B, the drain external electrode 421, the resistance electrodes 431A to 431C, and the third electrode 441 are the same electrodes as the first electrode 11, the drain external electrode 21, the resistance electrode 31, and the third electrode 41 of the semiconductor device 1, except for the different shapes.

[0124] The transistor element region 550, the drain boost region 560, and the Zener diode region 570 are the same regions as the transistor element region 150, the drain boost region 160, and the Zener diode region 170 of the semiconductor device 1, respectively.

[0125] The metal wirings 520A to 520B, 521, 522, and 523 are the same wirings as the metal wirings 120, 121, 122, and 123 of the semiconductor device 1, respectively, and the contact 511 is the same contact as the contact 111 of the semiconductor device 1.

[0126] The semiconductor device 1E, in Figure 6An example shown is one in which the first resistor elements 510, the external resistor terminals 430, and the resistor electrodes 431 do not correspond to each other one by one. The number of the first resistor elements 510 is 10, the number of the external resistor terminals 430 is 5, and the number of the resistor electrodes 431 is 3. Specifically, the first resistor element 510A corresponds to the external resistor terminal 430A, the first resistor elements 510B to 510D correspond to the external resistor terminal 430B, the first resistor elements 510E to 510F correspond to the external resistor terminal 430C, the first resistor element 510G corresponds to the external resistor terminal 430D, and the first resistor elements 510H to 510J correspond to the external resistor terminal 430E. In addition, the relationship between the first resistor elements 510 and the resistor electrodes 431 is as follows: the resistor electrode 431A is in contact connection with the first resistor elements 510A to 510D, the resistor electrode 431B is in contact connection with the first resistor elements 510E to 510F, and the resistor electrode 431C is in contact connection with the first resistor elements 510G to 510J, respectively, at the contact 511.

[0127] Regarding the configuration of the semiconductor device 1E described above, similar to the semiconductor device 1, the maximum temperature of heat generation during conduction can be reduced, and in addition, heat dissipation can be performed efficiently.

[0128] Furthermore, since the planar view shapes of the external resistor terminals 430B, 430C, and 430E are elliptical, the terminal area is larger than in the case of a circular shape, and heat dissipation can be performed more efficiently.

[0129] <Configuration with a lateral MOS transistor>

[0130] The above-described semiconductor device 1 has a configuration including a vertical MOS transistor, i.e., the transistor element 100. In the semiconductor device according to the present embodiment, the transistor element is not limited to the configuration of a vertical MOS transistor.

[0131] Figure 7 It is a cross-sectional view of the semiconductor device 1A according to the present embodiment.

[0132] The configuration of the semiconductor device 1A is as follows: the transistor element 100 of the vertical MOS transistor of the semiconductor device 1 is changed to the transistor element 100A of a lateral MOS transistor.

[0133] Regarding the same constituent elements as those of the semiconductor device 1, as the parts that have been described, the same reference numerals are given, and the detailed description is omitted, and the description will be centered on the differences from the semiconductor device 1.

[0134] The outer shape of the semiconductor device 1A is the same as Figure 1 the outer shape of the illustrated semiconductor device 1. In addition, the semiconductor device 1A, at Figure 3The semiconductor device 1 shown in the figure has an external first terminal 10, an external second terminal 20, an external resistance terminal 30, an external control terminal 40, a first resistance element 110, and a Zener diode 190 for ESD protection at the same positions.

[0135] As Figure 7 shown, the semiconductor device 1A includes a semiconductor substrate 81, an insulating layer 61, a passivation layer 62, a metal layer 71, a transistor element 100A, a resistance electrode 31, a first resistance element 110, and a metal wiring 120.

[0136] The semiconductor substrate 81 contains impurities of the second conductivity type and is made of silicon. For example, it can be a P-type silicon substrate. Here, let the first conductivity type be N-type and the second conductivity type be P-type.

[0137] The transistor element 100A has a first electrode 11, a drain external electrode 21, a gate conductor 84, a source internal electrode 82, and a drain internal electrode 83.

[0138] The source internal electrode 82 is a diffusion layer of the first conductivity type formed inside the semiconductor substrate 81 and is in contact connection with the first electrode 11. For example, it can be formed by implanting impurities of the first conductivity type in a part of the area of the semiconductor substrate 81.

[0139] The drain internal electrode 83 is a diffusion layer of the first conductivity type formed inside the semiconductor substrate 81 and is in contact connection with the drain external electrode 21. For example, it can be formed by implanting impurities of the first conductivity type in a part of the area of the semiconductor substrate 81.

[0140] The gate conductor 84 is in contact with the upper surface of the thin-film insulating layer 61 on the semiconductor substrate 81 and is formed between the source internal electrode 82 and the drain internal electrode 83 when viewing the semiconductor device 1A in plan view. It is made of polysilicon implanted with impurities of the first conductivity type and is electrically connected to the third electrode 41 (refer to Figure 3 ) through the metal wiring 121. The gate conductor 84 is the same control electrode as the gate conductor 55 of the semiconductor device 1.

[0141] With the above configuration, the semiconductor device 1A, like the semiconductor device 1, can make current flow from the external resistance terminal 30 to the external first terminal 10 when the transistor element 100A is in the on state. The current path at this time is from the external resistance terminal 30 to the external first terminal 10, passing through the resistance electrode 31, the first resistance element 110, the metal wiring 120, the drain external electrode 21, the drain internal electrode 83, the semiconductor substrate 81, the source internal electrode 82, and the first electrode 11 in sequence.

[0142] In the above-described semiconductor device 1A, the first conductivity type is N-type and the second conductivity type is P-type. However, the semiconductor device according to the present embodiment is not limited to this configuration, and may also be a configuration in which the first conductivity type is P-type and the second conductivity type is N-type.

[0143] <Configuration with a second resistance element>

[0144] The above-described semiconductor device 1 has a configuration in which a first resistance element is provided in a conduction current path. However, the semiconductor device according to the present embodiment may be a configuration in which a second resistance element is further provided.

[0145] Figure 8 It is a cross-sectional view of the vertical MOS transistor type semiconductor device 1F according to the present embodiment.

[0146] Hereinafter, for the same constituent elements in the semiconductor device 1F as those in the semiconductor device 1, the same reference numerals are given to the already described parts, and the detailed description is omitted. The description will be centered on the differences from the semiconductor device 1.

[0147] As Figure 8 shown, in the semiconductor device 1F, for the configuration of the semiconductor device 1, the high-concentration impurity layer 57 is changed to a second resistance element 610.

[0148] The second resistance element 610 is formed so as to be in contact with the semiconductor substrate 51 or the first low-concentration impurity layer 52, and is formed of a second low-concentration impurity layer that contains a lower concentration of impurities of the first conductivity type than the impurities of the first conductivity type in the semiconductor substrate 51. The second resistance element 610 is formed in contact with the drain external electrode 21 below the drain external electrode 21. Therefore, the additional setting of the second resistance element 610 does not increase the area of the semiconductor device 1F. In addition, the second resistance element 610 may be formed of polysilicon containing impurities.

[0149] The path of the conduction current in the semiconductor device 1F is a path that sequentially passes through the resistance electrode 31, the first resistance element 110, the metal wiring 120, the drain external electrode 21, the second resistance element 610, the semiconductor substrate 51, the first low-concentration impurity layer 52, the body region 53, the source region 54, and the first electrode 11 from the external resistance terminal 30 to the external first terminal 10. The heat generation positions during conduction are both the first resistance element 110 and the second resistance element 610. Therefore, the heat generation positions are more dispersed than those of the semiconductor device 1, and the maximum heat generation temperature during conduction can be further reduced. In addition, heat dissipation can be performed more efficiently.

[0150] The resistance values of the respective first resistance elements 110 are the same, and preferably, the resistance value of the second resistance element 610 is a value obtained by multiplying the number of the first resistance elements 110. Thus, the heat generation amounts generated in the respective first resistance elements 110 and the heat generation amount generated in the second resistance element 610 are equalized, and the maximum heat generation temperature in each of the first resistance elements 110 and the second resistance element 610 can be unified to the lowest value.

[0151] Figure 9 It is a cross-sectional view of the lateral MOS transistor type semiconductor device 1G according to the present embodiment.

[0152] Hereinafter, for the same components as those in the semiconductor device 1A in the semiconductor device 1G, the same reference numerals are given as the parts already described, and detailed description thereof is omitted, and the description will be centered on the differences from the semiconductor device 1A.

[0153] As Figure 9 shown, the semiconductor device 1G is configured by adding a second resistance element 710 to the configuration of the semiconductor device 1A.

[0154] The second resistance element 710 is formed on the source internal electrode 82 side in contact with the drain internal electrode 83 between the drain internal electrode 83 inside the semiconductor substrate 81 and directly below the gate conductor 84, and is formed of a low-concentration impurity layer, and the concentration of the impurity of the first conductivity type contained in the low-concentration impurity layer is lower than the concentration of the impurity of the first conductivity type of the drain internal electrode 83.

[0155] The path of the conduction current of the semiconductor device 1G is a path that sequentially passes through the resistance electrode 31, the first resistance element 110, the metal wiring 120, the drain external electrode 21, the drain internal electrode 83, the second resistance element 710, the semiconductor substrate 81, the source internal electrode 82, and the first electrode 11 when going from the external resistance terminal 30 to the external first terminal 10. Since the heat generation positions during conduction are both the first resistance element 110 and the second resistance element 710, the heat generation position is more dispersed than that of the semiconductor device 1A, and the maximum heat generation temperature during conduction can be further reduced, and in addition, heat dissipation can be performed more efficiently.

[0156] The resistance values of the respective first resistance elements 110 are the same, and preferably, the resistance value of the second resistance element 710 is a value obtained by multiplying the number of the first resistance elements 110. Thus, the heat generation amounts generated in the respective first resistance elements 110 and the heat generation amount generated in the second resistance element 710 are equalized, and the maximum heat generation temperature in each of the first resistance elements 110 and the second resistance element 710 can be unified to the lowest value.

[0157] In the thus configured semiconductor device 1G, the second resistance element 710 is connected to the drain internal electrode 83 and is additionally formed on the source internal electrode 82 side. However, it may also be configured by replacing the drain internal electrode 83 at the position of the drain internal electrode 83.

[0158] <Configuration without an external second terminal>

[0159] The above-described semiconductor device 1F has a configuration including an external second terminal 20. However, the semiconductor device according to the present embodiment is not limited to the configuration including the external second terminal 20.

[0160] Figure 10 It is a top perspective view of the semiconductor device 1H.

[0161] Hereinafter, for the same components as those in the semiconductor device 1F in the semiconductor device 1H, the same reference numerals are given to the parts that have already been described, and detailed descriptions are omitted. The description will be centered on the differences from the semiconductor device 1F.

[0162] In Figure 10 , the external first terminal 810, the external resistance terminals 830A to 830G (hereinafter sometimes referred to as the external resistance terminals 830), and the external control terminal 840 are external connection terminals similar to the external first terminal 10, the external resistance terminals 30, and the external control terminal 40 of the semiconductor device 1F, respectively.

[0163] The first electrode 811, the resistance electrodes 831A to 831G (hereinafter sometimes referred to as the resistance electrodes 831), and the third electrode 841 are electrodes similar to the first electrode 11, the resistance electrodes 31, and the third electrode 41 of the semiconductor device 1F, respectively.

[0164] The transistor element region 950 and the Zener diode region 970 are regions similar to the transistor element region 150 and the Zener diode region 170 of the semiconductor device 1F, respectively.

[0165] The metal wirings 921, 922A to 922F, and 923 are wirings similar to the metal wirings 121, 122, and 123 of the semiconductor device 1F, respectively.

[0166] As Figure 10 shown, in the semiconductor device 1H, there is no external second terminal 20 compared to the semiconductor device 1F, but one external resistance terminal 830 is added.

[0167] Figure 11 It is a cross-sectional view of the semiconductor device 1H showing a cut surface along the B1 - B2 line in Figure 10 .

[0168] As Figure 11It is shown that the semiconductor device 1H includes a semiconductor substrate 51, a first low-concentration impurity layer 52, an insulating layer 61, a passivation layer 62, a metal layer 71, a transistor element 100C, a resistance electrode 831 (among 831A to 831G, Figure 11 only 831A to 831B are shown), a first resistance element 910 (among 910A to 910G, Figure 11 only 910A to 910B are shown), and a second resistance element 930 (among 930A to 930G, Figure 11 only 930A to 930B are shown).

[0169] The transistor element 100C is a transistor element similar to the transistor element 100 of the semiconductor device 1F, except that the first electrode 11 is changed to the first electrode 811 and the external first terminal 10 is changed to the external first terminal 810.

[0170] The first resistance element 910 is a resistance element similar to the first resistance element 110 of the semiconductor device 1F and is made of polysilicon into which impurities are implanted.

[0171] The second resistance element 930 is a resistance element similar to the second resistance element 610 of the semiconductor device 1F and is made of a second low-concentration impurity layer.

[0172] The semiconductor device 1H includes the first resistance element 910 formed under the resistance electrode 831, and the other electrode of the first resistance element 910 is in contact connection with the resistance electrode 831. The semiconductor device 1H further includes the second resistance element 930 formed under the first resistance element 910, and the other electrode of the second resistance element 930 is in contact connection with one electrode of the first resistance element 910, and one electrode of the second resistance element 930 is in contact connection with the semiconductor substrate 51.

[0173] The semiconductor device 1H includes seven resistance electrodes 831, seven first resistance elements 910, and seven second resistance elements 930, which correspond to each other one by one.

[0174] The path of the conduction current of the semiconductor device 1H is a path that sequentially passes through the resistance electrode 831, the first resistance element 910, the second resistance element 930, the semiconductor substrate 51, the first low-concentration impurity layer 52, the body region 53, the source region 54, and the first electrode 811 from the external resistance terminal 830 to the external first terminal 810.

[0175] As described above, the semiconductor device 1H does not have an external second terminal 20 as compared with the semiconductor device 1F, but has one more external resistance terminal 830, so that the maximum temperature of heat generation during conduction can be further reduced, and heat dissipation can be performed more efficiently. Further, at this time, the external resistance terminals 830 are distributed at the positions of all four corners when the semiconductor device 1H is viewed in plan, and such a configuration is preferable for heat dissipation by dispersion. Furthermore, at this time, the external first terminal 810 is arranged at a position on the central side with respect to the other external connection terminals, which is preferable for well-balanced heat dissipation dispersion within the semiconductor device 1H.

[0176] The above-described semiconductor device 1H has a configuration in which a plurality of second resistance elements 930 are in one-to-one correspondence with the first resistance elements 910. However, the semiconductor device according to the present embodiment is not limited to the second resistance elements 930 being in one-to-one correspondence with the first resistance elements 910 or being composed of a plurality of them. One second resistance element 930 may be in correspondence with a plurality of first resistance elements 910. In addition, as long as there is one or more second resistance elements 930, the number may be the same as that of the first resistance elements 910.

[0177] In addition, the semiconductor device according to the present embodiment may not have the second resistance element 930. Instead of the second resistance element 930, it may be the first low-concentration impurity layer 52 of the semiconductor device 1F or the high-concentration impurity layer 57 of the semiconductor device 1. In these cases, the external second terminal 20 is not provided, but one more external resistance terminal 830 is provided, so that the maximum temperature of heat generation during conduction can be further reduced, and heat dissipation can be performed more efficiently.

[0178] <Deformation of resistance electrode and first resistance element>

[0179] In the above-described semiconductor devices 1, 1A, 1F, and 1G, the external resistance terminals 30 and the first resistance elements 110 are arranged at Figure 3 or Figure 5 the positions shown, but the semiconductor device according to the present embodiment is not limited to the above-described configuration.

[0180] Figure 12 is a top perspective view of the semiconductor device 1B according to the present embodiment.

[0181] Hereinafter, for the same constituent elements as those of the semiconductor device 1, the same reference numerals are given as those already described, and detailed description thereof is omitted, and the description will be centered on the differences from the semiconductor device 1.

[0182] In Figure 12Among them, the external first terminal 210, the external second terminal 220, the external resistance terminals 230A to 230F (hereinafter sometimes referred to as the external resistance terminals 230), and the external control terminal 240 are external connection terminals that are the same as the external first terminal 10, the external second terminal 20, the external resistance terminal 30, and the external control terminal 40 of the semiconductor device 1, respectively.

[0183] The first resistance elements 310A to 310L are resistance elements that are the same as the first resistance element 110 of the semiconductor device 1.

[0184] The first electrode 211, the drain external electrode 221, the resistance electrodes 231A to 231F, and the third electrode 241 are electrodes that are the same as the first electrode 11, the drain external electrode 21, the resistance electrode 31, and the third electrode 41 in the semiconductor device 1, respectively.

[0185] The transistor element region 350, the drain boost region 360, and the Zener diode region 370 are regions that are the same as the transistor element region 150, the drain boost region 160, and the Zener diode region 170 in the semiconductor device 1, respectively.

[0186] The metal wirings 320A to 320G, 321, 322A to 322D, and 323 are wirings that are the same as the metal wirings 120, 121, 122, and 123 in the semiconductor device 1, respectively, and the contact 311 is a contact that is the same as the contact 111 of the semiconductor device 1.

[0187] As Figure 12 shown, the external resistance terminals 230 are arranged in a matrix in the first terminal region 280 that constitutes approximately 2 / 3 of the planar view area of the semiconductor device 1B. The external first terminal 210, the external second terminal 220, and the external control terminal 240 (hereinafter sometimes collectively referred to as the external non-resistance terminals 2 for these three external connection terminals) are arranged in a row in the second terminal region 290 that constitutes approximately 1 / 3 of the planar view area of the semiconductor device 1B. In other words, in the terminal row where the external resistance terminals 230 are arranged, the external non-resistance terminals 2 are not arranged, and in the terminal row where the external non-resistance terminals 2 are arranged, the external resistance terminals 230 are not arranged.

[0188] Figure 13 It is a schematic diagram showing an example of the state where the semiconductor device 1B is mounted face down on a mounting substrate for mounting a charge and discharge circuit shown in the following Figure 15 shown.

[0189] The substrate wiring 300 is the following Figure 15The wiring on the high-voltage side of the charging and discharging circuit shown is a linear wiring pattern. Generally, for substrate wiring through which a high current flows, in order to avoid a decrease in conduction resistance and current concentration, a bent shape is avoided, and a linear wiring pattern is preferred. In the above semiconductor device 1B, by aligning the orientation of the terminal row in the first terminal region 280 with the wiring direction of the substrate wiring 300, all the external resistance terminals 230 can be joined to the substrate wiring 300.

[0190] Figure 14A , Figure 14B It is a top view of semiconductor devices 1C and 1D according to this embodiment in the case where the number of external resistance terminals 230 is increased with respect to the semiconductor device 1B.

[0191] In semiconductor devices 1C and 1D, the number of terminal rows of the external connection terminals 230 is 6 and 8 respectively. In the first terminal regions 280A and 280B, which are composed of approximately 5 / 6 and approximately 7 / 8 of the planar view area, 15 and 21 external resistance terminals 230 are arranged in a matrix. In the second terminal regions 290A and 290B, which are composed of approximately 1 / 6 and approximately 1 / 8 of the planar view area, the external non-resistance terminals 2 are arranged in a row. When the capacitance of the battery 1010 in the discharge circuit is large, the discharge current of the semiconductor device increases. In order not to exceed the allowable operating temperature of the semiconductor device, it is necessary to increase the number of external resistance terminals 230 to increase the degree of dispersed heat dissipation. At this time, in the above semiconductor devices 1C and 1D, the first terminal regions 280A and 280B and the second terminal regions 290A and 290B are also parallel to one side of the semiconductor devices 1C and 1D, and are configured to be divided into two when viewed in plan. Therefore, they can be mounted on a mounting substrate with a linear wiring pattern.

[0192] In addition, the positional relationship between the first terminal region and the second terminal region may be parallel to one side of the semiconductor device and not divided into two when viewed in plan. For example, it may be a relationship in which a plurality of first terminal regions and one second terminal region are parallel to one side of the semiconductor device and are divided into a plurality of parts when viewed in plan. In other words, as long as the configuration does not include other external terminals in the terminal row including the external resistance terminals, all the external resistance terminals can be mounted on a mounting substrate with a linear wiring pattern.

[0193] In addition, in the above semiconductor device 1B, only the external resistance terminals 230 are arranged in the first terminal region 280, but it may also include the external second terminals 220. In this case, in an application circuit that does not use the external second terminals 220 among the external connection terminals of the semiconductor device 1B, when mounting on a mounting substrate, the external second terminals 220 do not need to be joined to the mounting substrate.

[0194] <Application Example>

[0195] Figure 15 As an application example, in the charge / discharge circuit of a battery such as a smart phone, the semiconductor device 1 is provided on the high-voltage side of the charge / discharge circuit and used as a discharge circuit for instantaneously discharging the battery 1010.

[0196] The semiconductor device 1 instantaneously turns on the transistor element 100 according to a control signal given from the control IC 1020, and instantaneously discharges the battery 1010. By investigating the change in the voltage of the battery 1010 after the discharge, the degree of consumption of the battery 1010 can be estimated. At the time of this instantaneous discharge, a relatively large current of, for example, 1 A or more flows through the semiconductor device 1.

[0197] The inventor assumes Figure 15 In the charge / discharge circuit shown, with the semiconductor device 1 mounted on a glass epoxy substrate of 34 mm × 2.5 mm × 0.4 mm, which is the size of a battery module substrate equivalent to a smart phone, the semiconductor device 1 is operated for 100 ms under specified power consumption conditions, and a temperature change simulation is performed on the semiconductor device 1. Specifically, under the volume conditions of multiple semiconductor devices 1, the peak temperature value of the temperature change during the discharge operation is obtained.

[0198] Figure 16 The simulation results are shown.

[0199] In Figure 16 , the vertical axis is the peak temperature value Tjp, the horizontal axis is the volume V, the diamond mark indicates the result when the mounting substrate is a 1-layer metal substrate and the power consumption condition is 6.16 W, the circular mark indicates the result when the mounting substrate is a 3-layer metal substrate and the power consumption condition is 7.04 W, and the triangular mark indicates the result when the mounting substrate is a 3-layer metal substrate and the power consumption condition is 9.02 W.

[0200] From this result, at the start of the conduction operation of the transistor element 100, the heat generated in the semiconductor device 1 is much more stored in the semiconductor device 1 than dissipated to the mounting substrate. Therefore, for the peak temperature value Tjp, considering the volume V, it can be thought that the larger the volume V, the smaller the peak temperature value Tjp.

[0201] In addition, from this result, the following insight is obtained. In order to reduce the peak temperature value Tjp to below the allowable junction temperature of 150 °C, when the mounting substrate is a 1-layer metal substrate and the power consumption condition is 6.16 W, the volume V can be set to 2.20 mm 3 or more, and when the mounting substrate is a 3-layer metal substrate and the power consumption condition is 7.04 W, the volume V can be set to 1.94 mm3 As described above, when the mounting substrate is a three-layer metal substrate and the power consumption condition is 9.02 W, the volume V can be set to 3.05 mm 3 As described above.

[0202] Figure 17 Based on the above insights, the structural conditions of the semiconductor device 1 for controlling the peak temperature value Tjp below the allowable junction temperature of 150°C are discussed. When viewing the semiconductor device 1 in plan view, if the length of one side is set as X, the length of the other side is set as Y, the thickness of the semiconductor device 1 is set as Z, and the volume of the semiconductor device 1 is set as V, it is a diagram showing the relationship among X, Y, Z, and V.

[0203] Through Figure 17 The following insights can be obtained. When X is 4.4 mm and Y is 2.0 mm, to control the peak temperature value Tjp below the allowable junction temperature of 150°C, when the mounting substrate is a one-layer metal substrate and the power consumption condition is 6.16 W, the thickness of the semiconductor device 1 can be set to 250 μm or more. When the mounting substrate is a three-layer metal substrate and the power consumption condition is 9.02 W, the thickness of the semiconductor device 1 can be set to 350 μm or more.

[0204] As Figure 15 As shown, the semiconductor device 1 with the above structure is used as a discharge circuit for discharging the battery, but the semiconductor device related to this embodiment is not limited thereto. For example, it can also be used as a charging circuit for charging the battery. In this case, in the semiconductor device 1, it is configured with the first conductivity type as P-type and the second conductivity type as N-type, and the external resistance terminal 30 is connected to the anode-side node of the battery 1010, and a voltage higher than the anode voltage of the battery is applied to the external first terminal 10 to achieve this.

[0205] As described above, the semiconductor device related to this embodiment has been described according to the embodiment, but the present disclosure is not limited to these embodiments. Within the scope not exceeding the gist of the present invention, various modifications conceived by those skilled in the art can be implemented in this embodiment, or forms constructed by combining the constituent elements of the exemplified different semiconductor devices can be included within the scope of this embodiment.

[0206] For example, the transistor element can be an NPN-type or PNP-type bipolar transistor.

[0207] The semiconductor device according to the present invention can be widely used as a device for controlling the conduction state of the current path.

Claims

1. A semiconductor device is a chip - scale package - type semiconductor device mounted face - down, and is used for current control of instantaneous discharge of 1 A or more in a discharge circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series - connection circuit, which is formed by connecting in series a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous discharge without passing through other elements. The thickness of the semiconductor device is 250 μm or more. All the elements constituting the series - connection circuit are formed on the silicon substrate. When the semiconductor device is viewed in plan, the plurality of resistor elements are arranged radially with the position on the central side of the semiconductor device as the center.

2. The semiconductor device according to claim 1. The plurality of resistor elements are dispersedly arranged in an area of more than half of the plan - view area of the semiconductor device.

3. The semiconductor device according to claim 1. The thickness of the semiconductor device is 350 μm or more.

4. A semiconductor device is a chip - scale package - type semiconductor device mounted face - down, and is used for current control of instantaneous discharge of 1 A or more in a discharge circuit of a battery. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series - connection circuit, which is formed by connecting in series a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous discharge without passing through other elements. The volume of the semiconductor device is 1.94 mm 3 or more. All the elements constituting the series - connection circuit are formed on the silicon substrate. When the semiconductor device is viewed in plan, the plurality of resistor elements are arranged radially with the position on the central side of the semiconductor device as the center.

5. The semiconductor device according to claim 4. The plurality of resistor elements are dispersedly arranged in an area of more than half of the plan - view area of the semiconductor device.

6. The semiconductor device according to claim 4. The volume of the semiconductor device is 2.20 mm 3 or more.

7. The semiconductor device according to claim 6. The volume of the semiconductor device is 3.05 mm 3Above.

8. A semiconductor device is a chip - scale package - type semiconductor device mounted face - down and is used for current control in the charging circuit of a battery for instantaneous charging of 1 A or more. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series - connection circuit formed by a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous charging, which are connected in series without passing through other elements. The thickness of the semiconductor device is 250 μm or more. All the elements constituting the series - connection circuit are formed on the silicon substrate. When the semiconductor device is viewed in plan, the plurality of resistor elements are arranged radially with the position on the central side of the semiconductor device as the center.

9. The semiconductor device according to claim 8, The plurality of resistor elements are dispersedly arranged in an area of more than half of the plan - view area of the semiconductor device.

10. The semiconductor device according to claim 8, The thickness of the semiconductor device is 350 μm or more.

11. A semiconductor device is a chip - scale package - type semiconductor device mounted face - down and is used for current control in the charging circuit of a battery for instantaneous charging of 1 A or more. The semiconductor device has a plurality of elements formed on a silicon substrate. The semiconductor device has a series - connection circuit formed by a plurality of resistor elements connected in parallel with each other and a transistor element that instantaneously becomes conductive during the instantaneous charging, which are connected in series without passing through other elements. The volume of the semiconductor device is 1.94 mm 3 Above, All the elements constituting the series - connection circuit are formed on the silicon substrate. When the semiconductor device is viewed in plan, the plurality of resistor elements are arranged radially with the position on the central side of the semiconductor device as the center.

12. The semiconductor device according to claim 11, The plurality of resistor elements are dispersedly arranged in an area of more than half of the plan - view area of the semiconductor device.

13. The semiconductor device according to claim 11, The volume of the semiconductor device is 2.20 mm 3 Above.

14. The semiconductor device according to claim 13, The volume of the semiconductor device is 3.05 mm 3 or more.

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