Semiconductor structure and method of forming the same

Abstract

The application discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a metal oxide layer on the substrate in a first region and a second region; forming a covering layer on the metal oxide layer in the second region, and exposing the metal oxide layer in the first region; performing a heat treatment on the metal oxide layer in an oxygen-containing atmosphere, and reacting the metal oxide layer with the substrate to form an interface layer and a transition medium layer which are sequentially stacked between the substrate and the metal oxide layer in the first region, and the transition medium layer between the substrate and the metal oxide layer in the second region; and removing the covering layer. The interface layer in the first region is used to form a first gate medium layer, and the transition medium layer in the second region is used to form a second gate medium layer. The application adjusts the threshold voltage of the device by adjusting the gate medium layer, and is beneficial to reducing the difficulty of adjusting the threshold voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) transistors are among the most important components in integrated circuits. These CMOS transistors include PMOS and NMOS devices.

[0003] As the feature size of semiconductor structures continues to shrink, the most challenging problem is how to solve the issue of high leakage current in semiconductor structures. This high leakage current is primarily caused by the continuous reduction in the thickness of the traditional gate dielectric layer.

[0004] The current solution involves replacing the traditional silicon dioxide gate dielectric with a high-k gate dielectric material and using metal as the gate electrode to avoid the Fermi level pinning effect and boron infiltration effect between the high-k material and the traditional gate electrode material. Furthermore, to adjust the threshold voltage of CMOS transistors, a work function layer is currently formed on the surface of the high-k gate dielectric layer; the work function layer of PMOS devices requires a higher work function, while the work function layer of NMOS devices requires a lower work function. Therefore, the materials of the work function layers for PMOS and NMOS devices differ during their fabrication to meet their respective work function adjustment requirements.

[0005] However, adjusting the threshold voltage is currently quite difficult. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which adjusts the threshold voltage of the device by adjusting the gate dielectric stack, thereby reducing the difficulty of adjusting the threshold voltage.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a discrete first region and a second region; a first gate dielectric stack located on the substrate in the first region, the first gate dielectric stack including an interface layer and a first gate dielectric layer located on the interface layer; and a second gate dielectric stack located on the substrate in the second region, the second gate dielectric stack including a transition dielectric layer and a second gate dielectric layer located on the transition dielectric layer, wherein the transition dielectric layer is formed by heat-treating a metal oxide layer in an oxygen-containing atmosphere to react the metal oxide layer with the substrate.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a discrete first region and a second region; forming a metal oxide layer on the substrate of the first region and the second region; forming a capping layer on the metal oxide layer of the second region to expose the metal oxide layer of the first region; heat-treating the metal oxide layer in an oxygen-containing atmosphere to react the metal oxide layer with the substrate to form an interface layer and a transition dielectric layer stacked sequentially between the substrate and the metal oxide layer in the first region, and a transition dielectric layer between the substrate and the metal oxide layer in the second region; removing the capping layer after heat-treating the metal oxide layer; after removing the capping layer, the interface layer of the first region is used to form a first gate dielectric stack with a first gate dielectric layer, and the transition dielectric layer of the second region is used to form a second gate dielectric stack with a second gate dielectric layer.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this embodiment of the invention, since a capping layer is formed on the metal oxide layer in the second region, the oxygen partial pressure conditions of the metal oxide layer in the first region and the metal oxide layer in the second region are different during the heat treatment of the metal oxide layer in an oxygen-containing atmosphere. Accordingly, this embodiment of the invention utilizes the characteristic that different types of dielectric layers can be formed between the metal oxide layer and the substrate under different oxygen partial pressure conditions. In the same step, an interface layer and a transition dielectric layer are stacked between the substrate and the metal oxide layer in the first region, and a transition dielectric layer is formed between the substrate and the metal oxide layer in the second region. The interface layer in the first region is used to form a first gate dielectric stack with the first gate dielectric layer, and the transition dielectric layer in the second region is used to form a second gate dielectric stack with the second gate dielectric layer. The transition dielectric layer also enables direct contact between the second gate dielectric layer and the substrate. (Contact), thus making the flat band voltage offset caused by the second gate dielectric stack different from that caused by the first gate dielectric stack. In this way, by adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, which helps to reduce the difficulty of adjusting the threshold voltage and obtain devices with multiple threshold voltage types to meet the diverse needs of the device threshold voltage as the device size continues to shrink. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0013] Figures 10 to 11 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figures 12 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figure 14 This is a schematic diagram of the key steps in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] As the feature size of semiconductor structures continues to shrink, adjusting the threshold voltage becomes increasingly difficult. This paper analyzes the reasons for this increased difficulty in adjusting the threshold voltage, using a semiconductor structure formation method as an example.

[0017] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1 A substrate 10 is provided, on which an interlayer dielectric layer 20 is formed, and a gate opening 25 is formed within the interlayer dielectric layer 20.

[0019] The substrate 10 may include one or both of an NMOS region (not shown) and a PMOS region (not shown). The NMOS region can be used to form NMOS devices with different threshold voltages, and the PMOS region can be used to form PMOS devices with different threshold voltages.

[0020] The semiconductor structure is formed using a gate-last process, and the gate opening 25 is formed by removing the dummy gate.

[0021] Continue to refer to Figure 1 A high-k gate dielectric layer 30 is formed to conformally cover the gate opening 25.

[0022] refer to Figure 2 This forms a work function layer 40 that conformally covers the high-k gate dielectric layer 30.

[0023] Subsequent processes include: filling the gate opening 25 to form a gate electrode layer covering the work function layer 40; removing the gate electrode layer, work function layer 40 and high-k gate dielectric layer 30 above the top surface of the interlayer dielectric layer 20 through a planarization process, and using the remaining gate electrode layer, work function layer 40 and high-k gate dielectric layer 30 in the gate opening 25 to form a gate structure.

[0024] The work function layer 40 is used to adjust the threshold voltage of the corresponding MOS device. Depending on the type of MOS device to be formed and the corresponding threshold voltage, the work function layer 40 is a single-layer structure, or the work function layer 40 is a stacked structure, wherein the stacked work function layer 40 includes multiple sub-work function layers (not shown) stacked sequentially.

[0025] In order to meet the switching speed requirements of different MOS devices in integrated circuit design, it is necessary to form MOS devices with multiple threshold voltage types, which leads to an increase in the number of sub-work function layers contained in the work function layer 40 of the stacked structure. In particular, when the semiconductor structure formation method is used to form MOS devices with multiple threshold voltage types on the same substrate 10, the more types of threshold voltages there are, the more sub-work function layers contained in the work function layer 40 of the stacked structure.

[0026] However, as the feature size of the semiconductor structure continues to decrease, the size of the gate opening 25 also decreases accordingly. When the number of sub-work function layers contained in the work function layer 40 of the stacked structure increases, the difficulty of forming the work function layer 40 in the gate opening 25 also increases.

[0027] Therefore, due to the size limitation of the gate opening 25, it is currently difficult to adjust the threshold voltage of the MOS device by adjusting the sub-work function layers contained in the work function layer 40 of each gate opening 25, which makes it more difficult to adjust the threshold voltage.

[0028] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. Since a capping layer is formed on the metal oxide layer in the second region, the oxygen partial pressure conditions of the metal oxide layers in the first and second regions differ during heat treatment in an oxygen-containing atmosphere. Accordingly, this invention utilizes the characteristic that different types of dielectric layers can be formed between the metal oxide layer and the substrate under different oxygen partial pressure conditions. In the same step, an interface layer and a transition dielectric layer are stacked between the substrate and the metal oxide layer in the first region, and a transition dielectric layer is formed between the substrate and the metal oxide layer in the second region. The transition dielectric layer also enables direct contact between the second gate dielectric layer and the substrate, resulting in different flat-band voltage offsets caused by the second gate dielectric stack and the first gate dielectric stack. By adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, reducing the difficulty of adjusting the threshold voltage and obtaining devices with multiple threshold voltage types to meet the diverse threshold voltage requirements as device sizes continue to shrink.

[0029] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0030] refer to Figure 3 A substrate 100 is provided, including a separate first region 100a and a second region 100b.

[0031] The substrate 100 is used to provide a process platform for subsequent processes.

[0032] In this embodiment, the substrates 100 of the first region 100a and the second region 100b are also used as channels for different devices. Subsequently, a first gate structure is formed on the substrate 100 of the first region 100a, and a second gate structure is formed on the substrate 100 of the second region 100b.

[0033] Accordingly, both the first region 100a and the second region 100b are channel regions.

[0034] As an example, the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a three-dimensional substrate, for example, when forming a fin field-effect transistor, the substrate includes a substrate and fins located on the substrate.

[0035] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of silicon germanide, germanium, or silicon carbide.

[0036] In this embodiment, during the step of providing the substrate 100, a sacrificial oxide layer 110 is further formed on the surface of the substrate 100. The sacrificial oxide layer 110 is used to protect the substrate 100. In this embodiment, the material of the sacrificial oxide layer 110 is silicon oxide.

[0037] It should be noted that in this embodiment, the gate structure is formed using a gate-last process as an example. Therefore, in this embodiment, after providing the substrate 100, the formation method further includes: forming a dummy gate structure (not shown) on the sacrificial oxide layer 110 of the first region 100a and the second region 100b; forming an interlayer dielectric layer (not shown) on the substrate 100 on the side of the dummy gate structure; removing the dummy gate structure and forming a gate opening (not shown) in the interlayer dielectric layer to expose the sacrificial oxide layer 110.

[0038] The pseudo-gate structure is used to pre-reserve space for the subsequent formation of the gate structure.

[0039] In this embodiment, the material of the pseudo-gate structure includes polysilicon.

[0040] Interlayer dielectric layers are used to isolate adjacent devices. As an example, the material of the interlayer dielectric layer is silicon oxide.

[0041] The gate opening provides space for the formation of the gate structure. The bottom of the gate opening exposes the sacrificial oxide layer 110 to facilitate the subsequent removal of the sacrificial oxide layer 110 from the first region 100a and the second region 100b, thereby allowing the subsequently formed metal oxide layer to directly contact the substrate 100.

[0042] refer to Figure 4 The method for forming the semiconductor structure further includes: after providing the substrate 100, removing the sacrificial oxide layer 110 on the surface of the substrate 100 of the first region 100a and the second region 100b.

[0043] Specifically, after the gate opening is formed, the sacrificial oxide layer 110 exposed by the gate opening is removed.

[0044] By removing the sacrificial oxide layer 110 from the surface of the substrate 100 in the first region 100a and the second region 100b, the subsequently formed metal oxide layer can directly contact the substrate 100. Consequently, after the first gate dielectric stack is formed on the first region 100a and the second gate dielectric stack is formed on the second region 100b, the first gate dielectric stack and the second gate dielectric stack can contact the channel of the corresponding device.

[0045] The process for removing the sacrificial oxide layer 110 from the surface of the substrate 100 of the first region 100a and the second region 100b includes one or both of wet etching and dry etching processes.

[0046] As an example, a wet etching process is used to remove the sacrificial oxide layer 110 on the surface of the substrate 100 in the first region 100a and the second region 100b. The sacrificial oxide layer 110 is thin and easily removed cleanly by the wet etching process, which is simple to operate and low in cost. Specifically, the material of the sacrificial oxide layer 110 is silicon oxide, and the etching solution for the wet etching process is a hydrofluoric acid solution.

[0047] refer to Figure 5 A metal oxide layer 120 is formed on a substrate 100 in the first region 100a and the second region 100b, wherein the dielectric constant of the metal oxide layer 120 is greater than that of silicon oxide.

[0048] The metal oxide layer 120 is then subjected to heat treatment to react with the substrate 100, forming an interface layer and a transition medium layer that are stacked sequentially between the substrate 100 and the metal oxide layer 120 in the first region 100a, and a transition medium layer that is stacked between the substrate 100 and the metal oxide layer 120 in the second region 100b.

[0049] Furthermore, the metal oxide layer 120 is subsequently heat-treated in an oxygen-containing atmosphere to react with the substrate 100. An interface layer and a transition dielectric layer are stacked sequentially between the substrate 100 and the metal oxide layer 120 in the first region 100a. During the heat treatment, metal atoms in the metal oxide layer 120 diffuse into the interface layer, thereby allowing metal atoms to precipitate at the interface between the interface layer and the subsequent first gate dielectric layer, forming an electric dipole layer. The electric dipole layer can also play a role in regulating the threshold voltage of the device.

[0050] The dielectric constant of the metal oxide layer 120 is greater than that of silicon oxide. The high dielectric constant of the metal oxide layer 120 allows the remaining metal oxide layer 120 to be retained after subsequent heat treatment and used to form a gate dielectric layer.

[0051] In this embodiment, the material of the metal oxide layer 120 in the step of forming the metal oxide layer 120 includes lanthanum oxide, cerium oxide, aluminum oxide, manganese oxide, or magnesium oxide. During the heat treatment of the metal oxide layer 120, under different oxygen partial pressure conditions, the type of dielectric layer formed by the reaction of the material of the metal oxide layer 120 with the substrate 100 is different. Therefore, the properties of the metal oxide layer 120 material can be utilized to form different dielectric stacks between the substrate 100 and the metal oxide layer 120 in different regions in the same step.

[0052] When the material of the metal oxide layer 120 is lanthanum oxide or cerium oxide, since the flat band voltage generated by lanthanum oxide and cerium oxide with the substrate 100 is negative, after heat treatment to form a transition dielectric layer, the range of the adjusted flat band voltage offset can be increased through the transition dielectric layer and the first gate dielectric layer, which is beneficial to increasing the range of the adjusted threshold voltage offset. Moreover, lanthanum oxide and cerium oxide are both high-k dielectric materials with high dielectric constants, which is beneficial to enable the metal oxide layer 120 and the formed transition dielectric layer to serve as high-k gate dielectric layers.

[0053] In this embodiment, lanthanum oxide is used as an example to illustrate the material of the metal oxide layer 120. Compared with cerium oxide, lanthanum oxide has a larger absolute value of the flat band voltage when in direct contact with the substrate 100. Therefore, by selecting lanthanum oxide as the material of the metal oxide layer 120, it is beneficial to further increase the range of the adjustable threshold voltage offset. Moreover, selecting lanthanum oxide also helps to improve the process compatibility of the metal oxide layer 120.

[0054] In this embodiment, in the step of forming the metal oxide layer 120, the metal oxide layer 120 is formed on the substrate 100 at the bottom of the gate opening.

[0055] As the feature size of semiconductor structures continues to shrink, the size of the gate opening also decreases accordingly. Due to the size limitation of the gate opening, it is currently difficult to adjust the threshold voltage of a MOS device by adjusting the sub-work function layers contained in the work function layers of each gate opening. In this embodiment, a metal oxide layer 120 is formed on the substrate 100 at the bottom of the gate opening to facilitate the subsequent formation of different gate dielectric stacks, thereby achieving the effect of adjusting the threshold voltage. This helps avoid forming too many stacked structures in the gate opening, thus reducing the difficulty of adjusting the threshold voltage and meeting the demand for diverse threshold voltage types as device dimensions continue to shrink.

[0056] In this embodiment, the process for forming the metal oxide layer 120 includes: atomic layer deposition (ALD), physical vapor deposition (PVD), or metal-organic chemical vapor deposition (MOCVD). The physical vapor deposition process can be electron beam evaporation or sputtering.

[0057] refer to Figure 6 and Figure 7 A capping layer 140 is formed on the metal oxide layer 120 of the second region 100b, exposing the metal oxide layer 120 of the first region 100a.

[0058] The capping layer 140 covers the metal oxide layer 120 of the second region 100b and serves as an annealing capping layer to reduce the contact between the metal oxide layer 120 of the second region 100b and oxygen. As a result, when the metal oxide layer 120 is subsequently heat-treated in an oxygen-containing atmosphere, the oxygen partial pressure conditions of the metal oxide layer 120 of the first region 100a and the metal oxide layer 120 of the second region 100b are different, thereby enabling the formation of different stacks between the metal oxide layer 120 and the substrate 100 in different regions.

[0059] Therefore, the cover layer 140 is made of a material with high density and good sealing properties, which helps to isolate the metal oxide layer 120 of the second region 100b from oxygen. In this embodiment, the material of the cover layer 140 includes titanium nitride, tantalum nitride, amorphous silicon, or aluminum oxide.

[0060] As an example, the material of the capping layer 140 is titanium nitride, which is beneficial for improving process compatibility.

[0061] It should be noted that the thicker the capping layer 140, the better its sealing effect and the more significant the contact between the metal oxide layer 120 in the second region 100b and oxygen. This results in a greater difference in oxygen partial pressure between the metal oxide layer 120 in the first region 100a and the second region 100b during subsequent heat treatment of the metal oxide layer 120 in an oxygen-containing atmosphere. Therefore, in actual processes, the thickness of the capping layer 140 needs to be appropriately set to ensure that the subsequently formed gate dielectric stack meets process requirements.

[0062] In this embodiment, the step of forming the cover layer 140 includes: as follows Figure 6 As shown, a covering material layer 130 is formed on the substrate 100, covering the metal oxide layer 120 of the first region 100a and the second region 100b; as Figure 7 As shown, the covering material layer 130 on the metal oxide layer 120 located in the first region 100a is removed, and the remaining covering material layer 130 is used as the covering layer 140.

[0063] In this embodiment, the process for forming the cover material layer 130 includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0064] The process of forming the cover material layer 130 affects its density and sealing performance, which in turn affects the isolation effect of the cover layer 140 on the metal oxide layer 120 of the second region 100b from oxygen. This, in turn, affects the difference in oxygen partial pressure between the metal oxide layer 120 of the first region 100a and the metal oxide layer 120 of the second region 100b during subsequent heat treatment of the metal oxide layer 120 in an oxygen-containing atmosphere. Therefore, in actual processes, the process of forming the cover material layer 130 should be reasonably adjusted based on actual process requirements.

[0065] In this embodiment, one or both of dry and wet etching processes are used to remove the covering material layer 130 on the metal oxide layer 120 located in the first region 100a.

[0066] refer to Figure 8The metal oxide layer 120 is heat-treated 200 in an oxygen-containing atmosphere to react the metal oxide layer 120 with the substrate 100 to form an interface layer 150 and a transition medium layer 160 stacked sequentially between the substrate 100 and the metal oxide layer 120 in the first region 100a, and a transition medium layer 160 between the substrate 100 and the metal oxide layer 120 in the second region 100b.

[0067] After the cover layer 140 is subsequently removed, the interface layer 150 of the first region 100a is used to form a first gate dielectric stack with the first gate dielectric layer, and the transition dielectric layer 160 of the second region 100b is used to form a second gate dielectric stack with the second gate dielectric layer.

[0068] Since a capping layer 140 is formed on the metal oxide layer 120 of the second region 100b, the oxygen partial pressure conditions of the metal oxide layer 120 of the first region 100a and the metal oxide layer 120 of the second region 100b are different during the heat treatment 200. Accordingly, taking advantage of the characteristic that different types of dielectric layers can be formed between the metal oxide layer 120 and the substrate 100 under different oxygen partial pressure conditions, in this embodiment, in the same step, an interface layer 150 and a transition dielectric layer 160 are formed between the substrate 100 and the metal oxide layer 120 of the first region 100a, and a transition dielectric layer 160 is formed between the substrate 100 and the metal oxide layer 120 of the second region 100b. The transition dielectric layer 160 also enables direct contact between the second gate dielectric layer and the substrate 100. (Contact), thereby making the flat band voltage offset caused by the second gate dielectric stack different from that caused by the first gate dielectric stack. In turn, by adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, and devices with multiple threshold voltage types can be obtained to meet the demand for diversified threshold voltage of devices as device size continues to shrink.

[0069] Specifically, during the heat treatment 200 of the metal oxide layer 120 in an oxygen-containing atmosphere, oxygen atoms diffuse to the interface between the metal oxide layer 120 and the substrate 100, thereby reacting with the metal oxide layer 120 and the substrate 100.

[0070] The difference in the total amount of oxygen atoms in contact with the metal oxide layer 120 and the substrate 100 results in different dielectric layers formed at the interface between the metal oxide layer 120 and the substrate 100.

[0071] The heat treatment 200 on the metal oxide layer 120 is also used to repair the interface defects generated when the metal oxide layer 120 is directly formed on the substrate 100, thereby improving the interface quality of the surface of the substrate 100.

[0072] In this embodiment, since a capping layer 140 is formed on the metal oxide layer 120 of the second region 100b, there are more oxygen atoms in contact at the interface between the metal oxide layer 120 and the substrate 100 of the first region 100a. While oxygen reacts with the metal oxide layer 120 and the substrate 100 to form the transition medium layer 160, a portion of oxygen also reacts with the substrate 100 to form the interface layer 150. Thus, not only the transition medium layer 160 but also the interface layer 150 are formed between the metal oxide layer 120 and the substrate 100 of the first region 100a. However, there are fewer oxygen atoms in contact at the interface between the metal oxide layer 120 and the substrate 100 of the second region 100b. Oxygen only reacts with the metal oxide layer 120 and the substrate 100, thus the transition medium layer 160 is formed only between the metal oxide layer 120 and the substrate 100 of the second region 100b.

[0073] In this embodiment, the metal oxide layer 120 is located in the gate opening, and the transition dielectric layer 160 and the interface layer 150 are formed by heat treatment of the metal oxide layer 120 in an oxygen-containing atmosphere. This helps to avoid the formation of more stacked layers in the gate opening, thereby reducing the difficulty of adjusting the threshold voltage and meeting the demand for diversified threshold voltage types of devices as device size continues to shrink.

[0074] In this embodiment, the interface layer 150 is formed by oxidizing the substrate 100. In this embodiment, the material of the substrate 100 is silicon, and the material of the interface layer 150 is correspondingly silicon oxide. In other embodiments, depending on the material of the substrate, the material of the interface layer may also be silicon germanium oxide, germanium oxide, or carbon-containing silicon oxide.

[0075] The transition dielectric layer 160 is used to enable direct contact between the subsequent second gate dielectric layer and the substrate 100. Through the transition dielectric layer 160 and the second gate dielectric layer, the flat band voltage of the second gate dielectric stack can be adjusted, thereby adjusting the threshold voltage of the device.

[0076] In this embodiment, the transition dielectric layer 160 is formed by the reaction of the metal oxide layer 120 with the substrate 100 and oxygen atoms. The material of the transition dielectric layer 160 is silicate, germanium silicate, or germanate.

[0077] Specifically, the metal oxide layer 120 is made of lanthanum oxide, and the transition dielectric layer 160 is made of lanthanum silicate. The flat band voltage generated by the contact between lanthanum silicate and the substrate 100 is negative, thereby increasing the range of adjustable flat band voltage offset through the transition dielectric layer 160 and the subsequent second gate dielectric layer, and correspondingly increasing the range of adjustable threshold voltage offset.

[0078] In other embodiments, based on the material of the actual metal oxide layer, the material of the transition dielectric layer may also be cerium silicate, aluminum silicate, manganese silicate, or magnesium silicate. In still other embodiments, based on the actual substrate material and the material of the metal oxide layer, the material of the transition dielectric layer may also be the corresponding germanium silicate or germanate.

[0079] It should be noted that during the heat treatment 200 of the metal oxide layer 120, in order to avoid the metal oxide layer 120 reacting with the substrate 100 to form metal silicide, the oxygen partial pressure of the oxygen-containing atmosphere should not be too low. Therefore, in the actual process, it is necessary to reasonably set the oxygen partial pressure conditions based on the actual process.

[0080] It should also be noted that, in this embodiment, the heat treatment 200 of the metal oxide layer 120 in an oxygen-containing atmosphere is also suitable for causing the metal atoms 170 in the metal oxide layer 120 to diffuse into the interface layer 150.

[0081] Metal atoms 170 in the metal oxide layer 120 diffuse into the interface layer 150, thereby allowing metal atoms to precipitate at the interface between the interface layer 150 and the subsequent first gate dielectric layer, forming an electric dipole layer. The electric dipole layer can also play a role in regulating the threshold voltage of the device.

[0082] In this embodiment, the oxygen-containing atmosphere includes an oxygen source gas, which includes one or more of oxygen and water vapor. As an example, the metal oxide layer 120 is heat-treated 200 in an oxygen atmosphere.

[0083] In addition to the oxygen source gas, the oxygen-containing atmosphere may also include one or more of hydrogen, argon, and nitrogen to adjust the oxygen ratio and thus regulate the oxygen partial pressure.

[0084] The temperature of the heat treatment 200 should not be too low or too high. If the temperature of the heat treatment 200 is too low, the reaction between the metal oxide layer 120 and the substrate 100 may be insufficient; if the temperature of the heat treatment 200 is too high, it may adversely affect the performance of the device. Therefore, in this embodiment, the temperature of the heat treatment 200 is 600°C to 1200°C.

[0085] In this embodiment, the heat treatment 200 includes an annealing process. As an example, the annealing process is performed using a rapid thermal annealing (RTA) process.

[0086] refer to Figure 9 After heat treatment 200 on the metal oxide layer 120, the capping layer 140 is removed. Removing the capping layer 140 facilitates subsequent processes.

[0087] In this embodiment, the process for removing the capping layer 140 includes one or both of dry etching and wet etching. As an example, a wet etching process is used to remove the capping layer 140.

[0088] Continue to refer to Figure 9 After removing the cover layer 140, the interface layer 150 of the first region 100a is used to form a first gate dielectric stack 310 with the first gate dielectric layer 210, and the transition dielectric layer 160 of the second region 100b is used to form a second gate dielectric stack 320 with the second gate dielectric layer 220.

[0089] Subsequently, a gate electrode layer is formed on the first gate dielectric stack 310 and the second gate dielectric stack 320. The first gate dielectric stack 310 is used to achieve electrical isolation between the gate electrode layer and the channel of the first region 100a, and the second gate dielectric stack 320 is used to achieve electrical isolation between the gate electrode layer and the channel of the second region 100b.

[0090] In this embodiment, in the same step, an interface layer 150 and a transition dielectric layer 160 are formed between the substrate 100 and the metal oxide layer 120 in the first region 100a, and a transition dielectric layer 160 is formed between the substrate 100 and the metal oxide layer 120 in the second region 100b. The transition dielectric layer 160 also enables direct contact between the second gate dielectric layer 220 and the substrate 100, resulting in different flat-band voltage offsets caused by the second gate dielectric stack 320 and the first gate dielectric stack 310. By adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, thereby obtaining devices with multiple threshold voltage types to meet the demand for diversified threshold voltages as device sizes continue to shrink.

[0091] Specifically, the first gate dielectric stack 310 and the second gate dielectric stack 320 are located in the gate opening, thereby reducing the number of film layers formed in the gate opening and reducing the difficulty of adjusting the threshold voltage.

[0092] In this embodiment, after removing the cover layer 140, the transition dielectric layer 160 and the remaining metal oxide layer 120, which are sequentially stacked on the interface layer 150, are used to form the first gate dielectric layer 210, and the remaining metal oxide layer 120 in the second region 100b is used as the second gate dielectric layer 220.

[0093] Accordingly, in this embodiment, there is no need to perform the additional step of removing the metal oxide layer 120 or the transition dielectric layer 160 of the first region 100a, nor is it necessary to form the first gate dielectric layer and the second gate dielectric layer, which helps to simplify the process.

[0094] In this embodiment, the forming method further includes: after forming the first gate dielectric stack 310 and the second gate dielectric stack 320, forming a gate electrode layer (not shown) on the first gate dielectric stack 310 and the second gate dielectric stack 320, wherein the gate electrode layer and the first gate dielectric stack 310 are used to form a first gate structure, and the gate electrode layer and the second gate dielectric stack 320 are used to form a second gate structure.

[0095] Specifically, the gate electrode layer may include a work function metal layer and a metal electrode layer. By adjusting the material, thickness, and number of stacked layers of the work function layer, it can be paired with the first gate dielectric stack 310 and the second gate dielectric stack 320 to further adjust the threshold voltage of the device.

[0096] Figures 10 to 11 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment will not be repeated here. The differences between this embodiment and the previous embodiment are as follows:

[0097] The method for forming the semiconductor structure further includes:

[0098] like Figure 10 As shown, after removing the capping layer, the remaining metal oxide layer is removed, or the remaining metal oxide layer and a portion of the thickness of the transition dielectric layer 160 are removed.

[0099] like Figure 11 As shown, a high-k dielectric layer 180 is formed on the transition dielectric layer 160. The transition dielectric layer 160 and the high-k dielectric layer 180 are stacked sequentially on the interface layer 150 to form the first gate dielectric layer 210a. The high-k dielectric layer 180 in the second region 100b is used as the second gate dielectric layer 220a.

[0100] By removing the remaining metal oxide layer and then forming the high-k dielectric layer 180, different materials of the high-k dielectric layer 180 can be selected according to actual process requirements, thereby making the threshold voltage offset that the gate dielectric stack can adjust more flexibly.

[0101] Accordingly, in this embodiment, the first gate dielectric stack 310a includes an interface layer 150, a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320a includes a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially.

[0102] In this embodiment, the material of the high-k dielectric layer 180 includes HfO2, La2O3, CeO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, or TiO2.

[0103] As an example, the high-k dielectric layer 180 is made of HfO2, a commonly used high-k dielectric material in semiconductor processes, which improves process compatibility. Furthermore, HfO2 has a positive flat-band voltage with a high absolute value, which facilitates its coordination with the transition dielectric layer 160 and the interface layer 150 to achieve a wider adjustment range for the threshold voltage offset. In this embodiment, the process for forming the high-k dielectric layer 180 includes electron beam evaporation or atomic layer deposition.

[0104] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0105] Figures 12 to 13 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0106] The method for forming the semiconductor structure further includes:

[0107] like Figure 12 As shown, after removing the capping layer, the remaining metal oxide layer and the transition medium layer of the first region 100a are removed.

[0108] like Figure 13 As shown, a high-k dielectric layer 180 is formed on the interface layer 150 of the first region 100a and the transition dielectric layer 160 of the second region 100b. The high-k dielectric layer 180 of the first region 100a is used as the first gate dielectric layer 210b, and the high-k dielectric layer 180 of the second region 100b is used as the second gate dielectric layer 220b.

[0109] The remaining metal oxide layer and the transition dielectric layer of the first region 100a are removed, and the high-k dielectric layer 180 is formed to obtain a gate dielectric stack combination different from that in the previous embodiment.

[0110] Accordingly, the first gate dielectric stack 310b includes an interface layer 150 and a high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320b includes a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially.

[0111] In the process of removing the transition medium layer in the first region 100a, a portion of the thickness of the transition medium layer 160 in the second region 100b can also be removed.

[0112] In this embodiment, the material of the high-k dielectric layer 180 includes HfO2, La2O3, CeO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, or TiO2.

[0113] As an example, the high-k dielectric layer 180 is made of HfO2. HfO2 is a commonly used high-k dielectric material in semiconductor processes, which is beneficial for improving process compatibility. Furthermore, HfO2 has a positive flat-band voltage and a high absolute value of the flat-band voltage, which is beneficial for cooperating with the transition dielectric layer 160 and the interface layer 150 to obtain a larger adjustment range of the threshold voltage offset.

[0114] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0115] Figure 14 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:

[0116] like Figure 14 As shown, the forming method further includes: after removing the capping layer, forming a high-k dielectric layer 180 on the metal oxide layer 120, and the transition dielectric layer 160, the metal oxide layer 120 and the high-k dielectric layer 180 sequentially stacked on the interface layer 150 to serve as the first gate dielectric layer 210c, and the metal oxide layer 120 and the high-k dielectric layer 180 in the second region 100b to serve as the second gate dielectric layer 220c.

[0117] By retaining the metal oxide layer 120 and then forming a high-k dielectric layer 180 on the metal oxide layer 120, different gate dielectric stack combinations are obtained, thereby obtaining different types of threshold voltages.

[0118] Accordingly, in this embodiment, the first gate dielectric stack 310c includes an interface layer 150, a transition dielectric layer 160, a metal oxide layer 120 and the high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320c includes a transition dielectric layer 160, a metal oxide layer 120 and the high-k dielectric layer 180 stacked sequentially.

[0119] In actual processes, depending on the specific requirements, a portion of the metal oxide layer 120 can be removed before forming the high-k dielectric layer 180.

[0120] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0121] Accordingly, the present invention also provides a semiconductor structure. Figure 9 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0122] In this embodiment, the semiconductor structure includes: a substrate 100, including a discrete first region 100a and a second region 100b; a first gate dielectric stack 310, located on the substrate 100 of the first region 100a, the first gate dielectric stack 310 including an interface layer 150 and a first gate dielectric layer 210 located on the interface layer 150; and a second gate dielectric stack 320, located on the substrate 100 of the second region 100b, the second gate dielectric stack 320 including a transition dielectric layer 160 and a second gate dielectric layer 220 located on the transition dielectric layer 160, the transition dielectric layer 160 being formed by heat-treating a metal oxide layer 120 in an oxygen-containing atmosphere, causing the metal oxide layer 120 to react with the substrate 100.

[0123] In this embodiment, an interface layer 150 is provided between the substrate 100 of the first region 100a and the first gate dielectric layer 210, and a transition dielectric layer 160 is formed between the substrate 100 of the second region 100b and the second gate dielectric layer 220. The transition dielectric layer 160 enables direct contact between the second gate dielectric layer 220 and the substrate 100, thereby making the flat band voltage offset caused by the second gate dielectric stack 220 and the first gate dielectric stack 210 different. By adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, thereby obtaining devices with multiple threshold voltage types to meet the demand for diversified threshold voltages of devices as device size continues to shrink.

[0124] The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0125] In this embodiment, the substrate 100 of the first region 100a and the second region 100b is also used as a channel for different devices. Accordingly, both the first region 100a and the second region 100b are channel regions.

[0126] As an example, the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a three-dimensional substrate, for example, when forming a fin field-effect transistor, the substrate includes a substrate and fins located on the substrate.

[0127] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of silicon germanide, germanium, or silicon carbide.

[0128] The semiconductor structure typically further includes a gate electrode layer (not shown) located on the first gate dielectric stack 310 and the second gate dielectric stack 320. The first gate dielectric stack 310 is used to achieve electrical isolation between the gate electrode layer and the channel of the first region 100a, and the second gate dielectric stack 320 is used to achieve electrical isolation between the gate electrode layer and the channel of the second region 100b.

[0129] In this embodiment, the film layers contained in the first gate dielectric stack 310 and the second gate dielectric stack 320 are different, which makes the flat band voltage offset caused by the second gate dielectric stack 320 and the first gate dielectric stack 310 different. Thus, by adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, and devices with multiple threshold voltage types can be obtained to meet the needs of diversified threshold voltage of devices as device size continues to shrink. It also helps to reduce the difficulty of adjusting the threshold voltage.

[0130] In the first gate dielectric stack 310, the interface layer 150 is used to improve the interface quality of the substrate 100 surface of the first region 100a, thereby improving the carrier mobility.

[0131] The interface layer 150 is formed by oxidation of the surface of the substrate 100. In this embodiment, the material of the substrate 100 is silicon, and the material of the interface layer 150 is silicon oxide. In other embodiments, depending on the material of the actual substrate, the material of the interface layer may also be silicon germanium oxide, germanium oxide, or carbon-containing silicon oxide.

[0132] In the second gate dielectric stack 320, the transition dielectric layer 160 is used to achieve direct contact between the second gate dielectric layer 220 and the substrate 100, thereby increasing the range of flat band voltage offset caused by the second gate dielectric stack 320, and further increasing the range of adjustable threshold voltage offset.

[0133] The transition medium layer 160 is formed by heat-treating the metal oxide layer 120 in an oxygen-containing atmosphere, thereby causing the metal oxide layer 120 to react with the substrate 100.

[0134] Specifically, during the formation of the semiconductor structure, since a capping layer is formed on the metal oxide layer 120 of the second region 100b, the oxygen partial pressure conditions of the metal oxide layer 120 in the first region 100a and the metal oxide layer 120 in the second region 100b are different during the heat treatment of the metal oxide layer 120 in an oxygen-containing atmosphere. Accordingly, taking advantage of the characteristic that different types of dielectric layers can be formed between the metal oxide layer 120 and the substrate 100 under different oxygen partial pressure conditions, in this embodiment, an interface layer 1 is formed between the substrate 100 and the metal oxide layer 120 in the first region 100a in the same step. A stack of 50 and transition dielectric layer 160 is formed, and a transition dielectric layer 160 is formed between the substrate 100 and the metal oxide layer 120 in the second region 100b. The transition dielectric layer 160 also enables direct contact between the second gate dielectric layer 220 and the substrate 100, thereby making the flat band voltage offset caused by the second gate dielectric stack 320 different from that caused by the first gate dielectric stack 310. In this way, by adjusting the gate dielectric stack, the threshold voltage of the device can be adjusted, and devices with multiple threshold voltage types can be obtained to meet the demand for diversified threshold voltage of devices as device size continues to shrink.

[0135] The first gate dielectric layer 210 is used in conjunction with the interface layer 150 to adjust the threshold voltage. The second gate dielectric layer 220 is used in conjunction with the transition dielectric layer 160 to adjust the threshold voltage.

[0136] In this embodiment, the first gate dielectric layer 210 includes a transition dielectric layer 160 and the metal oxide layer 120 located on the transition dielectric layer 160, and the second gate dielectric layer 220 includes the metal oxide layer 120.

[0137] During the formation of the semiconductor structure, the metal oxide layer 120 is heat-treated in an oxygen-containing atmosphere to react with the substrate 100, thereby forming the interface layer 150 and the transition dielectric layer 160 stacked sequentially in the first region 100a, and the transition dielectric layer 160 is formed on the second region 100b.

[0138] Specifically, during the heat treatment of the metal oxide layer 120 in an oxygen-containing atmosphere, oxygen atoms diffuse to the interface between the metal oxide layer 120 and the substrate 100, thereby reacting with both the metal oxide layer 120 and the substrate 100. The difference in the total amount of oxygen atoms in contact with the metal oxide layer 120 and the substrate 100 results in different dielectric layers forming at the interface between them.

[0139] In this embodiment, the metal oxide layer 120 and the transition dielectric layer 150 of the first region 100a are retained in the semiconductor structure to serve as the first gate dielectric layer 210, and the metal oxide layer 120 of the second region 100b is retained to serve as the second gate dielectric layer 220. Therefore, there is no need to perform the additional step of removing the metal oxide layer 120 or the transition dielectric layer 160 of the first region 100a, nor is it necessary to form the first gate dielectric layer and the second gate dielectric layer, which is beneficial to simplifying the process.

[0140] In this embodiment, the dielectric constant of the metal oxide layer 120 material is greater than that of silicon oxide. Since the dielectric constant of the metal oxide layer 120 material is relatively high, the remaining metal oxide layer 120 can still be retained to form a gate dielectric layer.

[0141] In this embodiment, the material of the metal oxide layer 120 includes lanthanum oxide, cerium oxide, aluminum oxide, manganese oxide, or magnesium oxide. During heat treatment of the metal oxide layer 120, under different oxygen partial pressures, the type of dielectric layer formed by the reaction of the metal oxide layer 120 with the substrate 100 differs. Therefore, the properties of the metal oxide layer 120 material can be utilized to form different dielectric stacks between the substrate 100 and the metal oxide layer 120 in different regions within the same step.

[0142] When the metal oxide layer 120 is made of lanthanum oxide or cerium oxide, the flat band voltage generated by lanthanum oxide and cerium oxide with the substrate 100 is negative. Therefore, after heat treatment to form the transition dielectric layer 160, the range of the adjusted flat band voltage offset can be increased through the transition dielectric layer 160 and the first gate dielectric layer 210. This is beneficial to increasing the range of the adjusted threshold voltage offset. Moreover, lanthanum oxide and cerium oxide are both high-k dielectric materials with high dielectric constants, which is beneficial to enable the metal oxide layer 120 and the formed transition dielectric layer 160 to serve as high-k gate dielectric layers.

[0143] In this embodiment, lanthanum oxide is used as an example material for the metal oxide layer 120. Compared with cerium oxide, lanthanum oxide has a larger absolute value of the flat band voltage when in direct contact with the substrate 100. Therefore, by selecting lanthanum oxide as the material of the metal oxide layer 120, it is beneficial to further increase the range of the adjustable threshold voltage offset. Moreover, selecting lanthanum oxide material is also beneficial to improving the process compatibility of the metal oxide layer 120.

[0144] In this embodiment, the transition dielectric layer 160 is formed by the reaction of the metal oxide layer 120 with the substrate 100 and oxygen atoms. The material of the transition dielectric layer 160 is silicate, germanium silicate, or germanate.

[0145] Specifically, the metal oxide layer 120 is made of lanthanum oxide, and the transition dielectric layer 160 is made of lanthanum silicate. The flat band voltage generated by the contact between lanthanum silicate and the substrate 100 is negative, thereby increasing the range of adjustable flat band voltage offset through the transition dielectric layer 160 and the subsequent second gate dielectric layer, and correspondingly increasing the range of adjustable threshold voltage offset.

[0146] In other embodiments, based on the material of the actual metal oxide layer, the material of the transition dielectric layer may also be cerium silicate, aluminum silicate, manganese silicate, or magnesium silicate. In still other embodiments, based on the actual substrate material and the material of the metal oxide layer, the material of the transition dielectric layer may also be the corresponding germanium silicate or germanate.

[0147] It should also be noted that the interface layer 150 contains metal atoms, which are formed by the diffusion of metal atoms from the metal oxide layer 120 into the interface layer 150. Specifically, during the heat treatment 200 of the metal oxide layer 120 in an oxygen-containing atmosphere, it is also suitable to allow metal atoms 170 from the metal oxide layer 120 to diffuse into the interface layer 150.

[0148] Metal atoms 170 in the metal oxide layer 120 diffuse into the interface layer 150, thereby metal atoms can be deposited at the interface between the interface layer 150 and the first gate dielectric layer 210 to form an electric dipole layer, which can also play the role of regulating the threshold voltage of the device.

[0149] The semiconductor structure further includes a gate electrode layer (not shown) located on the first gate dielectric stack 310 and the second gate dielectric stack 320. The gate electrode layer and the first gate dielectric stack 310 are used to form a first gate structure, and the gate electrode layer and the second gate dielectric stack 320 are used to form a second gate structure.

[0150] Specifically, the gate electrode layer may include a work function metal layer and a metal electrode layer. By adjusting the material, thickness, and number of stacked layers of the work function layer, it can be paired with the first gate dielectric stack 310 and the second gate dielectric stack 320 to further adjust the threshold voltage of the device.

[0151] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0152] Figure 11This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated. The differences between this embodiment and the foregoing embodiments are as follows:

[0153] The first gate dielectric layer 210a includes a transition dielectric layer 160 and a high-k dielectric layer 180 located on the transition dielectric layer 160, and the second gate dielectric layer 220a is the high-k dielectric layer 180.

[0154] In this embodiment, during the formation of the semiconductor structure, after heat treatment, the remaining metal oxide layer is removed, and a high-k dielectric layer 180 is formed. This allows for the selection of high-k dielectric layers 180 made of different materials according to actual process requirements, thereby making the threshold voltage offset that the gate dielectric stack can adjust more flexibly.

[0155] Accordingly, in this embodiment, the first gate dielectric stack 310a includes an interface layer 150, a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320a includes a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially.

[0156] In this embodiment, the material of the high-k dielectric layer 180 includes HfO2, La2O3, CeO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, or TiO2.

[0157] As an example, the high-k dielectric layer 180 is made of HfO2. HfO2 is a commonly used high-k dielectric material in semiconductor processes, which is beneficial for improving process compatibility. Furthermore, HfO2 has a positive flat-band voltage and a high absolute value of the flat-band voltage, which is beneficial for cooperating with the transition dielectric layer 160 and the interface layer 150 to obtain a larger adjustment range of the threshold voltage offset.

[0158] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0159] Figure 13 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated. The differences between this embodiment and the foregoing embodiments are as follows:

[0160] In this embodiment, the first gate dielectric layer 210b and the second gate dielectric layer 220b are high-k dielectric layers 180.

[0161] In this embodiment, during the formation of the semiconductor structure, after heat treatment, the remaining metal oxide layer and the transition dielectric layer of the first region 100a are removed, and then the high-k dielectric layer 180 is formed, thereby obtaining a gate dielectric stack combination different from the aforementioned embodiment.

[0162] Accordingly, the first gate dielectric stack 310b includes an interface layer 150 and a high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320b includes a transition dielectric layer 160 and a high-k dielectric layer 180 stacked sequentially.

[0163] In this embodiment, the material of the high-k dielectric layer 180 includes HfO2, La2O3, CeO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, or TiO2.

[0164] As an example, the high-k dielectric layer 180 is made of HfO2. HfO2 is a commonly used high-k dielectric material in semiconductor processes, which is beneficial for improving process compatibility. Furthermore, HfO2 has a positive flat-band voltage and a high absolute value of the flat-band voltage, which is beneficial for cooperating with the transition dielectric layer 160 and the interface layer 150 to obtain a larger adjustment range of the threshold voltage offset.

[0165] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0166] Figure 14 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between this embodiment and the foregoing embodiments will not be repeated. The differences between this embodiment and the foregoing embodiments are as follows:

[0167] In this embodiment, the first gate dielectric layer 210c includes a transition dielectric layer 160, the metal oxide layer 120 and a high-k dielectric layer 180 stacked sequentially, and the second gate dielectric layer 220c includes the metal oxide layer 120 and the high-k dielectric layer 180 stacked sequentially.

[0168] In this embodiment, during the formation of the semiconductor structure, the metal oxide layer 120 is retained, and a high-k dielectric layer 180 is formed on the metal oxide layer 120 to obtain different gate dielectric stack combinations, thereby obtaining different types of threshold voltages.

[0169] Accordingly, in this embodiment, the first gate dielectric stack 310c includes an interface layer 150, a transition dielectric layer 160, a metal oxide layer 120 and the high-k dielectric layer 180 stacked sequentially, and the second gate dielectric stack 320c includes a transition dielectric layer 160, a metal oxide layer 120 and the high-k dielectric layer 180 stacked sequentially.

[0170] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0171] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base, comprising a discrete first region and a second region; A metal oxide layer is formed on the substrate in the first and second regions; A capping layer is formed on the metal oxide layer in the second region, exposing the metal oxide layer in the first region; The metal oxide layer is heat-treated in an oxygen-containing atmosphere to react with the substrate to form an interface layer and a transition medium layer stacked sequentially between the substrate and the metal oxide layer in the first region, and a transition medium layer between the substrate and the metal oxide layer in the second region. After heat treatment of the metal oxide layer, the covering layer is removed; After the cover layer is removed, the interface layer of the first region is used to form a first gate dielectric stack with the first gate dielectric layer, and the transition dielectric layer of the second region is used to form a second gate dielectric stack with the second gate dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the cover layer, the transition dielectric layer and the remaining metal oxide layer, which are stacked sequentially on the interface layer, are used to form the first gate dielectric layer, and the remaining metal oxide layer in the second region is used as the second gate dielectric layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after removing the capping layer, removing the remaining metal oxide layer, or removing the remaining metal oxide layer and a portion of the thickness of the transition dielectric layer; forming a high-k dielectric layer on the transition dielectric layer; the transition dielectric layer and the high-k dielectric layer sequentially stacked on the interface layer to form the first gate dielectric layer; and the high-k dielectric layer in the second region to serve as the second gate dielectric layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after removing the capping layer, removing the remaining metal oxide layer and the transition dielectric layer of the first region; forming a high-k dielectric layer on the interface layer of the first region and the transition dielectric layer of the second region, wherein the high-k dielectric layer of the first region is used as the first gate dielectric layer and the high-k dielectric layer of the second region is used as the second gate dielectric layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after removing the capping layer, forming a high-k dielectric layer on the metal oxide layer, wherein the transition dielectric layer, the metal oxide layer and the high-k dielectric layer are sequentially stacked on the interface layer to serve as the first gate dielectric layer, and the metal oxide layer and the high-k dielectric layer in the second region serve as the second gate dielectric layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the transition medium layer is silicate, germanic silicate, or germanate.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the metal oxide layer, the material of the metal oxide layer includes lanthanum oxide, cerium oxide, aluminum oxide, manganese oxide, or magnesium oxide.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Heat treatment of the metal oxide layer in an oxygen-containing atmosphere is also suitable for causing metal atoms in the metal oxide layer to diffuse into the interface layer.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The oxygen-containing atmosphere includes an oxygen source gas, which includes one or more of oxygen and water vapor.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The heat treatment temperature is between 600°C and 1200°C.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a sacrificial oxide layer is also formed on the surface of the substrate; The method for forming the semiconductor structure further includes: after providing the substrate and before forming the metal oxide layer, removing the sacrificial oxide layer on the substrate surface of the first region and the second region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After providing the substrate, and before removing the sacrificial oxide layer on the substrate surface of the first and second regions, the method for forming the semiconductor structure further includes: forming a dummy gate structure on the sacrificial oxide layer of the first and second regions; forming an interlayer dielectric layer on the substrate at the side of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer to expose the sacrificial oxide layer; In the step of removing the sacrificial oxide layer on the substrate surface of the first region and the second region, the sacrificial oxide layer exposed by the gate opening is removed; In the step of forming the metal oxide layer, the metal oxide layer is formed on the substrate at the bottom of the gate opening.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after forming a first gate dielectric stack and a second gate dielectric stack, forming a gate electrode layer on the first gate dielectric stack and the second gate dielectric stack, wherein the gate electrode layer and the first gate dielectric stack are used to form a first gate structure, and the gate electrode layer and the second gate dielectric stack are used to form a second gate structure.

14. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure as described in any one of claims 1-13, comprising: The base comprises a separate first region and a second region; A first gate dielectric stack is located on the substrate of the first region, and the first gate dielectric stack includes an interface layer and a first gate dielectric layer located on the interface layer. The second gate dielectric stack is located on the substrate of the second region. The second gate dielectric stack includes a transition dielectric layer and a second gate dielectric layer located on the transition dielectric layer. The transition dielectric layer is formed by heat-treating a metal oxide layer in an oxygen-containing atmosphere to react the metal oxide layer with the substrate.

15. The semiconductor structure as described in claim 14, characterized in that, The material of the transition medium layer is silicate, germanic silicate, or germanate.

16. The semiconductor structure as claimed in claim 14, characterized in that, The first gate dielectric layer includes a transition dielectric layer and the metal oxide layer located on the transition dielectric layer, and the second gate dielectric layer includes the metal oxide layer.

17. The semiconductor structure as claimed in claim 14, characterized in that, The first gate dielectric layer includes a transition dielectric layer and a high-k dielectric layer located on the transition dielectric layer, and the second gate dielectric layer is a high-k dielectric layer.

18. The semiconductor structure as described in claim 14, characterized in that, The first gate dielectric layer and the second gate dielectric layer are high-k dielectric layers.

19. The semiconductor structure as claimed in claim 14, characterized in that, The first gate dielectric layer includes a transition dielectric layer, the metal oxide layer and a high-k dielectric layer stacked sequentially, and the second gate dielectric layer includes the metal oxide layer and the high-k dielectric layer stacked sequentially.

20. The semiconductor structure as described in claim 17, 18, or 19, characterized in that, The high-k dielectric layer is made of materials including HfO2, La2O3, CeO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, or TiO2.

21. The semiconductor structure as described in claim 14, characterized in that, The materials of the metal oxide layer include lanthanum oxide, cerium oxide, aluminum oxide, manganese oxide, or magnesium oxide.

22. The semiconductor structure as described in claim 14, characterized in that, The interface layer contains metal atoms, which are formed by the diffusion of metal atoms from the metal oxide layer into the interface layer.

23. The semiconductor structure as described in claim 14, characterized in that, The semiconductor structure further includes: a gate electrode layer located on the first gate dielectric stack and the second gate dielectric stack, wherein the gate electrode layer and the first gate dielectric stack are used to form a first gate structure, and the gate electrode layer and the second gate dielectric stack are used to form a second gate structure.

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