A split-gate flash memory cell and a method for manufacturing the same

Abstract

The present invention provides a split-gate flash memory cell and a method for manufacturing the same, including: a substrate, a source line formed on the substrate, and two storage bits. The two storage bits are symmetrically arranged, and the source line is located between the two storage bits; each storage bit includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The erase gate includes a first portion and a second portion. The first portion extends in the horizontal direction. The second portion extends in the vertical direction; the word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the side wall of the first portion away from the source line. Dividing the erase gate into two parts effectively reduces the size of the device. At the same time, the setting of the erase gate can reduce the threshold voltage of the split-gate flash memory cell, enabling read operations under low voltage conditions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a split-gate flash memory cell and a method for manufacturing the same. Background Art

[0002] Flash memory has the advantages of high storage density, good reliability, and portability. Therefore, since its inception, flash memory has been widely used in mobile and communication devices such as mobile phones, laptops, and USB flash drives. Flash memory generally includes two structures: a stacked gate and a split gate structure. Currently, the split gate structure is more widely used. As the size of semiconductor devices continues to decrease, the existing split-gate flash memory generally has problems of large area and excessive source line resistance. Summary of the Invention

[0003] The purpose of the present invention is to provide a split-gate flash memory cell and a method for manufacturing the same, so as to solve the problems of large cell area and high read voltage of the existing split-gate flash memory cell.

[0004] To achieve the above purpose, the present invention provides a split-gate flash memory cell, including:

[0005] A substrate, a source line formed on the substrate, and two memory bits. The two memory bits are symmetrically arranged, and the source line is located between the two memory bits;

[0006] Each memory bit includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first part and a second part. The first dielectric layer covers the floating gate, the second dielectric layer covers a part of the first dielectric layer, the first part covers the second dielectric layer, the second part covers the remaining part of the first dielectric layer and extends upward to cover the sidewalls of the second dielectric layer and the first part, and the second part is located on the side close to the source line;

[0007] The word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the sidewalls of the first part away from the source line.

[0008] Optionally, each memory bit further includes:

[0009] A first sidewall, covering at least the second part, the first dielectric layer, and the sidewalls of the floating gate close to the source line;

[0010] A second sidewall, located on the first part;

[0011] A third sidewall that at least covers the first portion, the first dielectric layer, the second dielectric layer, and the sidewalls of the floating gate on the side away from the source line;

[0012] A fourth sidewall that at least covers the word line gate and the sidewalls of the tunneling oxide layer on the side away from the source line.

[0013] Optionally, the first dielectric layer includes a first oxide layer, and the second dielectric layer includes a nitride layer and a second oxide layer covering the nitride layer.

[0014] Optionally, the split-gate flash memory cell further includes:

[0015] A source region located in the substrate at the bottom of the source line, and the source region has an overlapping portion with each floating gate in the horizontal direction;

[0016] Two drain regions are respectively located in the substrate at the bottom of each word line gate layer, and each tunneling oxide layer covers a partial region of the corresponding drain region;

[0017] A plurality of plugs are respectively electrically connected to the source line, the word line gate, and the drain region, and respectively lead out the source line, the word line gate, and the drain region.

[0018] Optionally, the split-gate flash memory cell performs a programming operation by using a hot electron injection method, performs an erasing operation by using the F-N tunneling effect of electrons between the floating gate and the second portion of the erase gate, and performs a read operation by using channel inversion turn-on.

[0019] Optionally, the thickness of the tunneling oxide layer is

[0020] Optionally, the length of the floating gate in the horizontal direction is

[0021] Based on the same inventive concept, the present invention further provides a method for manufacturing a split-gate flash memory cell, including:

[0022] Providing a substrate, a source line and two memory bits are formed on the substrate, the two memory bits are symmetrically arranged, and the source line is located between the two memory bits;

[0023] Each of the storage bits includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first portion and a second portion. The first dielectric layer covers the floating gate. The second dielectric layer covers a part of the first dielectric layer. The first portion covers the second dielectric layer. The second portion covers the remaining part of the first dielectric layer and extends upward to cover the sidewalls of the second dielectric layer and the first portion, and the second portion is located on the side close to the source line;

[0024] The word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the sidewalls of the first portion away from the source line.

[0025] Optionally, the steps of forming the storage bit include:

[0026] Form a stacked layer on the substrate, the stacked layer includes a floating gate material layer, a first dielectric material layer, a second dielectric material layer, a first erase gate material layer, and a hard mask layer sequentially stacked on the substrate;

[0027] Etch the hard mask layer, the first erase gate material layer, and the second dielectric material layer in sequence to form an opening;

[0028] Form a second erase gate material layer on partial sidewalls on both sides of the opening, and the second erase gate material layer constitutes the second portion;

[0029] Continue to etch the first dielectric material layer and the floating gate material layer along the opening to make the opening extend downward to expose the substrate;

[0030] Fill the opening with source line material to form the source line;

[0031] After removing the hard mask layer, continue to etch the first erase gate material layer, the second dielectric material layer, the first dielectric material layer, and the floating gate material layer downward in sequence until the substrate is exposed. The remaining first erase gate material layer, second dielectric material layer, first dielectric material layer, and floating gate material layer respectively constitute the first portion, the second dielectric layer, the first dielectric layer, and the floating gate.

[0032] Optionally, after etching to form the opening until the substrate is exposed and before forming the source line material layer, it further includes:

[0033] Perform a first ion implantation process on the substrate in the opening to form a source region in the substrate in the opening.

[0034] Optionally, the step of sequentially etching the hard mask layer, the first erase gate material layer, and the second dielectric material layer to form the opening includes:

[0035] Etch the hard mask layer to form the opening, and form second sidewalls on the sidewalls on both sides of the opening;

[0036] Using the second sidewalls as a mask, continue to etch the first erase gate material layer and the second dielectric material layer along the opening, so that the opening extends downward to expose the first dielectric material layer.

[0037] Optionally, after continuing to etch the first dielectric material layer and the floating gate material layer along the opening, and before filling the opening with source line material to form the source line, the step of forming the storage bit further includes:

[0038] Form first sidewalls on partial sidewalls on both sides of the opening, and the first sidewalls cover at least the sidewalls of the second part, the first dielectric material layer, and the floating gate material layer; and,

[0039] After forming the first part, the second dielectric layer, the first dielectric layer, and the floating gate layer, form third sidewalls on at least the sidewalls of the first part, the second dielectric layer, the first dielectric layer, and the floating gate layer on the side away from the source line.

[0040] Optionally, after forming the first part, the second dielectric layer, the first dielectric layer, and the floating gate layer, the step of forming the storage bit further includes:

[0041] Form a tunneling oxide material layer and a word line material layer on the substrate in sequence;

[0042] Etch the word line material layer and the tunneling oxide material layer in sequence until the substrate is exposed, and the remaining tunneling oxide material layer and word line gate material layer respectively constitute the tunneling oxide layer and the word line gate.

[0043] Optionally, after forming the tunneling oxide layer and the word line gate, the step of forming the storage bit further includes:

[0044] Form fourth sidewalls on the sidewalls of the word line gate and the tunneling oxide layer on the side away from the source line.

[0045] Optionally, after forming the third sidewalls, further includes:

[0046] Perform a second ion implantation process on the substrate outside the third sidewalls to form two drain regions in the substrate.

[0047] Optionally, after forming the drain regions, further includes:

[0048] Plugs are respectively formed on the source line, the word line gate and the drain region. The plugs are respectively electrically connected to the source line, the word line gate and the drain region, and respectively lead out the source line, the word line gate and the drain region.

[0049] The present invention provides a split-gate flash memory cell and a preparation method thereof, including: a substrate and a source line and two memory bits formed on the substrate. The two memory bits are symmetrically arranged, and the source line is located between the two memory bits; each memory bit includes a floating gate, a gate dielectric layer, an erase gate, a word line gate and a tunneling oxide layer. The floating gate, the gate dielectric layer and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first part and a second part. The first dielectric layer covers the floating gate, the second dielectric layer covers part of the first dielectric layer, the first part covers the second dielectric layer, the second part covers the remaining part of the first dielectric layer and extends upward to cover the side walls of the second dielectric layer and the first part, and the second part is located on the side close to the source line; the word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the side walls of the first part far from the source line. When the split-gate flash memory cell performs an erase operation, electrons are transferred from the floating gate to the erase gate without the participation of the word line gate. Therefore, the tunneling oxide layer will not be subjected to electron tunneling during the erase operation, and thus the thickness of the tunneling oxide layer can be thinned to reduce the threshold voltage, so that the split-gate flash memory cell can perform a read operation under low voltage conditions and reduce the read error. In addition, by dividing the erase gate into two parts, the length of the erase gate in the horizontal direction can be reduced, effectively reducing the size of the device. Description of the Drawings

[0050] Figure 1 is a flowchart of a preparation method of a split-gate flash memory cell provided by an embodiment of the present invention;

[0051] Figures 2 to 19 is a schematic structural diagram corresponding to the corresponding steps of a preparation method of a split-gate flash memory cell provided by an embodiment of the present invention;

[0052] Among them, the description of the drawings is as follows:

[0053] A - storage area; B - logic area;

[0054] 100 - substrate; 101 - third oxide layer; 102 - floating gate material layer; 103 - first oxide layer (first dielectric layer); 104 - nitride layer; 105 - second oxide layer; 106 - first erase gate material layer; 107 - fourth oxide layer; 109 - fifth oxide layer;

[0055] 300 - Hard mask layer; 301 - First part; 302 - Second part; 303 - Floating gate; 304 - First dielectric layer; 305 - Second dielectric layer; 306 - Source line; 307 - Erase gate; 308 - Word line gate; 309 - Tunneling oxide layer; 310 - Logic gate; 311 - Self - aligned metal layer; 312 - Plug

[0056] 41 - Opening

[0057] 50 - First sidewall; 51 - Second sidewall; 52 - Third sidewall; 53 - Fourth sidewall; 54 - Fifth sidewall

[0058] 60 - First doping region; 61 - Source region; 62 - Second doping region; 65 - Drain region; 63 - Logic gate source region; 64 - Logic gate drain region Detailed implementation manners

[0059] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention

[0060] In the following text, terms such as "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that, under appropriate circumstances, these terms used in this way can be replaced. Similarly, if the methods described herein include a series of steps, and the steps presented herein are not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described in the text can be added to the method

[0061] Figure 19 The structural schematic diagram of the split - gate flash memory cell provided in this embodiment is as shown Figure 19 As shown, this embodiment provides a split - gate flash memory cell, including: a substrate 100, a source line 306 formed on the substrate 100, and two memory bits. The two memory bits are symmetrically arranged, and the source line 306 is located between the two memory bits. Wherein, each memory bit includes a floating gate 303, a gate dielectric layer, an erase gate 307, a word line gate 308, and a tunneling oxide layer 309

[0062] Specifically, the floating gate 303, the gate dielectric layer, and the erase gate 307 are sequentially stacked on the substrate 100. The gate dielectric layer includes a first dielectric layer 304 and a second dielectric layer 305. The first dielectric layer 304 includes a first oxide layer, and the second dielectric layer 305 includes a nitride layer and a second oxide layer covering the nitride layer. The erase gate 307 includes a first portion 301 and a second portion 302. The first dielectric layer 304 covers the floating gate 303, the second dielectric layer 305 covers a part of the first dielectric layer 304, the first portion 301 covers the second dielectric layer 305, the second portion 302 covers the remaining part of the first dielectric layer 304 and extends upward to cover the sidewalls of the second dielectric layer 305 and the first portion 301, and the second portion 302 is located on the side close to the source line 306. The word line gate 308 and the tunneling oxide layer 309 are sequentially stacked on the substrate 100, and the word line gate 308 extends upward to cover the gate dielectric layer and the sidewalls of the first portion 301 away from the source line 306.

[0063] Wherein, the length of the floating gate 303 in the horizontal direction is The length of the erase gate 307 in the horizontal direction is less than In this embodiment, the erase gate 307 is divided into the first portion 301 extending in the horizontal direction and the second portion 302 extending in the vertical direction, effectively reducing the length of the erase gate 307 in the horizontal direction, and thus reducing the size of the split-gate flash memory cell.

[0064] In addition, each memory bit further includes a first sidewall 50, a second sidewall 51, a third sidewall 52, and a fourth sidewall 53. The first sidewall 51 covers at least the sidewalls of the second portion 302, the first dielectric layer 304, and the floating gate 303 close to the source line 306. The first sidewall 50 isolates the source line 306 from the erase gate 307 and the floating gate 303. The second sidewall 51 is located on the first portion 301. The third sidewall 52 covers at least the sidewalls of the first portion 301, the first dielectric layer 304, the second dielectric layer 305, and the floating gate 303 away from the source line 306. The third sidewall 52 isolates the word line gate 308 from the erase gate 307 and the floating gate 303. The fourth sidewall 53 covers at least the sidewalls of the word line gate 308 and the tunneling oxide layer 309 away from the source line 306.

[0065] Continue to refer to Figure 19, the split-gate flash memory cell provided in this embodiment further includes a first doped region 60, a source region 61, a drain region 62, a self-aligned metal layer 311, and a plurality of plugs 312. The first doped region 60 is located in the substrate 100 at the bottom of the source line 306, and the first doped region 60 overlaps with each floating gate 303 in the horizontal direction; the source region 61 is located in the first doped region 60, and the source region 61 has an overlapping portion with each floating gate 303 in the horizontal direction; the two drain regions 62 are respectively located in the substrate 100 at the bottom of each word line gate 308, and each tunneling oxide layer 309 covers a partial region of the corresponding drain region 62; the self-aligned metal layer 311 is located on the surfaces of the substrate 100 corresponding to the drain region 62, the source line 306, and the word line gate 308, and the plurality of plugs 312 are respectively electrically connected to the source line 306, the word line gate 308, and the drain region 62 through the self-aligned metal layer 311, and lead out the source line 306, the word line gate 308, and the drain region 62 respectively.

[0066] Since the plug 312 is electrically connected to the source line 306 and leads out the source line 306, it is not necessary to form an H-shaped ACT pattern on the substrate 100 to connect the source line 306 to other structures, reducing the complexity of the process, and leading out the source line 306 through the plug 312 can greatly reduce the resistance value of the source line 306.

[0067] The split-gate flash memory cell provided in this embodiment performs a programming operation by means of hot electron injection, an erasing operation by means of F-N tunneling effect, and a reading operation by means of channel inversion turn-on. It should be noted that when the split-gate flash memory cell performs an erasing operation, a high potential difference is formed between the floating gate 303 and the erasing gate 307. By means of the F-N tunneling effect, the first oxide layer acts as a tunneling oxide layer, and electrons are pulled from the floating gate 303 to the erasing gate 307 through the first oxide layer. Figure 19 The position marked by the circle in is the erasing window of the split-gate flash memory cell.

[0068] Since electrons do not pass through the word line gate 308 during the erasing operation in this embodiment, the tunneling oxide layer 309 between the word line gate 308 and the substrate 100 will not be tunneled by electrons during the erasing operation. Therefore, the thickness of the tunneling oxide layer 309 can be reduced from the original to While effectively reducing the device size of the split-gate flash memory cell, the thinning of the thickness of the tunneling oxide layer 309 also reduces the threshold voltage of the split-gate flash memory cell, thereby enabling read operations at a low voltage. Similarly, since the word line gate 308 only controls the floating gate 303 during the erase operation and does not actually participate in the erase operation, the width of the word line gate 308 can also be appropriately reduced to further reduce the size of the split-gate flash memory cell.

[0069] In addition, as Figure 19 shown, the substrate 100 has a storage area A and a logic area B. The source line 306 and the storage bits are both located on the storage area A. Logic devices are formed on the logic area B. The logic devices include a logic gate 310, a logic gate source region 63, and a logic gate drain region 64 within the substrate 100 on both sides of the logic gate 310. And the logic devices can be high-voltage logic devices or low-voltage logic devices, and the present invention does not limit this. The logic area B also has a plurality of plugs 312. The plugs 312 are electrically connected to the logic gate 310, the logic gate source region 63, and the logic gate drain region 64 respectively through the self-aligned metal layer 311, and lead out the logic gate 310, the logic gate source region 63, and the logic gate drain region 64 respectively. There is also a fifth oxide layer 109 between the substrate 100 and the logic gate 310, and there are two fifth sidewalls 54 on the fifth oxide layer 109. The fifth sidewalls 54 cover two sidewalls of the logic gate 310 respectively.

[0070] Figure 1 is a flowchart of a method for manufacturing a split-gate flash memory cell provided in this embodiment. As Figure 1 shown, the present invention provides a method for manufacturing a split-gate flash memory cell, including:

[0071] Step S1: Provide a substrate, on which a source line and two storage bits are formed. The two storage bits are symmetrically arranged, and the source line is located between the two storage bits;

[0072] Step S2: Each storage bit includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first part and a second part. The first dielectric layer covers the floating gate. The second dielectric layer covers part of the first dielectric layer. The first part covers the second dielectric layer. The second part covers the remaining part of the first dielectric layer and extends upward to cover the sidewalls of the second dielectric layer and the first part. And the second part is located on the side close to the source line;

[0073] Step S3: The word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the sidewalls of the first portion away from the source line.

[0074] Figures 2 to 19 FIG. is a schematic structural diagram corresponding to the corresponding steps of a method for manufacturing a split-gate flash memory cell provided in this embodiment. The following will describe in more detail a method for manufacturing a split-gate flash memory cell provided in this embodiment, in which a preferred embodiment of the present invention is illustrated. Figures 2 to 19 FIG. shows a substrate 100 having a storage area A and a logic area B. A stacked layer is formed on the substrate 100. The stacked layer includes a third oxide layer 101, a floating gate material layer 102, a first dielectric material layer, a second dielectric material layer, a first erase gate material layer 106, and a hard mask layer 300 that are sequentially stacked on the substrate 100. Among them, the first dielectric material layer includes a first oxide layer 103, the second dielectric material layer includes a nitride layer 104 and a second oxide layer 105, and the second oxide layer 105 covers the nitride layer 104.

[0075] As Figure 2 shown, a substrate 100 is provided. The substrate has a storage area A and a logic area B. A stacked layer is formed on the substrate 100. The stacked layer includes a third oxide layer 101, a floating gate material layer 102, a first dielectric material layer, a second dielectric material layer, a first erase gate material layer 106, and a hard mask layer 300 that are sequentially stacked on the substrate 100. Among them, the first dielectric material layer includes a first oxide layer 103, the second dielectric material layer includes a nitride layer 104 and a second oxide layer 105, and the second oxide layer 105 covers the nitride layer 104.

[0076] The thickness of the third oxide layer 101 is The thickness of the floating gate material layer 102 is The thickness of the first oxide layer 103 is greater than The thickness of the first erase gate material layer 106 is The thickness of the nitride layer 104 is The thickness of the second oxide layer 105 is greater than The material of the hard mask layer 300 is silicon nitride, and the thickness of the hard mask layer 300 is much greater than the thickness of the first erase gate material layer 106.

[0077] As Figures 3 to 6 shown, the hard mask layer 300 on the storage area A is etched to form an opening 41 exposing the first erase gate material layer 106. Using the opening 41 as a self-alignment window, a third ion implantation process is performed on the first erase gate material layer 106, the second oxide layer 105, the nitride layer 104, the first oxide layer 103, the floating gate material layer 102, the third oxide layer 101, and the substrate 100 within the opening 41 to form a first doped region 60 in the substrate 100. The width of the first doped region 60 is greater than or equal to the width of the opening 41.

[0078] Further, second sidewalls 51 are formed on the sidewalls on both sides of the opening 41, and the second sidewalls 51 cover the sidewalls of the hard mask layer 300. Using the second sidewalls 51 as a mask, the first erasing gate material layer 106 and the second oxide layer 105 are continuously etched along the opening 41 to deepen the opening 41; then the nitride layer 104 in the opening 41 is continuously removed until the first oxide layer 103 is exposed.

[0079] As Figure 7 shown, a second erasing gate material layer is formed on the substrate 100, and the second erasing gate material layer covers the inner wall of the opening 41, the second sidewalls 51, and the hard mask layer 300. The second erasing gate material layer is etched by an anisotropic etching method, and the second erasing gate material layer on a part of the sidewalls of the opening 41 is retained, and the remaining second erasing gate material layer constitutes a second part 302 of the erasing gate. The second part 302 is connected to the first erasing gate material layer 106, and the second part 302 covers at least a part of the second sidewalls 51.

[0080] As Figures 8 to 9 shown, the first oxide layer 103, the floating gate material layer 102, and the third oxide layer 101 in the opening 41 are continuously etched along the opening 41 to deepen the opening 41 until the substrate 100 is exposed. Further, using the opening 41 as a self-alignment window, a first ion implantation process is performed on the first doped region 60 in the opening 41 to form a heavily doped region in the first doped region 60 to constitute a source region 61, and the source region 61 partially overlaps with the floating gate material layer 102 in the horizontal direction.

[0081] As Figure 10 shown, an ONO layer is formed on the substrate 100, and the ONO layer covers the hard mask layer 300, the second sidewalls 51, and the inner wall of the opening 41. Wherein, the ONO layer is a stack of silicon oxide / silicon nitride / silicon oxide, and the thickness of the oxide layer in the ONO layer is The thickness of the silicon nitride in the ONO layer is Then the ONO layer is etched by an anisotropic method, and the remaining ONO layer constitutes a first sidewall 50, and the first sidewall 50 covers at least the sidewalls of the second part 302, the first oxide layer 103, and the floating gate material layer 102.

[0082] As Figure 11As shown, a source line material layer is formed on the substrate 100. The source line material layer fills the opening 41 and extends to cover the hard mask layer 300. A chemical mechanical polishing process is performed on the source line material layer to remove the source line material layer on the hard mask layer 300. The remaining source line material layer constitutes the source line 306. The source line 306 fills a part of the opening 41, and the height of the source line 306 is higher than the height of the second part 302.

[0083] As Figure 12 shown, a fourth oxide layer 107 is formed on the source line 306. The fourth oxide layer 107 can be formed by a thermal oxidation process or a chemical vapor deposition process, and the thickness of the fourth oxide layer 107 is relatively thin. The fourth oxide layer 107 can protect the source line 306 in subsequent processes.

[0084] As Figures 13 to 14 shown, the hard mask layer 300 on the storage area A is removed, and etching is continued downward in sequence through the first erase gate material layer 106, the second dielectric material layer, the first dielectric material layer, the floating gate material layer 102, and the third oxide layer 101 until the substrate 100 is exposed. The remaining first erase gate material layer 106, second dielectric material layer, first dielectric material layer, and floating gate material layer 102 respectively constitute the first part 301, second dielectric layer 305, first dielectric layer 304, and floating gate layer 303. The first dielectric layer 304 and the second dielectric layer 305 constitute a gate dielectric layer.

[0085] Then, a fourth ion implantation process is performed on the substrate 100 on both sides of the floating gate 303 and the erase gate 307 to form two second doped regions 62 in the substrate 100.

[0086] In addition, while removing the stacked layer on the storage area A, the stacked layer on the logic area B is also removed.

[0087] As Figure 15 shown, a third sidewall 52 is formed outside the floating gate 303 and the erase gate 307. The third sidewall 52 covers at least the first part 301, the first dielectric layer 304, the second dielectric layer 305, and the sidewall of the floating gate 303 on the side away from the source line layer 306.

[0088] As Figure 16 shown, a tunneling oxide material layer and a word line material layer are sequentially formed on the substrate 100 of the storage area A. The word line material layer covers the tunneling oxide material layer. The thickness of the tunneling oxide material layer is Etch away part of the tunneling oxide material layer and the word line material layer in sequence until the substrate 100 is exposed. The remaining tunneling oxide material layer and word line gate material layer respectively form the tunneling oxide layer 309 and the word line gate 308, and the word line gate 308 extends upward to cover the gate dielectric layer and the sidewalls of the first portion 301 on the side away from the source line 306.

[0089] As Figure 17 shown, a fifth oxide layer 109 and a logic gate material layer are sequentially formed on the substrate 100 in the logic region B; then, part of the logic gate material layer and the fifth oxide layer 109 are etched away until the substrate 100 is exposed, and the remaining logic gate material layer forms the logic gate 312.

[0090] As Figure 18 shown, fifth sidewalls 54 are formed on both sides of the logic gate 310, and fourth sidewalls 53 are formed on the side of each word line gate 308 away from the source line 306. The fourth sidewalls 53 cover at least the sidewalls of the word line gate 308 and the tunneling oxide layer 309 on the side away from the source line 306. Then, a second ion implantation process is performed on the substrate 100 outside the third sidewalls 54 to form two drain regions 65 in the second doping region 62 respectively; a fourth ion implantation process is performed on the substrate 100 on both sides of the logic gate 312 to form a logic gate source region 63 and a logic gate drain region 64 in the substrate 100 on both sides of the logic gate 312 respectively.

[0091] Among them, the logic gate 310, the logic gate source region 63, and the logic gate drain region 64 constitute a logic device. The logic device can be a high-voltage logic device or a low-voltage logic device. Similarly, the thickness of the fifth oxide layer 109 can be adjusted according to the actual situation.

[0092] In addition, after forming the fourth sidewalls 53 and the fifth sidewalls 54, the fourth oxide layer 107 is removed to expose the top surface of the source line 306.

[0093] As Figure 19 shown, a self-aligned metal layer 311 and plugs 312 are respectively formed on the two drain regions 61, the two word line gates 308, the source line 306, the logic gate 310, the logic gate source region 63, and the logic gate drain region 64. The plugs 312 are electrically connected to the source line 306, the word line gate 308, the drain region 62, the logic gate 310, the logic gate source region 63, and the logic gate drain region 64 respectively through the self-aligned metal layer 311, and the plugs 312 lead out the source line 306, the word line gate 308, the drain region 62, the logic gate 310, the logic gate source region 63, and the logic gate drain region 64 respectively.

[0094] In the manufacturing process of the split-gate flash memory cell provided in this embodiment, the self-alignment process is used in many places, which reduces the complexity of the process, saves costs, and at the same time increases the alignment accuracy of the process, resulting in better device performance.

[0095] In summary, the present invention provides a split-gate flash memory cell and a preparation method thereof, including: a substrate 100, a source line 306 formed on the substrate 100, and two memory bits. The two memory bits are symmetrically arranged, and the source line 306 is located between the two memory bits; each memory bit includes a floating gate 303, a gate dielectric layer, an erase gate 307, a word line gate 308, and a tunneling oxide layer 309. The floating gate 303, the gate dielectric layer, and the erase gate 307 are sequentially stacked on the substrate 100. The gate dielectric layer includes a first dielectric layer 304 and a second dielectric layer 305. The erase gate 307 includes a first part 301 and a second part 302. The first dielectric layer 304 covers the floating gate 303, the second dielectric layer 305 covers a part of the first dielectric layer 304, the first part 301 covers the second dielectric layer 305, the second part 302 covers the remaining part of the first dielectric layer 304 and extends upward to cover the side walls of the second dielectric layer 305 and the first part 301, and the second part 302 is located on the side close to the source line 306; the word line gate 308 and the tunneling oxide layer 309 are sequentially stacked on the substrate 100, and the word line gate 308 extends upward to cover the gate dielectric layer and the side wall of the first part 301 away from the source line 306. When the split-gate flash memory cell performs an erase operation, electrons are transferred from the floating gate 303 to the erase gate 307 without the participation of the word line gate 308. Therefore, the tunneling oxide layer 309 will not be subjected to electron tunneling during the erase operation, and thus the thickness of the tunneling oxide layer 309 can be thinned to reduce the threshold voltage, so that the split-gate flash memory cell can perform a read operation under low-voltage conditions and reduce the read error. In addition, the erase gate 307 is divided into a first part 301 extending in the horizontal direction and a second part 302 extending in the vertical direction, reducing the length of the erase gate 307 in the horizontal direction to reduce the size of the split-gate flash memory cell.

[0096] The above is only the preferred embodiment of the present invention and does not impose any limitation on the present invention. Any person skilled in the art within the technical field of the present invention, without departing from the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A split-gate flash memory cell, characterized in that, Including: A substrate, a source line formed on the substrate, and two storage bits. The two storage bits are symmetrically arranged, and the source line is located between the two storage bits; Each storage bit includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first part and a second part. The first dielectric layer covers the floating gate, the second dielectric layer covers part of the first dielectric layer, the first part covers the second dielectric layer, the second part covers the remaining part of the first dielectric layer and extends upward to cover the sidewalls of the second dielectric layer and the first part, and the second part is located on the side close to the source line; The word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the sidewalls of the first part away from the source line; 2. The split-gate flash memory cell according to claim 1, wherein Each storage bit further includes: A first sidewall covering at least the second part, the first dielectric layer, and the sidewalls of the floating gate close to the source line; A second sidewall located on the first part; A third sidewall covering at least the first part, the first dielectric layer, the second dielectric layer, and the sidewalls of the floating gate away from the source line; A fourth sidewall covering at least the sidewalls of the word line gate and the tunneling oxide layer away from the source line; 3. A split-gate flash memory cell according to claim 1, wherein, The first dielectric layer includes a first oxide layer, and the second dielectric layer includes a nitride layer and a second oxide layer covering the nitride layer; 4. A split-gate flash memory cell as claimed in claim 1, wherein Further including: A source region located in the substrate at the bottom of the source line. The source region has an overlapping portion with each floating gate in the horizontal direction; Two drain regions respectively located in the substrate at the bottom of each word line gate layer, and each tunneling oxide layer covers a partial region of the corresponding drain region; A plurality of plugs are respectively electrically connected to the source line, the word line gate, and the drain region, and respectively lead out the source line, the word line gate, and the drain region; 5. A split-gate flash memory cell as claimed in claim 1, wherein, The split-gate flash memory cell performs a programming operation by using a hot electron injection method, an erase operation by using the F-N tunneling effect of electrons between the floating gate and the second part of the erase gate, and a read operation by using channel inversion turn-on; 6. The split-gate flash memory cell according to claim 1, wherein The thickness of the tunneling oxide layer is 7. A split-gate flash memory cell as claimed in claim 1, wherein The length of the floating gate in the horizontal direction is 8. A method for fabricating a split-gate flash memory cell, characterized in that, Including: Providing a substrate, on which a source line and two storage bits are formed. The two storage bits are symmetrically arranged, and the source line is located between the two storage bits; Each of the memory bits includes a floating gate, a gate dielectric layer, an erase gate, a word line gate, and a tunneling oxide layer. The floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the substrate. The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The erase gate includes a first portion and a second portion. The first dielectric layer covers the floating gate. The second dielectric layer covers a part of the first dielectric layer. The first portion covers the second dielectric layer. The second portion covers the remaining part of the first dielectric layer and extends upward to cover the sidewalls of the second dielectric layer and the first portion, and the second portion is located on the side close to the source line. The word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upward to cover the gate dielectric layer and the sidewall of the first portion away from the source line.

9. The manufacturing method of a split-gate flash memory cell as described in claim 8, wherein, The steps of forming the memory bit include: forming a stacked layer on the substrate, the stacked layer including a floating gate material layer, a first dielectric material layer, a second dielectric material layer, a first erase gate material layer, and a hard mask layer sequentially stacked on the substrate; etching the hard mask layer, the first erase gate material layer, and the second dielectric material layer in sequence to form an opening; forming a second erase gate material layer on partial sidewalls on both sides of the opening, and the second erase gate material layer constitutes the second portion; continuing to etch the first dielectric material layer and the floating gate material layer along the opening to make the opening extend downward to expose the substrate; filling the opening with source line material to form the source line; after removing the hard mask layer, continuing to etch the first erase gate material layer, the second dielectric material layer, the first dielectric material layer, and the floating gate material layer downward in sequence until the substrate is exposed, and the remaining first erase gate material layer, second dielectric material layer, first dielectric material layer, and floating gate material layer respectively constitute the first portion, the second dielectric layer, the first dielectric layer, and the floating gate.

10. The manufacturing method of a split-gate flash memory cell as described in claim 9, characterized in that, After etching to form the opening until the substrate is exposed and before forming the source line, the steps of forming the memory bit further include: performing a first ion implantation process on the substrate in the opening to form a source region in the substrate in the opening.

11. The manufacturing method of a split-gate flash memory cell as claimed in claim 9, wherein, The steps of etching the hard mask layer, the first erase gate material layer, and the second dielectric material layer in sequence to form the opening include: etching the hard mask layer to form the opening and forming second sidewalls on the sidewalls on both sides of the opening; using the second sidewalls as a mask and continuing to etch the first erase gate material layer and the second dielectric material layer along the opening to make the opening extend downward to expose the first dielectric material layer.

12. The manufacturing method of a split-gate flash memory cell as described in claim 9, wherein, After continuing to etch the first dielectric material layer and the floating gate material layer along the opening and before filling the opening with source line material to form the source line, the steps of forming the memory bit further include: forming first sidewalls on partial sidewalls on both sides of the opening, and the first sidewalls cover at least the sidewalls of the second portion, the first dielectric material layer, and the floating gate material layer; and, After forming the first portion, the second dielectric layer, the first dielectric layer, and the floating gate, a third sidewall is formed at least on sidewalls of the first portion, the second dielectric layer, the first dielectric layer, and the floating gate on a side away from the source line.

13. The manufacturing method of a split-gate flash memory cell as claimed in claim 9, wherein, After forming the first portion, the second dielectric layer, the first dielectric layer, and the floating gate, the steps of forming the memory cell further include: A tunneling oxide material layer and a word line material layer are sequentially formed on the substrate; The word line material layer and the tunneling oxide material layer are etched in sequence until the substrate is exposed, and the remaining tunneling oxide material layer and word line material layer respectively constitute the tunneling oxide layer and the word line gate.

14. The manufacturing method of a split-gate flash memory cell as described in claim 13, wherein, After forming the tunneling oxide layer and the word line gate, the steps of forming the memory cell further include: A fourth sidewall is formed on sidewalls of the word line gate and the tunneling oxide layer on a side away from the source line.

15. The manufacturing method of a split-gate flash memory cell as described in claim 14, characterized in that, After forming the fourth sidewall, it further includes: Performing a second ion implantation process on the substrate outside the fourth sidewall to form two drain regions in the substrate.

16. The manufacturing method of a split-gate flash memory cell as described in claim 15, characterized in that, After forming the drain regions, it further includes: Plugs are respectively formed on the source line, the word line gate, and the drain regions, and the plugs are respectively electrically connected to the source line, the word line gate, and the drain regions, and respectively lead out the source line, the word line gate, and the drain regions.

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