Method for manufacturing a memory

Abstract

The application provides a manufacturing method of a memory. After a silicon oxide layer appears on the back surface of a substrate, the silicon oxide layer is removed, and then subsequent processes are continued, so that no silicon oxide is inserted between the multiple silicon nitride layers formed on the back surface of the substrate, and thus the silicon nitride layers on the back surface of the substrate can be removed by a process of removing a silicon nitride sacrificial layer. That is, while forming a device, the silicon nitride film layers formed on the back surface of the substrate can be removed, which helps to eliminate the stress of the substrate, so as to improve the defects of line tilt and further improve the leakage between lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, in particular to a memory manufacturing method. BACKGROUND

[0002] NAND memory as an important memory has extremely fast write and erase speed, is widely used in various types of memory cards, and is gradually replacing mechanical hard disks and solid state disks. With the size of electronic devices being reduced, the size of NAND memory is also gradually reduced, especially the reduction of the word line spacing in NAND. However, the reduction of the word line spacing has a certain impact on the performance of part of the NAND memory. For example, in a floating gate type memory, the reduction of the word line spacing will cause serious inter-cell coupling interference problems, thereby affecting the size of the cell threshold voltage, the programming and reading speed of the memory array.

[0003] In order to solve this problem, an air gap isolation technology is introduced into the manufacturing of NAND memory, mainly by introducing a substance with the lowest dielectric constant, air, between adjacent word lines, thereby forming a gap between adjacent word lines to improve the capacitive coupling effect between the word line floating gates of the device. However, in the small size NAND manufacturing process, due to the reduction of the size of the adjacent word line spacing, the aspect ratio is high (more than 10), thereby causing the word line structure to be relatively weak and easily tilted in the subsequent process, resulting in leakage between the word lines.

[0004] In particular, in the small size NAND process, multiple film layers are deposited on the front and back of the wafer multiple times, the film layer on the front of the wafer is consumed in the process, and the film layer on the back of the wafer is basically not consumed. Thus, after the air gap is formed, the film layer on the back of the wafer is relatively thick, with a thickness of about 1 microns, causing the overall wafer to have abnormal warping, and the wafer edge is prone to word line structure tilting due to uneven stress, and the uniformity of the leakage between the word lines is affected. SUMMARY

[0005] The purpose of the present application is to provide a memory manufacturing method to solve the problem that in the NAND memory manufacturing process, the film layer deposited on the back of the wafer is basically not consumed, causing the overall wafer to have abnormal warping after the air gap is formed, and the wafer edge is prone to word line structure tilting.

[0006] To solve the above technical problems, the present application provides a memory manufacturing method, comprising:

[0007] providing a substrate, forming a plurality of word lines on the front surface of the substrate, including forming a first silicon nitride layer, the first silicon nitride layer being formed on the front surface of the substrate and also on the back surface of the substrate;

[0008] forming a second silicon nitride layer covering the sidewall of the word line to form a silicon nitride sacrificial layer;

[0009] forming a first silicon oxide layer covering the word line and the silicon nitride sacrificial layer, and also covering the first silicon nitride layer on the back surface of the substrate;

[0010] removing the first silicon oxide layer on the back surface of the substrate to expose the first silicon nitride layer on the back surface of the substrate;

[0011] forming a third silicon nitride layer covering the first silicon oxide layer on the front surface of the substrate and the first silicon nitride layer on the back surface of the substrate;

[0012] removing the silicon nitride sacrificial layer while removing the third silicon nitride layer and the first silicon nitride layer exposed on the back surface of the substrate.

[0013] Optionally, after removing the silicon nitride sacrificial layer to release a gap on the side of the word line, a first dielectric layer is deposited, covering the top of the word line and capping the top of the gap.

[0014] Optionally, the silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon nitride layer on the back surface of the substrate are removed by wet etching.

[0015] Optionally, the solution used in the wet etching is a phosphoric acid solution.

[0016] Optionally, the method of removing the first silicon oxide layer on the back surface of the substrate comprises: forming a protective layer on the front surface of the substrate; removing the first silicon oxide layer on the back surface of the substrate; and removing the protective layer.

[0017] Optionally, the first silicon oxide layer is removed by wet etching.

[0018] Optionally, the solution used in the wet etching is a hydrofluoric acid solution.

[0019] Optionally, the first silicon oxide layer is formed by furnace tube growth.

[0020] Optionally, after forming the third silicon nitride layer and before removing the silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon oxide layer are etched back to expose the top of the word line.

[0021] Optionally, the sidewall of the word line further comprises a silicon oxide layer between the sidewall of the word line and the silicon nitride sacrificial layer.

[0022] Optionally, after forming the third silicon nitride layer and before removing the silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon oxide layer are etched back to expose the top of the word line, and the silicon oxide layer and the silicon nitride sacrificial layer are etched back to expose the head of the word line.

[0023] Optionally, after removing the silicon nitride sacrificial layer, a metal silicide is formed at the head of the word line.

[0024] Optionally, the metal silicide is nickel silicide.

[0025] Optionally, on the front side of the substrate, at least one side of the word line is formed with a plurality of select gate.

[0026] Optionally, the method further comprises: forming the select gate simultaneously with forming the word line; forming a second dielectric layer, which at least fills between the select gates.

[0027] The method for manufacturing a memory provided by the present application removes the silicon oxide layer first after forming the silicon oxide layer on the back side of the substrate, and then continues with the subsequent process, so that the plurality of silicon nitride layers formed on the back side of the substrate are not interpenetrated with silicon oxide, thereby enabling the silicon nitride layers on the back side of the substrate to be removed completely by the process of removing the silicon nitride sacrificial layer. That is, the silicon nitride film layers formed on the back side of the substrate can be removed completely while forming the device, which helps to eliminate the stress of the substrate, thereby improving the defect of word line tilting and further improving the case of leakage between word lines. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figures 1A-1D Fig. 1 is a schematic view of a substrate in a method for manufacturing a memory;

[0029] Figure 2 Fig. 3 is a flow chart of a method for manufacturing a memory according to an embodiment of the present application;

[0030] Figures 3A-3I Fig. 4 is a schematic view of a substrate in a method for manufacturing a memory according to an embodiment of the present application.

[0031] In the drawings,

[0032] 100 - substrate; 210 - word line; 211 - first silicon nitride layer; 220 - select gate; 310 - silicon nitride sacrificial layer; 320 - silicon oxide layer; 400 - first silicon oxide layer; 500 - protective layer; 600 - third silicon nitride layer; 700 - first dielectric layer; 800 - metal silicide; 900 - second dielectric layer. DETAILED DESCRIPTION

[0033] As described in the background, in the process of manufacturing a small size memory, a plurality of film layers are deposited on the front and back of a wafer, the film layers on the front of the wafer are consumed in the process, while the film layers on the back of the wafer are basically not consumed, so that after the air gap is formed, the film layers on the back of the wafer are more and the thickness can reach about 1 micron, which causes the wafer to be abnormally warped, the wafer edge is prone to word line structure toppling due to uneven stress in the wafer, and the leakage uniformity between word lines is affected.

[0034] Specifically, a method for manufacturing a memory generally comprises the following steps.

[0035] First, referring to Figure 1A , a substrate 100 is provided, and a plurality of word lines 210 are formed on the front surface of the substrate 100. Among them, the word lines 210 contain a first silicon nitride layer (not shown in the figure), and when the first silicon nitride layer is formed, a first silicon nitride layer 211 is formed on the back surface of the substrate 100.

[0036] Next, referring to Figure 1B , a second silicon nitride layer is formed, which covers the sidewalls of the word lines to form a silicon nitride sacrificial layer 310. In addition, a silicon oxide layer 320 is also formed between the sidewalls of the word lines 210 and the silicon nitride sacrificial layer 310. Thus, a sidewall structure is formed on the sidewalls of the word lines 210 by using the silicon oxide layer 320 and the silicon nitride sacrificial layer 310.

[0037] Next, referring to Figure 1C , a first silicon oxide layer 400 is formed, which covers the word lines 210 and the silicon nitride sacrificial layer 310, and also covers the first silicon nitride layer 211 on the back surface of the substrate 100. Then, a third silicon nitride layer 600 is formed, which covers the first silicon oxide layer 400 on the front surface of the substrate and the first silicon oxide layer 400 on the back surface of the substrate.

[0038] That is, when the first silicon oxide layer 400 and the third silicon nitride layer 600 are formed on the front surface of the substrate 100, corresponding film layers are also formed on the back surface of the substrate 100. At this time, the first silicon nitride layer 211, the first silicon oxide layer 400 and the third silicon nitride layer 600 are sequentially formed from top to bottom on the back surface of the substrate 100.

[0039] Next, referring to Figure 1D , the silicon nitride sacrificial layer 310 is removed to release a gap at the side of the word line, and a first dielectric layer 700 is deposited to cap the top of the gap. Among them, the silicon nitride sacrificial layer 310 can be removed by using a wet etching process.

[0040] In the process of removing the silicon nitride sacrificial layer 310, the film layer of silicon nitride material exposed on the back surface of the substrate 100 is also consumed. Specifically, only the third silicon nitride layer 600 exposed on the substrate can be removed, while the first silicon oxide layer 400 and the first silicon nitride layer 211 covered thereby remain on the back surface of the substrate, as shown in Figure 1D Thus, the warping of the wafer as a whole is abnormal, the stress is uneven in the wafer plane, the word line structure is prone to tilt at the edge of the wafer, and the leakage uniformity between word lines is affected.

[0041] To avoid the above-mentioned situation, the embodiment provides a manufacturing method of a memory. After forming a silicon oxide layer on the back surface of a substrate, the silicon oxide layer is removed, and then subsequent processes are continued, so that no silicon oxide is intercalated between the multiple silicon nitride layers formed on the back surface of the substrate. Thus, the silicon nitride layers on the back surface of the substrate can be removed by the process of removing the silicon nitride sacrificial layer. That is, while the device is formed, the silicon nitride film layer formed on the back surface of the substrate can be removed in its entirety, which helps to eliminate the stress of the substrate, thereby improving the defect of word line tilt and further improving the leakage between word lines.

[0042] The manufacturing method of the memory provided by the embodiment of the present application is further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0043] Figure 2 The flow chart of the manufacturing method of the memory provided by an embodiment of the present application is shown. Figures 3A-3I The change schematic diagram of the substrate in the manufacturing method of the memory provided by an embodiment of the present application is shown. In combination with Figure 2 and FIG. 3 Figures 3A-3I The manufacturing method of the memory provided by the embodiment includes the following steps.

[0044] Step S100: providing a substrate, forming multiple word lines on the front surface of the substrate, including forming a first silicon nitride layer, the first silicon nitride layer being formed on the front surface of the substrate and also on the back surface of the substrate.

[0045] As shown in Figure 3A The substrate 100 is formed with multiple word lines 210 arranged at intervals. Specifically, the word line can include a word line conductive layer and a first silicon nitride layer (not shown in the figure) located on the word line conductive layer, and the material of the word line conductive layer includes, for example, polysilicon. When the first silicon nitride layer on the front surface of the substrate is formed (i.e., the first silicon nitride layer is formed on the word line conductive layer), the first silicon nitride layer 211 is also formed on the back surface of the substrate 100 at the same time.

[0046] In a further aspect, a plurality of select gate electrodes 220 are formed on at least one side of the word lines 210 on the front side of the substrate 100. In particular, the select gate electrodes 220 are formed simultaneously with the word lines 210, wherein the select gate electrodes 220 can also comprise a first silicon nitride layer. That is, in the present embodiment, the select gate electrodes 220 are formed simultaneously with the word lines 210 and comprise the same film layers.

[0047] Step S200: Referring to FIG. 2A in particular, Figure 3B As shown in FIG. 2B, a second silicon nitride layer is formed, which covers the sidewalls of the word lines 210 to form a silicon nitride sacrificial layer 310. In the present embodiment, the second silicon nitride layer also covers the sidewalls of the select gate electrodes 220 to form the silicon nitride sacrificial layer 310.

[0048] In addition, a silicon oxide layer 320 is formed on the sidewalls of the word lines 210, which is located between the sidewalls of the word lines 210 and the silicon nitride sacrificial layer 310. In the present embodiment, the silicon oxide layer 320 is also formed between the sidewalls of the select gate electrodes 220 and the silicon nitride sacrificial layer 310.

[0049] Continuing to refer to FIG. 2C in particular, Figure 3B As shown in FIG. 2C, the preparation method of the silicon nitride sacrificial layer 310 and the silicon oxide layer 320 can comprise: sequentially depositing a silicon oxide material layer and a silicon nitride material layer on the substrate 100, which sequentially cover the word lines 210 and the select gate electrodes 220; and then performing an etching process to remove the silicon oxide material layer and the silicon nitride material layer on the surface and to retain the silicon oxide material layer and the silicon nitride material layer on the sidewalls of the word lines 210 and the select gate electrodes 220 to form the silicon nitride sacrificial layer 310 and the silicon oxide layer 320.

[0050] Step S300: A first silicon oxide layer is formed, which covers the word lines and the silicon nitride sacrificial layer, and also covers the first silicon nitride layer on the back side of the substrate. At the same time, the first silicon nitride layer also covers part of the select gate electrodes.

[0051] As shown in FIG. 4A in particular, Figure 3C As shown in FIG. 4A in particular, Figure 3B A first silicon oxide layer 400 is formed on the basis of the structure formed, which covers the substrate 100, the top of the word lines 210 and the silicon nitride sacrificial layer 310, and also covers the top and sidewalls of the select gate electrodes 220. The first silicon oxide layer 400 is formed, for example, by means of furnace tube growth. In this process, a first silicon oxide layer is also formed on the back side of the substrate 100. That is, after step S300, the first silicon oxide layer 400 is formed on the first silicon nitride layer 211 on the back side of the substrate 100.

[0052] Step S400: Remove the first silicon oxide layer on the back side of the substrate to expose the first silicon nitride layer on the back side of the substrate. Specifically, the method for removing the first silicon oxide layer on the back side of the substrate may include the following steps.

[0053] Step S410: A protective layer is formed on the front side of the substrate 100. For example... Figure 3D As shown, a protective layer 500 is formed on the first silicon oxide layer 400 on the front side of the substrate 100 to protect the front side of the wafer from damage. The protective layer 500 is, for example, photoresist.

[0054] Step S420: Remove the first silicon oxide layer on the back side of the substrate. For example, the first silicon oxide layer 400 on the back side of the substrate 100 can be removed by wet etching. The solution used for wet etching is, for example, a hydrofluoric acid solution.

[0055] Step S430: Remove the protective layer. That is, after removing the first silicon oxide layer 400 on the back side of the substrate, remove the protective layer 500 to restore the wafer (e.g., Figure 3E (As shown). The protective layer 500 can be removed using either a wet process or a dry process.

[0056] like Figure 3E As shown, after step S400 is completed, the first silicon oxide layer 400 on the back side of the substrate 100 is removed, thereby exposing the first silicon nitride layer 211 on the back side of the substrate 100.

[0057] Step S500: As Figure 3F As shown, a third silicon nitride layer 600 is formed, which covers the first silicon oxide layer 400 on the front side of the substrate and the first silicon nitride layer 211 on the back side of the substrate.

[0058] In this embodiment, after the third silicon nitride layer 600 is formed, the second dielectric layer 900 is formed, and the third silicon nitride layer 600 is used as the polishing stop layer to perform the chemical mechanical polishing process.

[0059] like Figure 3FAs shown, a third silicon nitride layer 600 is formed on the first silicon oxide layer 400. At this time, the third silicon nitride layer 600 is also formed on the back side of the substrate 100. Then, a second dielectric layer is formed, which at least fills the spaces between the select gates. Specifically, a second dielectric layer 900 is formed on the third silicon nitride layer 600, filling at least the gaps between adjacent select gates 220. Next, a chemical mechanical polishing process is performed to planarize the layer until the upper surface of the third silicon nitride layer 600 is exposed, so that the remaining second dielectric layer 900 fills the gaps between adjacent select gates 220. The second dielectric layer 900 is made of silicon oxide, for example, formed by chemical vapor deposition.

[0060] That is, after step S500 is completed, the back side of the substrate 100 is deposited from top to bottom with: a first silicon nitride layer 211 and a third silicon nitride layer 600.

[0061] Step S600: Remove the silicon nitride sacrificial layer, and simultaneously remove the third silicon nitride layer and the first silicon nitride layer exposed on the back side of the substrate.

[0062] like Figures 3G-3H As shown, the silicon nitride sacrificial layer 310 is removed to create a gap on the side of the word line 210. Furthermore, while removing the silicon nitride sacrificial layer 310, the first silicon nitride layer 211 and the third silicon nitride layer 600 exposed on the back side of the substrate 100 are also completely removed. For example, wet etching is used to remove the silicon nitride sacrificial layer 320, the third silicon nitride layer 600 on the back side of the substrate, and the first silicon nitride layer 211, using a solution such as a phosphoric acid solution. That is, after step 600, the entire silicon nitride film layer formed on the back side of the substrate 100 is removed.

[0063] In this embodiment, the method for removing the silicon nitride sacrificial layer 310 includes: etching back the third silicon nitride layer 600 and the first silicon oxide layer 400 to expose the top of the word line and the top of the select gate.

[0064] In other embodiments, after etching back to expose the top of the word line 210 and the select gate 220, the silicon oxide layer 320 and the silicon nitride sacrificial layer 310 can be etched back to reduce their height, thereby exposing the head of the word line 210. Figure 3G As shown. And, the silicon oxide layer 320, the silicon nitride sacrificial layer 310, and the second dielectric layer 900 between the selected gate 220 are etched back to expose the head of the selected gate 220. Next, refer to... Figure 3HAs shown, the wet etching process can be used to continue etching the silicon nitride sacrificial layer 310, and in the process, the third silicon nitride layer 600 and the first silicon nitride layer 211 on the back of the substrate can be removed at the same time.

[0065] Step S700: deposit a first dielectric layer, which covers the top of the word lines and covers the top of the gap.

[0066] The manufacturing method provided in this embodiment further includes: before depositing the first dielectric layer, filling the gap between the select gate electrodes. In the etching process in step S600, the second silicon nitride layer and the silicon nitride sacrificial layer formed between the adjacent select gate electrodes 220 will also be etched to form a gap (as shown in Figure 3H As shown, the gap at this position will affect the performance of the device. Therefore, before depositing the first dielectric layer, the gap between the select gate electrodes needs to be filled (as shown in Figure 3I As shown, the gap at this position will affect the performance of the device. Therefore, before depositing the first dielectric layer, the gap between the select gate electrodes needs to be filled (as shown in

[0067] In a further solution, if the etching exposes the head of the word line 210 and the head of the select gate electrode 220, after removing the silicon nitride sacrificial layer 310 and before forming the first dielectric layer 700, the solution further includes: forming a metal silicide 800 on the head of the word line 210 and the head of the select gate electrode 220, respectively. The metal silicide 800 is nickel silicide.

[0068] Then, the first dielectric layer 700 is formed, which covers the top of the word line 210 and the top of the select gate electrode 220, and covers the top of the gap. As shown in Figure 3I As shown in this embodiment, the first dielectric layer 700 covers the top of the word line 210 and the metal silicide of the select gate electrode 220, and covers the top of the gap, so as to form an air gap between the word lines 210.

[0069] In this embodiment, after the silicon oxide layer is formed on the back of the substrate, the silicon oxide layer is removed, and then the subsequent process is continued, so that the multiple silicon nitride layers formed on the back of the substrate are not interpenetrated by silicon oxide. Therefore, the silicon nitride layers on the back of the substrate can be removed by the process of removing the silicon nitride sacrificial layer. That is, while the device is formed, the multiple film layers formed on the back of the substrate can be removed, which helps to eliminate the stress of the substrate, thereby improving the defect of word line tilting and improving the leakage between the word lines.

[0070] As can be seen from the above, in the manufacturing method of the memory provided by the embodiment of the present application, after the silicon oxide layer appears on the back surface of the substrate, the silicon oxide layer is removed first, and then the subsequent process is continued, so that the silicon oxide is not inserted between the multiple silicon nitride layers formed on the back surface of the substrate, and thus the silicon nitride layers on the back surface of the substrate can be removed completely by using the process of removing the silicon nitride sacrificial layer. That is, while the device is formed, the silicon nitride film layer formed on the back surface of the substrate can be removed completely, which helps to eliminate the stress of the substrate, thereby improving the defect of the word line tilt and further improving the leakage between the word lines.

[0071] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a memory, characterized by, The method comprises: providing a substrate, forming a plurality of word lines on the front surface of the substrate, including forming a first silicon nitride layer on the front surface of the substrate, and also on the back surface of the substrate; forming a second silicon nitride layer covering the sidewalls of the word lines to form a silicon nitride sacrificial layer; forming a first silicon oxide layer covering the word lines and the silicon nitride sacrificial layer, and also covering the first silicon nitride layer on the back surface of the substrate; removing the first silicon oxide layer on the back surface of the substrate to expose the first silicon nitride layer on the back surface of the substrate; forming a third silicon nitride layer covering the first silicon oxide layer on the front surface of the substrate and the first silicon nitride layer on the back surface of the substrate; removing the silicon nitride sacrificial layer while removing the third silicon nitride layer and the first silicon nitride layer exposed on the back surface of the substrate.

2. The method of manufacturing a memory according to claim 1, wherein, After removing the silicon nitride sacrificial layer to release a gap on the side of the word line, a first dielectric layer is deposited, covering the top of the word line and capping the top of the gap.

3. The method of manufacturing a memory according to claim 1, wherein The silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon nitride layer on the back surface of the substrate are removed by wet etching.

4. The method for manufacturing a memory according to claim 3, wherein The solution used in the wet etching is a phosphoric acid solution.

5. The method of manufacturing a memory according to claim 1, wherein, The method for removing the first silicon oxide layer on the back surface of the substrate comprises: forming a protective layer on the front surface of the substrate; removing the first silicon oxide layer on the back surface of the substrate; removing the protective layer.

6. The method of manufacturing a memory as claimed in claim 5, wherein, The first silicon oxide layer is removed by wet etching.

7. The method for manufacturing a memory according to claim 6, wherein The solution used in the wet etching is a hydrofluoric acid solution.

8. The method of fabricating a memory as defined in claim 1, wherein, The first silicon oxide layer is formed by furnace tube growth.

9. The method of fabricating a memory as defined in claim 1, wherein, After forming the third silicon nitride layer and before removing the silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon oxide layer are etched back to expose the top of the word line.

10. The method of manufacturing a memory as claimed in claim 1, wherein, The sidewall of the word line also has a silicon oxide layer between the sidewall of the word line and the silicon nitride sacrificial layer.

11. The method of manufacturing a memory as claimed in claim 10, wherein, After forming the third silicon nitride layer and before removing the silicon nitride sacrificial layer, the third silicon nitride layer and the first silicon oxide layer are etched back to expose the top of the word line, and the silicon oxide layer and the silicon nitride sacrificial layer are etched back to expose the head of the word line.

12. The method of manufacturing a memory as defined in claim 11, wherein, After removing the silicon nitride sacrificial layer, a metal silicide is formed on the head of the word line.

13. The method of manufacturing a memory according to claim 12, wherein, The metal silicide is a nickel silicide.

14. The method of fabricating a memory of claim 1, wherein, On the front surface of the substrate, at least one side of the word line is formed with a plurality of select gates.

15. The method of fabricating a memory as defined in claim 14, wherein, The method further comprises: forming the select gates simultaneously with forming the word lines; forming a second dielectric layer filling at least between the select gates.

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