Integrated assembly and method of forming an integrated assembly

Abstract

The present application relates to integrated assemblies and methods of forming the same. Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel material pillars are arranged in the first and second memory regions. Conductive pillars are arranged in the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is between a first memory block region and a second memory block region. Doped semiconductor material is within the first memory region, the second memory region, and the intermediate region and is adjacent to the panel. The doped semiconductor material is at least part of a conductive source structure within the first and second memory regions. An insulating ring surrounds a lower region of the conductive pillars and between the conductive pillars and the doped semiconductor material. Some embodiments include methods of forming the integrated assembly.

Description

Technical Field

[0001] The present invention relates to methods of forming integrated assemblies, such as integrated memory devices, and the integrated assemblies. Background Art

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory that is widely used in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0004] Before describing NAND specifically, it may be helpful to more generally describe the relationship of a memory array within an integrated arrangement. FIG1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines WL0 to WLm for conducting signals); and first data lines 1006 (e.g., bit lines BL0 to BLn for conducting signals). Access lines 1004 and first data lines 1006 can be used to transmit information to and from memory cells 1003. Row decoder 1007 and column decoder 1008 decode address signals A0 to AX on address lines 1009 to determine which of memory cells 1003 are to be accessed. Sense amplifier circuit 1015 operates to determine the value of information read from memory cell 1003. I / O circuit 1017 transmits the value of information between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 through DQN on I / O lines 1005 can represent the value of information to be read from or written to memory cell 1003. Other devices can communicate with device 1000 via I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 is used to control memory operations to be performed on memory cell 1003 and uses signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuitry 1040 can respond to signals CSEL1 through CSELn via I / O circuitry 1017 to select signals on first data line 1006 and second data line 1013, which can represent the value of information to be read from or programmed into memory cell 1003. Column decoder 1008 may selectively activate CSEL1 through CSELn signals based on A0 through AX address signals on address lines 1009. Selection circuit 1040 may select signals on first and second data lines 1006 and 1013 to enable communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 of FIG. 1 can be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used in the memory array 1002 of FIG. 1 . Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices can include, for example, thirty-two charge storage devices stacked one on top of another, where each charge storage device corresponds to, for example, one of thirty-two rows (e.g., rows 0 through 31). The charge storage devices of corresponding strings can share a common channel region, such as a common channel region formed in corresponding pillars of semiconductor material (e.g., polysilicon) around which the charge storage device strings are formed. In a second direction (XX'), each first group of the multiple strings, for example, sixteen first groups, can include, for example, eight strings that share multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines can couple charge storage devices within a layer. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, and so on. In the third direction (Y-Y'), each second group of strings, such as eight second groups, can include sixteen strings coupled by corresponding data lines from eight data lines. The size of the memory block can include 1,024 pages and a total of approximately 16 MB (e.g., 16 WLs x 32 rows x 2 bits = 1,024 pages / block, block size = 1,024 pages x 16 KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages can be larger or smaller than those shown in FIG.

[0006] 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, the memory block 300 including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to FIG. The multi-string memory block 300 can be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I , tile array j and tile arrays K, where each subset (e.g., tile column) includes a "partial block" (sub-block) of the memory block 300. A global drain-side select gate (SGD) line 340 can be coupled to the SGDs of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers from multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 can simultaneously couple or disconnect the SGDs of the strings of the corresponding partial block (e.g., tile column) independently of the SGDs of the strings of other partial blocks. A global source-side select gate (SGS) line 360 ​​can be coupled to the SGSs of multiple strings. For example, a global SGS line 360 ​​can be coupled to a plurality of sub-SGS lines 362, 364, 366 via corresponding sub-SGS drivers from a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a respective subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 can simultaneously couple or disconnect the SGS of the strings of the corresponding partial block (e.g., a tile column) independently of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 can couple charge storage devices corresponding to a respective row of each string in a plurality of strings. Each global CG line (e.g., global CG line 350) can be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via corresponding sub-string drivers from a plurality of sub-string drivers 312, 314, and 316. Each of the substring drivers can simultaneously couple or disconnect the charge storage devices corresponding to the corresponding partial blocks and / or rows independently of the charge storage devices of other partial blocks and / or rows. The charge storage devices corresponding to the corresponding subset (e.g., partial block) and the corresponding row may include the charge storage devices of a "partial row" (e.g., a single "tile"). The strings corresponding to the corresponding subset (e.g., partial block) can be coupled to corresponding sub-sources of sub-sources 372, 374, and 376 (e.g., "tile sources"), each of which is coupled to a corresponding power supply.

[0007] Instead, the NAND memory device 200 is described with reference to the schematic illustration of FIG. 4 .

[0008] Memory array 200 includes word lines 2021 to 202 N , and bit lines 2281 to 228 M .

[0009] Memory array 200 also includes NAND strings 2061 through 206 M Each NAND string includes charge storage transistors 2081 to 208 NThe charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge-trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0010] Charge storage transistors 208 are located at the intersections of word lines 202 and strings 206. Charge storage transistors 208 represent nonvolatile memory cells for storing data. The charge storage transistors 208 of each NAND string 206 are connected in series in a source-to-drain fashion between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of a string 206 and a source select line 214, while each drain select device 212 is located at the intersection of a string 206 and a drain select line 215. Select devices 210 and 212 can be any suitable access devices and are generally illustrated by the blocks in FIG. 4 .

[0011] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select devices 210 are connected to a source select line 214.

[0012] The drain of each drain select device 212 is connected to a bit line (i.e., digit line) 228 at a drain contact. For example, the drain of drain select device 2121 is connected to bit line 2281. The source of each drain select device 212 is connected to the drain of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain select device 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N of the drain.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are commonly coupled to a given word line 202.

[0014] Vertically stacked memory cells of a three-dimensional NAND architecture can be block erased by generating hole carriers beneath them and then sweeping the hole carriers up the memory cells with an electric field.

[0015] The gating structure of the transistor can be utilized to provide gate-induced drain leakage (GIDL), which generates holes for block erase of memory cells. The transistor can be a source-side select (SGS) device as described above. The channel material associated with the memory cell string can be configured as a channel material pillar, and a region of such a pillar can be coupled to the SGS device in a gating manner. The portion of the channel material pillar coupled in the gating manner is the portion that overlaps the gate of the SGS device.

[0016] It may be desirable to heavily dope at least some of the gating coupled portions of the channel material. In some applications, it may be desirable that the gating coupled portions include both a heavily doped lower region and a lightly doped upper region; wherein both regions overlap with the gate of the SGS device. Specifically, the overlap with the lightly doped region provides a non-leakage "off" characteristic for the SGS device, and the overlap with the heavily doped region provides a leakage GIDL characteristic for the SGS device. The terms "heavily doped" and "lightly doped" are utilized relative to each other and not relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than an adjacent "lightly doped" region and may or may not include heavy doping in the conventional sense. Similarly, a "lightly doped" region is more lightly doped than an adjacent "heavily doped" region and may or may not include light doping in the conventional sense. In some applications, the term "lightly doped" refers to a region having a voltage less than or equal to about 10 V. 18 atoms / cm3 of dopant, and the term "heavily doped" refers to a semiconductor material having greater than or equal to about 10 22 atoms / cubic centimeter of dopant in a semiconductor material.

[0017] The channel material may initially be doped to a lightly doped level, and then heavily doped regions may be formed by outdiffusion from the underlying doped semiconductor material.

[0018] It would be desirable to develop improved methods of forming integrated memories (eg, NAND memories).It would also be desirable to develop improved memory devices. Summary of the Invention

[0019] According to one aspect of the present application, an integrated assembly is provided. The integrated assembly includes: a memory region and another region adjacent to the memory region; a channel material pillar disposed in the memory region and a conductive pillar disposed in the other region; a source structure coupled to a lower region of the channel material pillar; a panel extending across the memory region and the other region and separating a first memory block region from a second memory block region; a doped semiconductor material immediately adjacent to the panel in the memory region and the other region; the doped semiconductor material being at least part of the source structure in the memory region; and a liner laterally surrounding the lower region of the conductive pillar; the liner being between the conductive pillar and the doped semiconductor material and directly contacting the doped semiconductor material.

[0020] According to another aspect of the present application, an integrated assembly is provided. The integrated assembly includes: a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; a conductive pillar disposed within the intermediate region; a panel extending across the first memory region, the intermediate region, and the second memory region; the panel being laterally located between a first memory block region and a second memory block region; a doped semiconductor material within the first memory region, the second memory region, and the intermediate region and immediately adjacent to the panel; the doped semiconductor material being at least part of a conductive source structure within the first and second memory regions; and an insulating ring laterally surrounding a lower region of the conductive pillar and between the conductive pillar and the doped semiconductor material; the doped semiconductor material directly contacting an outer edge of the insulating ring.

[0021] According to another aspect of the present application, a method for forming an integrated assembly is provided. The method includes: forming a structure including a first memory area, a second memory area laterally offset from the first memory area, and an intermediate area laterally between the first and second memory areas; the structure includes a first stack extending across the first memory area, the second memory area, and the intermediate area; the first stack includes alternating semiconductor material-containing areas and intermediate areas; there are at least three semiconductor material-containing areas, wherein one of the semiconductor material-containing areas is a central semiconductor material-containing area and is vertically located between the other two semiconductor material-containing areas; the structure also includes a second stack extending across the first memory area, the second memory area, and the intermediate area, wherein the second stack is above the first stack; the second stack includes alternating first and second levels, wherein the first level includes sacrificial material and the second level includes insulating material; an insulating ring extends through the first stack in the intermediate area; the insulating ring includes insulating ring material; an island of the first stack is surrounded by the insulating ring; forming the second stack extending through the first and second memory areas and at least partially into the first and second memory areas a column of the first stack of memory regions, the column comprising a cell material and a channel material; forming a column extending through the second stack of the intermediate region and into the island; forming a slit opening through the second stack to the central semiconductor material region of the first stack; the slit opening extending across the first memory region, the intermediate region and the second memory region; removing the central semiconductor material region from the first memory region, the intermediate region and the second memory region using one or more etchants flowing into the slit opening, the insulating ring material being resistant to the one or more etchants; the removal of the central semiconductor material region forming a conduit in the first stack within the first and second memory regions; extending the conduit through the cell material and to the channel material of the column; forming a doped semiconductor material within the extended conduit; outwardly diffusing dopants from the doped semiconductor material into the channel material, the outwardly diffused dopants extending upward to at least one of the first levels; and replacing at least some of the sacrificial material of the first level with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 shows a block diagram of a prior art memory device having a memory array of memory cells.

[0023] FIG. 2 shows a schematic diagram of the prior art memory device of FIG. 1 in the form of a 3D NAND memory device.

[0024] FIG. 3 illustrates a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 along the XX′ direction.

[0025] FIG. 4 is a schematic diagram of a NAND memory array according to the prior art.

[0026] Figure 5-5B is a schematic top view of a region of an example integrated assembly at an example processing stage of an example embodiment method for forming an example memory device ( Figure 5 ) and a pair of schematic cross-sectional side views ( Figure 5A and 5B ). Figure 5A and 5B The cross-sectional side views are along Figure 5 Lines AA and BB. Figure 5 A top view along Figure 5A and 5B Line CC.

[0027] Figure 6-6B is Figure 5-5B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly.

[0028] Figure 7A and 7B is Figure 6-6B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 7A and 7B The cross-sectional side views are respectively along Figure 6A and 6B Same cross section.

[0029] Figure 8A and 8B is Figure 7A and 7B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 8A and 8B The cross-sectional side views are respectively along Figure 6A and 6B Same cross section.

[0030] Figure 9A and 9B is Figure 8A and 8B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 9A and 9B The cross-sectional side views are respectively along Figure 6A and 6BSame cross section.

[0031] Figure 10A and 10B is Figure 9A and 9B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 10A and 10B The cross-sectional side views are respectively along Figure 6A and 6B The same cross section

[0032] Figure 11A and 11B is Figure 10A and 10B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 11A and 11B The cross-sectional side views are respectively along Figure 6A and 6B Same cross section.

[0033] Figure 12A and 12B is Figure 11A and 11B The instance processing phase after the instance processing phase of Figure 5-5B Schematic cross-sectional side view of a region of an example integrated assembly. Figure 12A and 12B Along the Figure 6A and 6B Same cross section.

[0034] Figure 13A and 13B yes Figure 12A and 12B A schematic cross-sectional side view of an example integrated assembly of FIG. 1 and illustrating the addition of such an assembly. Figure 12A and 12B Additional vertical extensions beyond those shown in

[0035] Figure 13C yes Figure 13A and 13B Schematic top view of the assembly. Figure 13A and 13B The cross-sectional side views are taken along lines AA and BB of FIG13 . The top view of FIG13 is taken along lines AA and BB of FIG13 . Figure 13A and 13B Line CC.

[0036] Figure 13C-1 is based on Figure 13C An alternative embodiment of the embodiment of the embodiment of the present invention is similar to Figure 13C Schematic top view of the area of ​​.

[0037] Figure 13C-2 is based on Figure 13C Another alternative embodiment of the embodiment of the embodiment of the present invention is similar to Figure 13C Schematic top view of the area of ​​. DETAILED DESCRIPTION

[0038] Some embodiments include using an insulating ring to protect the lower region of the conductive pillar during etching of materials associated with the integrated assembly. Some embodiments include an integrated assembly having an insulating ring laterally surrounding the lower region of the conductive pillar. Example embodiment reference Figure 5 -13 descriptions.

[0039] Figure 5 A top view of several example regions along an example integrated assembly 10 is shown. The illustrated region of assembly 10 includes a pair of memory regions (memory array regions) 12a and 12b (array-1 and array-2), and includes an intermediate region 14 between the memory regions. In some embodiments, memory regions 12a and 12b may be referred to as first regions that are laterally displaced relative to each other (later offset from each other), and intermediate region 14 may be referred to as another region (or as a second region) between the laterally displaced (later offset) first regions. Intermediate region 14 may include numerous regions associated with integrated memory, including, for example, step regions, peak regions, bridge regions, and the like.

[0040] In the illustrated embodiment, the insulating material 36 is disposed within the intermediate region 14 and is configured as an annular ring 35. Figure 5 In the embodiment of FIG, the rings 35 are square, but in other embodiments may have any suitable shape, including, for example, circular, rectangular, oval, etc. The rings 35 may all have the same or different shapes from one another. Each of the rings 35 forms an island 40 within the interior of the ring. The island 40 may serve as a landing area for a conductive post, as described below with reference to FIG. Figure 6-6B Discuss in more detail.

[0041] In some embodiments, material 36 may be referred to as an insulating ring material. Insulating ring material 36 may comprise any suitable composition, and in some embodiments, may comprise one or more of doped silicon oxide, doped silicon nitride, silicon oxynitride, and carbon. For example, insulating ring material 36 may comprise, consist essentially of, or consist of carbon-doped silicon oxide (e.g., carbon-doped silicon dioxide); wherein the carbon concentration is between about 10 15 atoms / cm3 to about 10 25As another example, the insulating ring material 36 may include, consist essentially of, or consist of carbon-doped silicon nitride; wherein the carbon concentration is about 10 15 atoms / cm3 to about 10 25 atoms / cm3. As another example, the insulating ring material 36 may include SiON, consist essentially of SiON, or consist of SiON, where this chemical formula indicates the major components rather than a specific stoichiometry. In some embodiments, SiON may be referred to as silicon oxynitride. Si and O may be present in concentrations in the range of about 20 atomic % (at%) to about 70 at%, and nitrogen may be present in concentrations in the range of about 0.01 at% to about 35 at%, about 10 at%, and about 20 at%. 15 atoms / cm3 to about 10 25 atoms / cm3, etc. As another example, insulating ring material 36 can include, consist essentially of, or consist of carbon. The carbon can be in any suitable form, and in some embodiments, can be entirely in an amorphous phase, or at least essentially entirely in an amorphous phase, where the term "essentially entirely in an amorphous phase" means entirely in an amorphous phase within reasonable manufacturing and measurement tolerances.

[0042] refer to Figure 5A and 5B , which are shown in Figure 5 A cross-sectional side view within the intermediate area 14 and the storage area 12a at a processing stage. Figure 5A The view along Figure 5 Line AA, and Figure 5B The view along Figure 5 Line BB. Figure 5 The view along Figure 5A and 5B Line CC. Figure 5A and 5B The view schematically illustrates Figure 5 The example structure shown in the top view of Figure 5 Provide the same ratio.

[0043] Figure 5A and 5B An example configuration is shown in which insulating material 50 forms a support structure for stack 52 .

[0044] Insulating material 50 may comprise any suitable composition, and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0045] In the illustrated embodiment, the conductive structure 54 is within the insulating material 50. The conductive structure 54 may include any suitable conductive material, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0046] One or more of conductive structures 54 may be coupled to logic circuitry (eg, CMOS) disposed beneath insulating material 50 . Figure 5A Logic circuitry is shown, which may include components 56a and 56b corresponding to, for example, control circuitry and / or sensing circuitry (eg, sense amplifier circuitry, driver circuitry, etc.). Figure 5B Logic circuitry configured to include component 56 c (eg, control circuitry) coupled to source structure 42 including stack 52 is shown.

[0047] Logic circuitry 56 may be supported by a semiconductor material (not shown). Such semiconductor material may, for example, include, consist essentially of, or consist of single crystal silicon (Si). The semiconductor material may be referred to as a semiconductor base, or as a semiconductor substrate. The term "semiconductor substrate" means any structure comprising semiconductor material, including but not limited to a monolithic semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. The configuration described herein may be referred to as an integrated configuration supported by a semiconductor substrate, and therefore may be considered an integrated assembly.

[0048] The stack 52 may be referred to as a first stack and may be considered to span Figure 5 The stack 52 includes a conductive material 58 and includes regions 60 and 62 above the conductive material 58. The region 60 may be referred to as a semiconductor material containing region.

[0049] In the embodiment shown, there are three regions in region 60, and these regions are labeled 60a, 60b, and 60c. Regions 60a and 60c contain semiconductor material 64. Such semiconductor material may include conductively doped semiconductor material, such as conductively doped silicon. In some embodiments, the silicon may be n-type doped and, therefore, may be doped with one or both of phosphorus and arsenic. The conductively doped silicon of regions 60a and 60c may be doped to at least about 10 Å with one or more suitable conductivity-enhancing dopants. 22The semiconductor material in region 60a can be the same as the semiconductor material in region 60c, as shown, or can be different from the semiconductor material in region 60c.

[0050] Central region 60b comprises material 34. Material 34 may comprise an undoped semiconductor material, such as undoped silicon. The term "undoped" does not necessarily mean that there is absolutely no dopant in the semiconductor material, but rather that the amount of any dopant present in such semiconductor material is generally understood to be insignificant. For example, depending on the context, undoped silicon may be understood to comprise less than about 10 16 atoms / cm3, less than about 10 15 In some embodiments, material 34 may include, consist essentially of, or consist of silicon. In some embodiments, material 34 is a sacrificial material (e.g., with respect to the following reference to Figure 8B The described processes are discussed in greater detail herein), and thus material 34 may comprise any suitable sacrificial material, including but not limited to an undoped semiconductor material (eg, undoped silicon).

[0051] Regions 60a-c may be viewed as vertically stacked on top of one another, with region 60b being the central semiconductor material-containing region (in some embodiments) and vertically located between regions 60a and 60c.

[0052] Intervening regions 62 alternate with regions 60 within stack 52. Regions 62 include material 66. Material 66 can be insulating, conductive, or the like. In some embodiments, material 66 can be insulating and can include, consist essentially of, or consist of one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, or the like. Regions 62a and 62b can include the same composition as one another (as shown) or can include different compositions relative to one another. One or both of regions 62 can include a uniform composition (as shown) or can include a laminate of two or more different compositions.

[0053] Although stack 52 is shown as including three of regions 60 (which may be semiconductor material-containing regions) and two of intervening regions 62, it should be understood that the stack may include any suitable number of regions 60 and 62. In some embodiments, stack 52 may include at least three of regions 60 and at least two of intervening regions 62.

[0054] Region 60 can be formed to any suitable thickness, and in some embodiments, can be formed to a thickness in a range from about 100 nanometers (nm) to about 300 nm. Region 62 can be formed to any suitable thickness, and in some embodiments, can be formed to a thickness in a range from about 5 nm to about 20 nm.

[0055] Figure 5A Islands 40 are shown to include regions of conductive material 58 , and at least some of the islands are coupled to CMOS circuitry 56 through conductive material 58 and one or more conductive structures 54 .

[0056] refer to Figure 6-6B , a second stack 68 is formed above the first stack 52. Second stack 68 has alternating first levels 70 and second levels 72. First levels 70 include material 74, and second levels 72 include material 76. Materials 74 and 76 may include any suitable composition. In some embodiments, material 74 may include, consist essentially of, or consist of silicon nitride; and material 76 may include, consist essentially of, or consist of silicon dioxide. Material 74 may be referred to as a sacrificial material, and material 76 may be referred to as an insulating material.

[0057] Figure 6A and 6B The illustrated area of ​​the assembly 10 may be the lower portion of the assembly, and it is understood that the assembly may include a plurality of Figure 6A and 6B A stack 68 of many more levels is shown.

[0058] In some embodiments, first stack 52 and second stack 68 may be considered together to correspond to construction 43 , where, in the illustrated embodiment, such construction also includes insulating ring 35 and island 40 .

[0059] Unit material pillars 16 are formed within storage regions 12a and 12b and are specifically formed to extend through second stack 68 and into first stack 52. Pillars 16 can be substantially identical to one another, where the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement. Pillars 16 can be arranged in a compact configuration within each of storage regions 12a and 12b, such as a hexagonal close-packed (HCP) arrangement. Hundreds, thousands, millions, hundreds of thousands, and so forth, of pillars 16 can be arranged within each of storage regions 12a and 12b.

[0060] Each of pillars 16 includes an exterior region 18 containing memory cell material, a channel material 20 adjacent to exterior region 18 , and an insulating material 22 surrounded by channel material 20 .

[0061] The cell materials within region 18 may include tunneling materials, charge storage materials, and charge blocking materials. The tunneling material (also referred to as a gate dielectric material) may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like. The charge storage material may include any suitable composition and, in some embodiments, may include a floating gate material (e.g., polysilicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, and the like). The charge blocking material may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0062] Channel material 20 comprises a semiconductor material. The semiconductor material may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of one or more of silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, or the like; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are older nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material may comprise, consist essentially of, or consist of appropriately doped silicon.

[0063] The channel material 20 can be considered to be configured as a channel material pillar 24. In the embodiment shown, the channel material pillar 24 is Figure 6 , wherein such an annular ring surrounds the insulating material 22. Such a configuration of the channel material pillars may be considered to correspond to a "hollow" channel configuration, wherein the insulating material 22 is disposed within the hollow body of the channel material pillars. In other embodiments, the channel material 22 may be configured as solid pillars. In some embodiments, the channel material pillars within the memory region 12a may be referred to as first channel material pillars, and the channel material pillars within the memory region 12b may be referred to as second channel material pillars. The channel material pillars may be arranged in any suitable configuration within the first memory region 12a and the second memory region 12b. In some embodiments, the channel material pillars may be arranged in a compact configuration, such as a hexagonal close-packed (HCP) configuration.

[0064] Insulating material 22 may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0065] Cell material pillars 16 are formed to extend through first stack 68 and partially into second stack 52, as shown in FIG6B. In the embodiment shown, cell material pillars 16 extend into lower region 60a of stack 52, but do not extend into conductive material 58. Cell material pillars 16 include cell material 18, channel material pillars 24, and dielectric material 22. In some embodiments, memory regions 12a and 12b (including Figure 6B The segments of the stack 52 within the illustrated region of FIG. 5 may be considered to correspond to source structures 42 similar to the source structures described above with reference to the prior art in FIG. 1-4 .

[0066] Pillars 26 are formed to extend through the second stack 68 within the intermediate region 14 and into the islands 40. Each pillar 26 comprises a conductive material 28 laterally surrounded by an insulating liner 30. The pillars 26 can be arranged in any suitable configuration and may or may not be of the same size and composition as one another. Hundreds, thousands, millions, etc. of pillars 26 may be provided within the intermediate region 14.

[0067] Conductive material 28 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 28 may include one or more of tungsten, titanium nitride, and tungsten nitride. For example, conductive material 28 may include a conductive liner including one or both of titanium nitride and tungsten nitride along insulating liner 30, and may include a tungsten filler laterally surrounded by the conductive liner.

[0068] Insulating liner 30 may comprise any suitable composition, and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0069] In some embodiments, the conductive material 28 of the pillars 26 can be considered to be configured as conductive pillars 32. Such conductive pillars can be "live" and thus can serve as electrical interconnects. Alternatively, the pillars can be "dummy" and can serve only to provide structural support.

[0070] Conductive pillars 32 are formed to extend through first stack 68, through regions 60 and 62 of second stack 52, and to conductive material 58, as shown. Figure 6A. In the illustrated embodiment, conductive pillars 32 are electrically coupled to conductive material 58 of island 40. In embodiments where conductive pillars 32 are "live" pillars, conductive pillars 32 may be coupled to CMOS circuitry 56 through material 58. Alternatively, in embodiments where conductive pillars are "dummy" configurations provided for structural support rather than electrical connection, at least some of conductive pillars 32 may not be coupled to CMOS circuitry.

[0071] Intermediate region 14 may include numerous regions associated with integrated memory, including, for example, step regions, peak regions, bridge regions, etc. If conductive pillars 32 are charged pillars, such pillars may be used to interconnect components associated with memory regions 12 a and 12 b to circuitry below the illustrated region of integrated assembly 10. For example, the conductive pillars may be used to connect bit lines to sensing circuitry (e.g., sense amplifier circuitry), to connect SGD devices to control circuitry, etc.

[0072] The lower region of conductive pillar 32 is shown as being laterally surrounded by an annular ring 35. In some embodiments, annular ring 35 may be referred to as an outer ring. The lower region of the conductive pillar is also laterally surrounded by an inner ring 37 comprising material from regions 60a, 60b, 60c, 62a, and 62b of stack 52, and an additional inner ring comprising insulating material 30. In the illustrated embodiment, each island 40 supports one of the conductive pillars 32. In other embodiments, at least one of the islands 40 may support two or more of the conductive pillars. Also, in the illustrated embodiment, each pillar 26 comprises a conductive pillar 32. In other embodiments, one or more of the pillars 26 may comprise only insulating material, particularly where such pillars are provided solely for structural support.

[0073] Figure 6A and 6B A slit opening 82 is shown through the first stack 68 and into the second stack 52. In the embodiment shown, the slit opening stops at the material 34. In other embodiments, the slit opening may extend into the material 34. The slit opening 82 is Figure 6 The slit opening 82 extends along a first direction (the y-axis direction shown) and spans across the regions 12a, 12b, and 14.

[0074] In the illustrated embodiment, the slit opening has a substantially vertically straight sidewall surface; wherein the term "substantially vertically straight" means vertically straight within reasonable tolerances of manufacturing and measurement. In other embodiments, the sidewall surface of the slit opening may be tapered.

[0075] A protective material 84 is formed within the slit opening 82 and along the sidewall surfaces of the slit opening. The protective material 84 may comprise any suitable composition. In some embodiments, the protective material 84 may comprise, consist essentially of, or consist of silicon; and may specifically comprise substantially undoped (e.g., comprising an intrinsic dopant concentration, and in some embodiments, comprising less than or equal to about 10%). 16 In some embodiments, protective material 84 may include one or more of a metal (e.g., tungsten, titanium, etc.), a metal-containing material (e.g., a metal silicide, a metal nitride, a metal carbide, a metal boride, etc.), and a semiconductor material (e.g., silicon, germanium, etc.).

[0076] refer to Figure 7A and 7B , one or more etchings are used to break through the protective material 84 at the bottom of the slit opening 82 to expose the central semiconductor material containing region 60b of the first stack 52. The slit opening 82 spans Figure 6 Thus, removing the protective material 84 from the bottom of the slit opening 82 exposes the memory area (e.g., Figure 7B 12a) and the middle area 14 ( Figure 7A ) in the material 34.

[0077] refer to Figure 8A and 8B , the sacrificial material 34 of the central region 60b is removed to form a conduit 86 within regions 12a, 12b, and 14 (where regions 12a and 14 are Figure 8B and 8A shown in ).

[0078] Conduit 86 can be formed using any suitable process, and in some embodiments, can be formed using one or more etchants containing hydrofluoric acid. In the illustrated embodiment, intervening regions 62a and 62b remain after forming conduit 86. In other embodiments, such intervening regions can be removed during conduit formation, depending on the composition of the intervening regions and the composition of the etchant used to remove material 34.

[0079] Figure 8A The material 36 of the annular ring 35 is shown to be resistant to the etchant used to form the conduit 86. In some embodiments, the material 34 exposed within the slit 82 can be considered to be removed selectively relative to the insulating ring material 36. For purposes of interpreting this disclosure and the appended claims, a first material is considered to be removed selectively relative to a second material if the first material is removed faster than the second material; this may include, but is not limited to, a condition where the first material is removed at 100% selectivity relative to the second material.

[0080] refer to Figure 9B The conduit 86 extends through the cell material 18 to expose the sidewall surface of the semiconductor material (channel material) 20 . Figure 9A It is shown that no significant changes occur within the intermediate region 14 during the extension of the conduit 86 through the cell material 18. In other words, the material 36 of the ring 35 is resistant to the etchant used to extend the conduit 86 through the cell material 18.

[0081] refer to Figure 10A and 10B , formed in the conduit 86 by the conductive doped semiconductor material 88 ( Figure 9A and 9B ). Semiconductor material 88 may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of one or more of silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, or the like. In some embodiments, semiconductor material 88 may comprise a material that is heavily doped (e.g., doped to at least about 10 nm) with an n-type dopant (e.g., phosphorus, arsenic, etc.). 22 The conductive material 88 may be viewed as a source structure component 90 configured to couple with the lower region of the channel material pillar 24. In some embodiments, Figure 9B The materials in the first stack 52 can all be considered as part of the conductive electrode structure 42. Figure 8B During the removal of the catheter 86, the regions 62a and 62b (as described above with reference to Figure 8B Regions 62a and 62b may be conductive so that they do not adversely affect conduction along source structures 42 including stack 52, or may be insulating and remain thin enough so that they do not problematically affect conduction along source structures including stack 52.

[0082] Material 88 becomes memory areas 12a and 12b (at Figure 10B 12a) and replaces some of the material 34 in the central region 60b of the intermediate region 14 (where the intermediate region 14 is in the Figure 10A shown in ).

[0083] exist Figure 10B In the illustrated embodiment of FIG. 8 , the doped semiconductor material 88 directly contacts the channel material 20 of the channel material pillar 24 .

[0084] exist Figure 10A and 10BIn the illustrated embodiment, the liner 35 has an uppermost surface 47 that is coextensive with an uppermost surface 49 of the source structure 42 .

[0085] refer to Figure 11A and 11B The materials 84 and 88 are removed from the opening (slit) 82 by one or more suitable etches. The materials may be removed by any suitable etchant. The slit opening 82 may be punched to any suitable depth within the source structure 42.

[0086] Dopants are out-diffused from conductively doped semiconductor material 88 into semiconductor material (channel material) 20 to form a heavily doped region 92 within a lower portion of channel material pillar 24. A general upper boundary of the dopants within heavily doped region 92 is indicated by line 93.

[0087] Out-diffusion from doped material 88 into semiconductor material 20 may be achieved by any suitable treatment, including, for example, a suitable thermal treatment (eg, thermal treatment at a temperature exceeding about 300° C. for a duration of at least about two minutes).

[0088] Remove the sacrificial material 74 of the first level 70 ( Figure 10A and 10B ) and is replaced with conductive material 94. Although conductive material 94 is shown as completely filling first level 70, in other embodiments, at least some of the material disposed within first level 70 may be an insulating material (eg, a dielectric barrier material).

[0089] Conductive material 94 may comprise any suitable composition and, in some embodiments, may comprise a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material may comprise any suitable composition and, in some embodiments, may comprise one or more of aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0090] Figure 11A and 11B The first level 70 is a conductive level, and the stack 68 can be considered to include alternating insulating levels (interposer levels) 72 and conductive levels 70 .

[0091] refer to Figure 12A and 12B , a panel material 96 is formed within the slit opening 82. The panel material 96 may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide. Although the panel material 96 is shown as a single uniform composition, in other embodiments, the panel material may comprise a laminate of two or more different compositions.

[0092] The panel material 96 forms a cross-memory area (e.g., Figure 12B12a) and the middle zone ( Figure 12A The lower area of ​​the panel 98 directly contacts the memory area 12a ( Figure 12B ) and the middle zone 14 ( Figure 12A ) within the doped semiconductor material 88.

[0093] Figure 12B The assembly 10 can be considered as a memory device including a memory cell 100 and a select device (SGS device) 102. The lowermost portion of the conductive level 70 is labeled 70a and extends to the conductive level 70a via the doped region 92. The conductive level 70a includes the SGS device 102. In the embodiment shown, the dopant extends partially across the level 70a to achieve a desired balance between the non-leakage "off" characteristics and the leaky GIDL characteristics of the SGS device.

[0094] Although only one of the conductive levels is shown as being incorporated into the SGS device, in other embodiments, multiple conductive levels may be incorporated into the SGS device. The conductive levels may be electrically coupled (joined together) to form a long-channel SGS device. If multiple conductive levels are incorporated into the SGS device, out-diffused dopants may extend upward across two or more of the conductive levels 70 incorporated into the SGS device.

[0095] Memory cells 100 (e.g., NAND memory cells) are stacked vertically on top of each other. Each of the memory cells includes a region of semiconductor material (channel material) 20 and includes a region of conductive layer 70 (control gate region). The region of conductive layer 70 not included in the memory cell 100 can be considered a word line region (routing region) that couples the control gate region with driver circuitry and / or with other suitable circuitry. The memory cell 100 includes cell materials (e.g., tunneling material, charge storage material, and charge blocking material) within region 18.

[0096] In some embodiments, the conductive level 70 associated with the memory cell 100 can be referred to as a word line / control gate level (or memory cell level) because it includes the word lines and control gates associated with the vertically stacked memory cells of a NAND string. A NAND string can include any suitable number of memory cell levels. For example, a NAND string can have 8 memory cell layers, 16 memory cell layers, 32 memory cell layers, 64 memory cell layers, 512 memory cell layers, 1024 memory cell layers, etc.

[0097] The source structure 42 including the stack 52 may be similar to the source structure 216 described in the "Background" section. Figure 12BAs shown in FIG, the source structure is shown coupled to control circuitry (e.g., CMOS) 56 c. The control circuitry may be below the source structure (as shown), or may be in any other suitable orientation. The source structure may be coupled to the control circuitry 56 c at any suitable processing stage.

[0098] In some embodiments, the channel material pillars 24 may be considered to represent a cross- Figure 12B 104. The memory cells 100 on one side of the panel 98 may be considered to be within the first block 104, and the memory cells 100 on the other side of the panel 98 may be considered to be within the second block 106. The blocks 104 and 106 may be similar to the memory blocks (or sub-blocks of memory) described above in the "Background" section of this disclosure.

[0099] Figure 13A and 13B Show Figure 12A and 12B The stack 68 may extend vertically to extend along a substantial portion of the structures 98, 32, and 16 and is shown extending vertically and coupled to additional circuit elements.

[0100] Figure 13B The cell material pillar 16 extends upward to the bit line 108. The SGD device 110 is schematically illustrated adjacent the upper region of the pillar 16 and below the bit line 108.

[0101] The bit line 108 may be relative to Figure 13B The cross-section of the image extends into and out of the page.

[0102] Pillar 16, bit line 108, SGD device 110, SGS device 102, and memory cell 100 may together be considered to form a NAND-type configuration similar to those described above with reference to Figures 1-4.

[0103] exist Figure 13B In the view of FIG, the bit line 108 is indicated as being coupled to the conductive pillar 32, and in FIG. Figure 13A , conductive pillars 32 are indicated as being coupled to bit lines 108. Thus, in some embodiments, bit lines 108 associated with memory region 12a can be coupled to logic circuitry (e.g., 56a and 56b) through conductive pillars 32 associated with intermediate region 14. In some embodiments, logic circuitry 56a and 56b can include sensing circuitry (e.g., sense amplifier circuitry).

[0104] Bit line 108 is an example of a component that can be associated with cell material pillar 16 and coupled to logic circuitry through conductive pillar 32. In other embodiments, other components can be coupled to logic circuitry through one or more of conductive pillars 32, instead of or in addition to a bit line. For example, an SGD device can be coupled to logic circuitry through conductive pillar 32, and in such embodiments, the logic circuitry can include control circuitry for controlling the SGD device. Typically, one or more components can be operatively proximate to cell material pillar 16 (and / or channel material pillar 24) and can be coupled to logic circuitry 56 through conductive pillar 32.

[0105] Figure 13C Shown along Figure 13A and 13B 1. Panel 98 extends across memory regions 12a and 12b and across middle region 14. Panel 98 is laterally located between first memory block region 104 and second memory block region 106 and subdivides first memory block region 104 from second memory block region 106 (i.e., separates first memory block region from second memory block region).

[0106] In the illustrated embodiment, doped semiconductor material 88 is immediately adjacent to segments of panel 98 within intermediate region 14, memory region 12a, and memory region 12b. Doped semiconductor material 88 within memory regions 12a and 12b is immediately adjacent to, and electrically coupled to, channel material pillars 24. In contrast, doped semiconductor material 88 is not immediately adjacent to conductive pillars 32, but rather has at least one insulating material between doped semiconductor material 88 and conductive pillars 32 (e.g., insulating material 36), such that the conductive pillars are not electrically coupled to doped semiconductor material 88.

[0107] In the illustrated embodiment, the insulating material 36 is configured to surround the lower region of the conductive pillar 32 (see FIG. Figure 13A The insulating ring 35 has an outer edge 33, and the doped semiconductor material 88 directly contacts such outer edge of the insulating ring.

[0108] The insulating rings 35 are shown as being square, but in other embodiments may have any suitable shape, including, for example, circular, oval, rectangular, etc. Also, while one post 32 is shown within each ring 35 , in other embodiments, more than one post 32 may be present within one or more of the rings 35 .

[0109] exist Figure 13CIn the illustrated embodiment, ring 35 is an outer ring and laterally surrounds a first inner ring 122 comprising insulating material 34 and a second inner ring 120 comprising material 30. In some embodiments, material 34 of inner ring 122 may comprise, consist essentially of, or consist of silicon. In some embodiments, material 30 of inner ring 120 may comprise, consist essentially of, or consist of silicon dioxide. Figure 13C-1 and 13C-2 Alternative embodiments are shown in which one or both of the inner rings 120 and 122 are omitted.

[0110] Figure 13C The illustrated panel 98 may be one of many panels that extend across regions 12a, 12b, and 14 and separate the first and second memory block regions from each other. Accordingly, the illustrated memory block regions 104 and 106 may represent panels that may be used in Figure 13C A number of memory blocks are formed at the process stage shown.

[0111] The assemblies and structures discussed above can be used within integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0112] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0113] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide linguistic variance to simplify the premise basis within the following claims, and are not intended to indicate any significant chemical or electrical differences.

[0114] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in other instances may be intended to provide linguistic variation within this disclosure to simplify the underlying basis for the appended claims.

[0115] The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the following claims relate to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the drawings or rotated relative to such orientation.

[0116] Unless otherwise specified, the cross-sectional views of the accompanying figures illustrate only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawing.

[0117] When a structure is referred to as being "on," "adjacent," or "against" another structure, the structure may be directly on the other structure or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0118] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying base (e.g., substrate). A vertically extending structure may or may not extend substantially normal to the upper surface of the base.

[0119] Some embodiments include an integrated assembly having a memory region and another region adjacent to the memory region. A channel material pillar is arranged in the memory region. The pillar is arranged in the other region. A source structure is coupled to a lower region of the channel material pillar. A panel extends across the memory region and the other region. The panel separates a first memory block region from a second memory block region. Doped semiconductor material is adjacent to the panel in the memory region and the other region. The doped semiconductor material is at least part of a source structure in the memory region. A liner laterally surrounds the lower region of the conductive pillar. The liner is between the conductive pillar and the doped semiconductor material and directly contacts the doped semiconductor material. The uppermost surface of the liner may be coextensive with the uppermost surface of the source structure.

[0120] Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. A first column of channel material is arranged in the first memory region. A second column of channel material is arranged in the second memory region. A conductive column is arranged in the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is laterally located between the first memory block region and the second memory block region. Doped semiconductor material is within the first memory region, the second memory region, and the intermediate region and is adjacent to the panel. The doped semiconductor material is at least part of the conductive source structure within the first and second memory regions. An insulating ring laterally surrounds a lower region of the conductive column and between the conductive column and the doped semiconductor material. The doped semiconductor material directly contacts the outer edge of the insulating ring.

[0121] Some embodiments include a method for forming an integrated assembly. A structure is formed comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions. The structure comprises a first stack extending across the first memory region, the second memory region, and the intermediate region. The first stack comprises alternating regions containing semiconductor material and intermediate regions. There are at least three regions containing semiconductor material, one of which is a central region containing semiconductor material and is vertically located between the other two regions containing semiconductor material. The structure further comprises a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is above the first stack. The second stack comprises alternating first and second layers, wherein the first layers comprise sacrificial material and the second layers comprise insulating material. An insulating ring extends through the first stack in the intermediate region. The insulating ring comprises insulating ring material. An island in the first stack is surrounded by the insulating ring. A pillar extends through the second stack of the first and second memory regions and at least partially into the first stack of the first and second memory regions. The pillar comprises cell material and channel material. The pillar is formed so as to extend through the second stack in the intermediate region and into the island. A slit opening is formed through the second stack to the central region containing semiconductor material in the first stack. The slit opening extends across the first memory region, the middle region, and the second memory region. A central region containing semiconductor material is removed from the first memory region, the middle region, and the second memory region using one or more etchants flowing into the slit opening. The insulating ring material is resistant to the one or more etchants. Removal of the central region containing semiconductor material forms a conduit in the first stack within the first and second memory regions. The conduit is extended through the cell material and reaches the channel material of the pillar. Doped semiconductor material is formed within the extended conduit. Dopants are out-diffused from the doped semiconductor material into the channel material. The out-diffused dopants extend upward to at least one of the first levels. At least some of the sacrificial material of the first level is replaced with a conductive material.

[0122] As specified, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a memory area and another area adjacent to the memory area; a channel material pillar disposed in the memory region and a conductive pillar disposed in the another region; a source structure coupled to a lower region of the channel material pillar; a panel extending across the memory area and the another area and separating the first memory block area from the second memory block area; a doped semiconductor material proximate to the panel in the memory region and the further region; the doped semiconductor material being at least part of the source structure in the memory region; as well as A liner laterally surrounds the lower region of the conductive pillar; the liner is between the conductive pillar and the doped semiconductor material and directly contacts the doped semiconductor material.

2. The integrated assembly of claim 1, wherein an uppermost surface of the liner is coextensive with an uppermost surface of the source structure.

3. The integrated assembly of claim 1, wherein at least some of the conductive pillars are coupled with logic circuitry underlying the at least some of the conductive pillars.

4. The integrated assembly of claim 3, comprising a bit line over and electrically coupled to the pillar of channel material; and wherein the bit line is coupled to the conductive pillar and through the conductive pillar to the logic circuitry.

5. The integrated assembly of claim 4, wherein the logic circuitry includes sense amplifier circuitry.

6. The integrated assembly of claim 1, wherein the doped semiconductor material comprises silicon.

7. The integrated assembly of claim 1 wherein the liner comprises doped silicon oxide.

8. The integrated assembly of claim 1 wherein the liner comprises carbon-doped silicon oxide.

9. The integrated assembly of claim 8, wherein the carbon is present in a concentration of about 10 15 atoms / cm3 to about 10 25 atoms / cm3 range.

10. The integrated assembly of claim 1 wherein the liner comprises doped silicon nitride.

11. The integrated assembly of claim 1 wherein the liner comprises carbon-doped silicon nitride.

12. The integrated assembly of claim 11, wherein the carbon is present in a concentration of about 10 15 atoms / cm3 to about 10 25 atoms / cm3 range.

13. The integrated assembly of claim 1, wherein the liner comprises SiON, wherein the chemical formula indicates major components rather than specific stoichiometry.

14. The integrated assembly of claim 13, wherein silicon and oxygen are present in a concentration range of about 20 at % to about 70 at %.

15. The integrated assembly of claim 13, wherein nitrogen is present in a concentration ranging from about 0.01 at % to about 35 at %.

16. The integrated assembly of claim 13, wherein nitrogen is present at a concentration of about 10 15 atoms / cm3 to about 10 25 atoms / cm3 range.

17. The integrated assembly of claim 1 wherein the liner consists essentially of carbon.

18. The integrated assembly of claim 17, wherein the carbon is substantially entirely in an amorphous phase.

19. The integrated assembly of claim 1 comprising a vertically stacked conductive level above the memory region and the another region; and wherein the pillar of channel material and the pillar extend through the vertically stacked conductive level.

20. The integrated assembly of claim 19, wherein an upper conductive level in the vertically stacked conductive levels is a memory cell level, and wherein a lower conductive level in the vertically stacked conductive levels is a select device level.

21. The integrated assembly of claim 1, wherein each of the liners is an outer ring and laterally surrounds an inner ring comprising semiconductor material.

22. The integrated assembly of claim 21, wherein the semiconductor material consists of silicon.

23. An integrated assembly comprising: a first memory area, a second memory area offset from said first memory area, and an intermediate area between said first and second memory areas; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; a conductive pillar disposed in the middle region; a panel extending across the first memory area, the middle area, and the second memory area; the panel being laterally located between the first memory block area and the second memory block area; a doped semiconductor material within the first memory region, the second memory region, and the intermediate region and proximate to the panel; the doped semiconductor material being at least part of a conductive source structure within the first and second memory regions; as well as An insulating ring laterally surrounds the lower region of the conductive pillar and is between the conductive pillar and the doped semiconductor material; the doped semiconductor material directly contacts the outer edge of the insulating ring.

24. The integrated assembly of claim 23, wherein the insulating ring comprises carbon-doped silicon oxide.

25. The integrated assembly of claim 23, wherein the insulating ring comprises carbon-doped silicon nitride.

26. The integrated assembly of claim 23, wherein the insulating ring comprises SiON, wherein the chemical formula indicates major components rather than a specific stoichiometry.

27. The integrated assembly of claim 23, wherein the insulating ring consists essentially of carbon.

28. The integrated assembly of claim 23, wherein the insulating ring is an outer ring and laterally surrounds the inner ring.

29. The integrated assembly of claim 28, wherein the inner ring comprises silicon.

30. The integrated assembly of claim 28, wherein the inner ring consists essentially of silicon.

31. The integrated assembly of claim 28, wherein the inner ring comprises silicon dioxide.

32. The integrated assembly of claim 28, wherein the inner ring is a first inner ring and laterally surrounds a second inner ring.

33. The integrated assembly of claim 32, wherein the first inner ring consists essentially of silicon, and wherein the second inner ring comprises silicon dioxide.

34. The integrated assembly of claim 33, wherein the second inner ring directly contacts the conductive post.

35. The integrated assembly of claim 23, wherein the doped semiconductor material comprises silicon.

36. The integrated assembly of claim 23, wherein a component is operatively proximate to the pillar of channel material and is also coupled to the conductive pillar, and wherein the conductive pillar is electrically coupled to logic circuitry.

37. The integrated assembly of claim 36, wherein the component is a bit line, and wherein the logic circuitry includes sense amplifier circuitry.

38. A method of forming an integrated assembly, comprising: forming a structure comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions; the structure comprising a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack comprising alternating semiconductor material-containing regions and intermediate regions; there being at least three of the semiconductor material-containing regions, wherein one of the semiconductor material-containing regions is a central semiconductor material-containing region and is vertically located between the other two semiconductor material-containing regions; the structure further comprising a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is above the first stack; the second stack comprising alternating first and second levels, wherein the first levels comprise a sacrificial material and the second levels comprise an insulating material; an insulating ring extending through the first stack in the intermediate region; the insulating ring comprising an insulating ring material; an island of the first stack being surrounded by the insulating ring; forming pillars extending through the second stacks of the first and second memory regions and at least partially into the first stacks of the first and second memory regions, the pillars comprising cell material and channel material; forming pillars extending through the second stack of the intermediate region and into the islands; forming a slit opening through the second stack to the central semiconductor material-containing region of the first stack; the slit opening extending across the first storage region, the middle region, and the second storage region; removing the central semiconductor material-containing region from within the first reservoir region, the intermediate region, and the second reservoir region using one or more etchants flowing into the slit opening, the insulating ring material being resistant to the one or more etchants; the removal of the central semiconductor material-containing region forming a conduit in the first stack within the first and second reservoir regions; extending the conduit through the cell material and to the channel material of the column; forming a doped semiconductor material within the extended conduit; outdiffusing a dopant from the doped semiconductor material into the channel material, the outdiffused dopant extending up to at least one of the first levels; as well as At least some of the sacrificial material of the first level is replaced with a conductive material.

39. The method of claim 38, further comprising forming a source select device comprising the at least one of the first levels.

40. The method of claim 38, wherein the insulating ring material comprises carbon-doped silicon oxide.

41. The method of claim 38, wherein the insulating ring material comprises carbon-doped silicon nitride.

42. The method of claim 38, wherein the insulating ring material comprises SiON, wherein the chemical formula indicates major components rather than a specific stoichiometry.

43. The method of claim 38, wherein the insulating ring material is composed of carbon.

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