Display panel

Abstract

The application discloses a display panel, which comprises a substrate, an oxide active layer, a gate, a gate insulating layer, a source, a first drain and a second drain. The oxide active layer is arranged on the substrate, and the oxide active layer comprises a first active part and a second active part, the first active part and the second active part are arranged in the same layer and are spaced apart, the first active part and the second active part are arranged in two transistors respectively, and the conductivity of the first active part is different from that of the second active part. The gate insulating layer is arranged between the gate and the oxide active layer. The source is arranged on the side, away from the substrate, of the oxide active layer and the gate. The first drain and the second drain are arranged in the same layer as the source. By arranging two active parts with different conductivities in the two transistors respectively, the display panel can meet the required display effect in different use states, thereby improving the stability and applicability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] Thin-film transistors (TFTs) are key driving components for display panels. The fabrication process of TFTs determines the display quality and, more importantly, the cost of the display panel.

[0003] Existing thin-film transistors cannot meet the requirements of display panels to have different display effects under different usage conditions. They are also prone to short circuits under high voltage, which can lead to display panel failure and instability. In addition, their applicability is not high. Summary of the Invention

[0004] This application provides a display panel to improve the stability of the display panel.

[0005] This application provides a display panel, the display panel comprising:

[0006] substrate;

[0007] An oxide active layer is disposed on the substrate. The oxide active layer includes a first active portion and a second active portion. The first active portion and the second active portion are disposed on the same layer and spaced apart. The conductivity of the first active portion and the conductivity of the second active portion are different.

[0008] A gate is disposed on one side of the oxide active layer;

[0009] A gate insulating layer is disposed between the gate and the oxide active layer;

[0010] The source electrode is disposed on the side of the oxide active layer and the gate electrode away from the substrate; and

[0011] The first drain and the second drain are disposed on the same layer as the source. The first drain and the source are connected through the first active part, and the second drain and the source are connected through the second active part.

[0012] The first active portion, the gate, the gate insulating layer, the source, and the first drain constitute a first transistor, and the second active portion, the gate, the gate insulating layer, the source, and the second drain constitute a second transistor.

[0013] Optionally, in some embodiments of this application, the conductivity of the first active portion is greater than the conductivity of the second active portion.

[0014] Optionally, in some embodiments of this application, the display panel further includes pixel electrodes disposed on the first transistor and the second transistor, the first drain being insulated from and spaced apart from the second drain, and respectively connected to the pixel electrodes.

[0015] Optionally, in some embodiments of this application, the display panel further includes an insulating dielectric layer disposed on the first transistor and the second transistor. The insulating dielectric layer includes two staggered connection holes that penetrate the insulating dielectric layer and expose the first drain and the second drain, respectively.

[0016] The pixel electrode is disposed on the insulating dielectric layer and extends into the two connection holes to connect to the first drain and the second drain, respectively.

[0017] Optionally, in some embodiments of this application, the display panel further includes a pixel electrode disposed on the first transistor and the second transistor, wherein the first drain and the second drain are integrally formed and connected to the pixel electrode.

[0018] Optionally, in some embodiments of this application, the display panel further includes an insulating dielectric layer disposed on the first transistor and the second transistor, and a connection hole disposed in the insulating dielectric layer, the connection hole penetrating the insulating dielectric layer to expose the first drain or the second drain, the pixel electrode being disposed on the insulating dielectric layer and extending into the connection hole to connect with the first drain or the second drain.

[0019] Optionally, in some embodiments of this application, the display panel has a first state;

[0020] In the first state, a first voltage is provided to the gate to turn on the first active part and turn off the second active part, and the display panel displays at a first brightness.

[0021] Optionally, in some embodiments of this application, the display panel further has a second state.

[0022] In the second state, a second voltage is provided to the gate to turn on the first active part and the second active part. The second voltage is greater than the first voltage, and the display panel displays at a second brightness, which is greater than the first brightness.

[0023] Optionally, in some embodiments of this application, the first brightness is less than or equal to 350 nits, and the second brightness is greater than 350 nits.

[0024] Optionally, in some embodiments of this application, the material of the oxide active layer includes at least one of IGZO, ZTO, IZO, and Ln-IZO.

[0025] This application discloses a display panel, which includes a substrate, an oxide active layer, a gate, a gate insulating layer, a source, a first drain, and a second drain. The oxide active layer is disposed on the substrate and includes a first active portion and a second active portion. The first active portion and the second active portion are disposed on the same layer and spaced apart. The conductivity of the first active portion and the conductivity of the second active portion are different. The gate is disposed on one side of the oxide active layer. The gate insulating layer is disposed between the gate and the oxide active layer. The source is disposed on the side of the oxide active layer and the gate away from the substrate. The first drain and the second drain are disposed on the same layer as the source. The first drain and the source are connected through the first active portion, and the second drain and the source are connected through the second active portion. The first active portion, the gate, the gate insulating layer, the source, and the first drain constitute a first transistor, and the second active portion, the gate, the gate insulating layer, the source, and the second drain constitute a second transistor. By setting two active parts with different conductivity in the two transistors, the display panel can meet the display effects required under different usage conditions. At the same time, it can reduce the current pressure in actual operation, thereby improving the applicability and stability of the display panel and thus improving the performance of the display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a first planar schematic diagram of the display panel provided in the embodiments of this application.

[0028] Figure 2 yes Figure 1 A schematic diagram of the display panel along line AB.

[0029] Figure 3 yes Figure 1 A schematic diagram of the display panel along the CD line.

[0030] Figure 4 yes Figure 1 A schematic diagram of the display panel along the EF line.

[0031] Figure 5 This is a second planar schematic diagram of the display panel provided in the embodiments of this application.

[0032] Figure label:

[0033] Display panel 10; scan line 11; data line 12; oxide active layer 13; substrate 100; first transistor 200; gate 210; gate insulating layer 220; first active portion 230; first drain 240; source 250; second transistor 300; second active portion 310; second drain 320; insulating dielectric layer 400; interlayer dielectric layer 410; first passivation layer 420; second passivation layer 430; connection hole 431; common electrode 500; pixel electrode 600. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In this application, "reaction" can be a chemical reaction or a physical reaction.

[0035] This application discloses a display panel, which includes a substrate, an oxide active layer, a gate, a gate insulating layer, a source, a first drain, and a second drain. The oxide active layer is disposed on the substrate. The oxide active layer includes a first active portion and a second active portion. The first active portion and the second active portion are disposed on the same layer and spaced apart. The conductivity of the first active portion and the conductivity of the second active portion are different. The gate is disposed on one side of the oxide active layer. The gate insulating layer is disposed between the gate and the oxide active layer. The source is disposed on the side of the oxide active layer and the gate away from the substrate. The first drain and the second drain are disposed on the same layer as the source. The first drain and the source are connected through the first active portion. The second drain and the source are connected through the second active portion. The first active portion, the gate, the gate insulating layer, the source, and the first drain constitute a first transistor. The second active portion, the gate, the gate insulating layer, the source, and the second drain constitute a second transistor.

[0036] In this application, by setting two active parts with different conductivity in two transistors respectively, the display panel can meet the display effect required under different usage conditions. At the same time, the current pressure in actual operation can be reduced, thereby improving the applicability and stability of the display panel and thus improving the performance of the display panel.

[0037] Please see Figures 1-4 This application provides a display panel 10. The display panel 10 includes a substrate 100, a first transistor 200, a second transistor 300, an insulating dielectric layer 400, a pixel electrode 600, and a common electrode 500.

[0038] An oxide active layer 13 is disposed on the substrate 100. The oxide active layer 13 includes a first active portion 230 and a second active portion 310. The first active portion 230 and the second active portion 310 are disposed on the same layer and spaced apart. The conductivity of the first active portion 230 is different from that of the second active portion 310. A gate 210 is disposed on one side of the oxide active layer 13. A gate insulating layer 220 is disposed between the gate 210 and the oxide active layer 13. A source 250 is disposed on the side of the oxide active layer 13 and the gate 210 away from the substrate 100. A first drain 240 and a second drain 320 are disposed on the same layer as the source 250. The first drain 240 and the source 250 are connected through the first active portion 230. The second drain 320 and the source 250 are connected through the second active portion 310. A first active portion 230, a gate 210, a gate insulating layer 220, a source 250, and a first drain 240 constitute a first transistor 200. A second active portion 310, a gate 210, a gate insulating layer 220, a source 250, and a second drain 320 constitute a second transistor 300. Specifically, the first transistor 200 and the second transistor 300 are connected in parallel. The number of first transistors 200 and the number of second transistors 300 includes at least one. The display panel 10 also includes intersecting scan lines 11 and data lines 12. The first transistor 200 includes a first active portion 230, a gate insulating layer 220, a gate 210, a first drain 240, and a source 250. The second transistor 300 includes a second active portion 310, a gate 210, a gate insulating layer 220, a source 250, and a second drain 320. The gate 210, the gate insulating layer 220, and the first active portion 230 are sequentially stacked on the substrate 100. The second active portion 310 and the first active portion 230 are disposed on the same layer and spaced apart. The conductivity of the first active portion 230 is different from that of the second active portion 310. The first drain 240 and the source 250 are disposed on the same layer and spaced apart on the first active portion 230. The source 250 and the second drain 320 are disposed on the same layer and spaced apart on the second active portion 310. The source 250 is connected to the data line 12. The gate 210 is connected to the scan line 11. That is, the first transistor 200 and the second transistor 300 share the gate 210, the gate insulating layer 220, and the source 250. The first transistor 200 and the second transistor 300 are bottom-gate transistors.

[0039] In another embodiment, the first transistor 200 and the second transistor 300 may also be top-gate transistors.

[0040] In this application, the first transistor 200 and the second transistor 300 are respectively composed of two active portions 230 and 310 with different conductivity, such that the threshold voltage of the first active portion 230 is different from that of the second active portion 310. This allows the display panel 10 to display different brightness when different voltages are applied to the first transistor 200 and the second transistor 300, and it is less likely to cause short circuits under higher voltages, thereby improving the applicability and stability of the display panel 10 and reducing costs.

[0041] In one embodiment, the materials of the first active portion 230 and the second active portion 310 include at least one of IGZO, ZTO, IZO and Ln-IZO.

[0042] In one embodiment, when the first active portion 230 and the second active portion 310 are formed using IGZO, the composition ratio of IGZO is as follows: In has a mass fraction of (20%-40%) in IGZO; Ga has a mass fraction of (20%-40%) in IGZO; and Zn has a mass fraction of (20%-60%) in IGZO, which can improve the stability of the first transistor 200 and the second transistor 300.

[0043] It should be noted that the conductivity of the first active part 230 and the second active part 310 can be obtained by adjusting the constituent components or by adjusting various parameters during the deposition process, such as pressure, baking temperature after film formation, and baking time.

[0044] In one embodiment, the conductivity of the first active portion 230 is greater than the conductivity of the second active portion 310.

[0045] In this application, the conductivity of the first active part 230 is set to be greater than that of the second active part 310, such that the threshold voltage of the first active part 230 is less than that of the second active part 310. This allows the display panel 10 to display different brightness levels when different voltages are applied to the first transistor 200 and the second transistor 300. For example, when a first voltage is applied to the first transistor 200 and the second transistor 300, the first active part 230 is turned on, and the second active part 310 is turned off, at which point the display panel 10 displays the first brightness. When a second voltage is applied to the first transistor 200 and the second transistor 300, the first active part 230 and the second active part 310 are turned on, and the second voltage is greater than the first voltage, at which point the display panel 10 displays the second brightness, which is greater than the first brightness. This satisfies the requirement for different brightness levels of the display panel 10 under different usage conditions, thereby improving the applicability of the display panel 10 and reducing costs. At the same time, it can reduce the current pressure during actual operation, thereby improving the stability of the display panel 10.

[0046] It should be noted that the first brightness is less than or equal to 350 nits, and the second brightness is greater than 350 nits.

[0047] In one embodiment, the first drain 240 and the second drain 320 are arranged at an interval. Specifically, the first drain 240 is disposed on the first active portion 230, and the second drain 320 is disposed on the second active portion 310.

[0048] In this application, the first drain 240 and the second drain 320 are spaced apart and respectively disposed on the first active portion 230 and the second active portion 310. This reduces the amount of metal disposed on the first active portion 230 and the second active portion 310, increases the area of ​​the opening region, thereby increasing the aperture ratio and transmittance, and thus improving the display effect of the display panel 10.

[0049] An insulating dielectric layer 400 is disposed on the first transistor 200 and the second transistor 300. The insulating dielectric layer 400 includes two staggered connection holes 431. The two connection holes 431 penetrate the insulating dielectric layer 400 to expose the first drain 240 and the second drain 320. Specifically, the insulating dielectric layer 400 includes an interlayer dielectric layer 410, a first passivation layer 420, and a second passivation layer 430. The interlayer dielectric layer 410 and the first passivation layer 420 are sequentially stacked on the first transistor 200 and the second transistor 300. A common electrode 500 is disposed on the first passivation layer 420. A second passivation layer 430 is disposed on the first passivation layer 420 and the common electrode 500. The second passivation layer 430 includes two staggered connection holes 431. One connection hole 431 penetrates the interlayer dielectric layer 410, the first passivation layer 420, and the second passivation layer 430 to expose the first drain 240. Another connection hole 431 penetrates the interlayer dielectric layer 410, the first passivation layer 420 and the second passivation layer 430 to expose the second drain 320.

[0050] Pixel electrode 600 is disposed on first transistor 200 and second transistor 300. First drain 240 and second drain 320 are insulated from each other and spaced apart, and are respectively connected to pixel electrode 600. Specifically, pixel electrode 600 is disposed on insulating dielectric layer 400 and extends into two connection holes 431 to connect to first drain 240 and second drain 320.

[0051] In one embodiment, the display panel 10 has a first state. In the first state, a first voltage is provided to the gate 210, which turns on the first active part 230 and turns off the second active part 310, and the display panel 10 displays at a first brightness.

[0052] In one embodiment, the display panel 10 also has a second state. In the second state, a second voltage is provided to the gate 210, which turns on the first active portion 230 and the second active portion 310. The second voltage is greater than the first voltage, and the display panel 10 displays at a second brightness, which is greater than the first brightness.

[0053] Specifically, when the display panel 10 requires a first brightness, the gate 210 provides a first voltage. At this time, the first active part 230 is turned on and the second active part 310 is turned off. All the current flows through the first active part 230. At this time, the display brightness of the display panel 10 (250nit-350nit) is relatively low, which can meet normal use, such as in environments with low ambient light, such as indoors.

[0054] When the display panel 10 requires a second brightness, the second brightness is greater than the first brightness. The gate 210 is given a second voltage, which is greater than the first voltage. The first active part 230 and the second active part 310 are turned on. At this time, the data voltage is shunt through the first active part 230 and the second active part 310, and the pixel electrode 600 can obtain a larger voltage. At this time, the display panel 10 can obtain a high brightness (>350 nits) display, which can meet the requirements for use in environments with strong light, such as outdoors.

[0055] Please see Figure 5 It should be noted that the second structure differs from the first structure in that:

[0056] The first drain 240 and the second drain 320 are integrated. The insulating dielectric layer 400 does not have two connection holes 431, but only one connection hole 431, and this connection hole 431 exposes either the first drain 240 or the second drain 320; that is, the insulating dielectric layer 400 has only one through-hole. The pixel electrode 600 extends into the connection hole 431 and connects to either the first drain 240 or the second drain 320. Other aspects are the same as in the first structure and will not be described further here.

[0057] In this application, the first drain 240 and the second drain 320 are integrated, that is, the first active part 230 and the second active part 310 share a single electrode layer, so that in the same pixel, it is not necessary to open two through holes to connect with the first active part 230 and the second active part 310, thereby avoiding the increased difficulty of process debugging due to opening two through holes in the same pixel. At the same time, when the pixel is small, the two through holes are more likely to cross-link together, which will lead to the display panel 10 being defective.

[0058] In one embodiment, the display panel 10 is a liquid crystal display panel.

[0059] This application provides a display panel 10, in which a first transistor 200 and a second transistor 300 are respectively composed of two active portions 230 and 310 with different conductivity, such that the display panel 10 displays different brightness levels when different voltages are applied to the first transistor 200 and the second transistor 300. For example, when a first voltage is applied to the first transistor 200 and the second transistor 300, the first active portion 230 is turned on and the second active portion 310 is turned off, at which time the display panel 10 displays the first brightness, which is sufficient for use in low-light environments, such as indoors. When a second voltage is applied to the first transistor 200 and the second transistor 300, the first active portion 230 and the second active portion 310 are turned on, and the second voltage is greater than the first voltage, at which time the display panel 10 displays the second brightness, which is greater than the first brightness, thus sufficient for use in bright-light environments, such as outdoors. Therefore, the display panel 10 can meet the requirement of different brightness levels under different usage conditions, thereby improving the applicability of the display panel 10 and reducing costs; at the same time, it reduces the current pressure during actual operation, thereby improving the stability of the display panel 10.

[0060] The above provides a detailed description of a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; an oxide active layer disposed on the substrate, the oxide active layer comprising a first active part and a second active part, the first active part and the second active part being disposed in the same layer and spaced apart, the first active part having a conductivity greater than that of the second active part; a gate disposed on one side of the oxide active layer; a gate insulating layer disposed between the gate and the oxide active layer; a source disposed on the oxide active layer and the gate away from the substrate; and a first drain and a second drain disposed in the same layer as the source, the first drain being connected to the source through the first active part, and the second drain being connected to the source through the second active part; the first active part, the gate, the gate insulating layer, the source, and the first drain constitute a first transistor, and the second active part, the gate, the gate insulating layer, the source, and the second drain constitute a second transistor; wherein the display panel has a first state; in the first state, a first voltage is provided to the gate to turn on the first active part and turn off the second active part, and the display panel displays at a first brightness. The display panel further comprises a pixel electrode disposed on the first transistor and the second transistor, the first drain and the second drain being insulated and spaced apart and connected to the pixel electrode respectively.

2. The display panel of claim 1, wherein, The display panel further comprises an insulating medium layer disposed on the first transistor and the second transistor, the insulating medium layer comprising two connection holes disposed in a staggered manner, the two connection holes penetrating through the insulating medium layer and respectively exposing the first drain and the second drain; 3. The display panel of claim 2, wherein, the pixel electrode is disposed on the insulating medium layer and extends into the two connection holes to be connected to the first drain and the second drain respectively. The display panel further comprises a pixel electrode disposed on the first transistor and the second transistor, the first drain and the second drain being integrated and connected to the pixel electrode.

4. The display panel of claim 1, wherein, The display panel further comprises an insulating medium layer disposed on the first transistor and the second transistor, the insulating medium layer comprising one connection hole penetrating through the insulating medium layer to expose the first drain or the second drain, and the pixel electrode is disposed on the insulating medium layer and extends into the one connection hole to be connected to the first drain or the second drain.

5. The display panel of claim 4, wherein, The display panel further has a second state, 6. The display panel of claim 1, wherein, in the second state, a second voltage is provided to the gate to turn on the first active part and the second active part, the second voltage being greater than the first voltage, and the display panel displays at a second brightness, the second brightness being greater than the first brightness. The first brightness is less than or equal to 350 nit, and the second brightness is greater than 350 nit.

7. The display panel of claim 6, wherein, The material of the oxide active layer comprises at least one of IGZO, ZTO, IZO, and Ln-IZO.

8. The display panel of claim 1, wherein, ​

Images