Semiconductor devices and their fabrication methods

Abstract

The device includes: source / drain regions located above a substrate and spaced apart along a first direction; a first gate structure located between the source / drain regions; and a first channel structure surrounding the first gate structure. The first channel structure includes alternately stacked first and second semiconductor layers. When viewed in a cross-section taken along a second direction perpendicular to the first direction, the central axis of the second semiconductor layer is laterally offset from the central axis of the first semiconductor layer. Embodiments of this application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer of material on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of individual electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, which allows more components to be integrated into a given area. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device including: source / drain regions located above a substrate and spaced apart along a first direction; a first gate structure located between the source / drain regions; and a first channel structure surrounded by the first gate structure, the first channel structure including alternately stacked first and second semiconductor layers, wherein, when viewed in a cross-section taken along a second direction perpendicular to the first direction, the central axis of the second semiconductor layer is laterally offset from the central axis of the first semiconductor layer.

[0005] Other embodiments of this application provide a semiconductor device including: a source region; a drain region separated from the source region along a first direction; and a channel structure between the source region and the drain region, the channel structure including alternately stacked first and second semiconductor layers, wherein, when viewed in a cross-section taken along a second direction perpendicular to the first direction, the first semiconductor layer has opposing first and second sides, the second semiconductor layer has opposing third and fourth sides, the third side of the second semiconductor layer is aligned with the first side of the first semiconductor layer, and the fourth side of the second semiconductor layer is laterally retracted from the second side of the first semiconductor layer.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a fin structure having alternating first and second semiconductor layers over a substrate; forming a dielectric wall on a first longitudinal side of the fin structure but not on a second longitudinal side of the fin structure; performing a first etching process to etch the second semiconductor layer at an etching rate faster than that of etching the first semiconductor layer; performing a second etching process after performing the first etching process to remove the dielectric wall; and forming a gate structure over the first and second semiconductor layers after removing the dielectric wall. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanoFET is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 An example of a nanoFET with an eccentric interbridge channel is shown in a three-dimensional view according to some embodiments.

[0010] Figure 3 Simulation results showing channel charge density in different nanoFETs are presented according to some embodiments of the present invention.

[0011] Figure 4 Simulation results showing the electron density along the width direction of the nanostructure channel in different nanoFETs according to some embodiments of the present invention are presented.

[0012] Figure 5 Simulation results showing electron density along the height direction of inter-bridge channels and nanostructure channels in different nanoFETs according to some embodiments of the present invention are presented.

[0013] Figures 6A to 6D These are simulation results showing the electron density improvement ratio between different nanoFETs according to some embodiments of the present invention.

[0014] Figures 7A to 7D These are simulation results showing the electron density improvement ratio between different nanoFETs according to some embodiments of the present invention.

[0015] Figure 8A Cross-sectional views of inter-bridge channels with different widths are shown according to some embodiments of the present invention.

[0016] Figure 8B Simulation results of electron density in nanoFETs with various inter-bridge channel width differences according to some embodiments of the present invention are shown.

[0017] Figure 9A Simulation results show the improvement rates of on-current, subthreshold swing (SS), and on-current / off-current ratios among different nanoFETs according to some embodiments of the present invention.

[0018] Figure 9B It shows Figure 9A The channel structure of the nanoFET.

[0019] Figures 10A to 22B These are top and cross-sectional views of an intermediate stage in the fabrication of a nanoFET according to some embodiments of the present invention.

[0020] Figures 23A to 31B These are top and cross-sectional views of an intermediate stage in the fabrication of a nanoFET according to some embodiments of the present invention.

[0021] Figures 32A to 40B These are top and cross-sectional views of an intermediate stage in the fabrication of a nanoFET according to some embodiments of the present invention.

[0022] Figure 41 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention.

[0023] Figure 42 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention.

[0024] Figure 43 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention.

[0025] Figure 44 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. As used herein, “left or right,” “about,” “approximately,” or “basically” can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms “left or right,” “about,” “approximately,” or “basically” can be inferred unless explicitly stated otherwise.

[0028] As the fin width in FinFETs decreases, variations in channel width can lead to mobility losses. NanoFETs (e.g., nanosheet FETs, nanowire FETs, etc.) are being investigated as alternatives to FinFETs. In nanoFETs, the transistor's gate is fabricated entirely around the channel (e.g., a nanosheet channel or a nanowire channel), allowing the channel to be surrounded or sealed by the gate. Such transistors offer the advantage of improved gate-to-channel electrostatic control, which also reduces leakage current.

[0029] Figure 1Examples of nanoFETs (e.g., nanosheet FETs, nanoplate FETs, etc.) in three-dimensional views according to some embodiments are shown. The nanoFET includes a nanostructure 104 (e.g., nanosheet, nanowire, nanoring, nanoplate, or other structure having nanoscale dimensions (e.g., several nanometers)) above fins 102 on a substrate 100 (e.g., a semiconductor substrate), wherein the nanostructure 104 serves as a channel region for a GAA-FET. The nanostructure 104 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 106 are disposed between adjacent fins 102, and the fins 102 may protrude over and from between adjacent isolation regions 106. Although the isolation regions 106 are described / shown as separated from the substrate 100, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fins 102 is shown as being a single, continuous material with the substrate 100, the bottom of the fins 102 and / or the substrate 100 may include a single material or multiple materials. In this context, fin 102 refers to the portion extending between adjacent isolation regions 106. Gate dielectric 110 is located above the top surface of fin 102 and along the top, sidewalls, and bottom surface of nanostructure 104. Gate electrode 112 is located above gate dielectric 110. Epitaxial source / drain regions 108 are disposed on fin 102 on opposite sides of gate dielectric layer 110 and gate electrode 112.

[0030] In various embodiments of the invention, inter-bridge channels (which may be interchangeably referred to as bridging channels, bridging portions, or bridging structures in some embodiments of the invention) are added between adjacent nanostructure channels to improve the on-state current of the nanoFET. Furthermore, in various embodiments of the invention, the inter-bridge channels are confined to the peripheral or eccentric regions of the nanostructure channels, which provides improved on-state current enhancement compared to forming inter-bridge channels confined to the central region of the nanostructure channels.

[0031] Figure 2 An example of a nanoFET with an eccentric interbridge channel is shown in a three-dimensional view according to some embodiments. The nanoFET includes a channel structure 203 comprising alternating nanostructured channels 204A-204C (collectively referred to as nanostructured channels 204) and interbridge channels 205A-205B (collectively referred to as interbridge channels 205) on a substrate 200. The substrate 200 may include fins and isolation regions disposed between adjacent fins, such as... Figure 1As shown in the diagram, epitaxial source / drain regions 208 are disposed on opposite sides of the channel structure 203 on the substrate 200. A gate structure 210 surrounds the channel structure 203 and is separated from the epitaxial source / drain regions 208 by a gate spacer 218. The gate structure 210 includes, for example, a gate dielectric 212 over the channel structure 203, a work function metal layer 214 over the gate dielectric 212, and a fill metal 216 over the work function metal layer 214.

[0032] In the channel structure 203, each of the nanostructured channels 204 has a width W204 in the direction perpendicular to the current flow direction between the epitaxial source / drain regions 208 (referred to as the current flow direction), and each of the inter-bridge channels 205 has a width W205 in the current flow direction, which is smaller than the width W204 of the nanostructured channel 204. The inter-bridge channel 205 is confined to the peripheral region of the nanostructured channel 204, rather than the central region of the nanostructured channel 204. In this configuration, the inter-bridge channel 205 forms a single concave angle C203 with only one corresponding nanostructured channel 204. Conversely, if the inter-bridge channel 205 is confined to the central region of the nanostructured channel 204, then the inter-bridge channel 205 will form two concave angles with one corresponding nanostructured channel 204, such as... Figure 3 As exemplified in case #2, the concave corners in the channel structure are observed to result in a weaker gate electric field (i.e., weaker gate control), which in turn may lead to fewer conductive charge carriers. Therefore, by confining the interbridge channel 205 to the peripheral region of the nanostructured channel 204, the number of concave corners in the channel structure 203 can be reduced by half, which in turn produces stronger gate control and thus more conductive charge carriers, which in turn allows for a further increase in the on-current enhancement, as discussed in more detail below.

[0033] Figure 3 Simulation results showing channel charge densities in different nanoFETs according to some embodiments of the present invention are illustrated, wherein the channel charge density is... Figure 3 Displayed on the vertical axis, and the gate voltage is... Figure 3The values ​​are shown on the horizontal axis. In case #1, the channel structure of the nanoFET includes two separated nanostructured channels NS without an inter-bridge channel. In case #2, the channel structure of the nanoFET includes two nanostructured channels NS and an inter-bridge channel IB extending from the central region of the lower nanostructured channel to the central region of the upper nanostructured channel. In case #3, the channel structure of the nanoFET includes two nanostructured channels NS and an inter-bridge channel IB extending from the peripheral region of the lower nanostructured channel to the peripheral region of the upper nanostructured channel. In cases #1-3, the channel structure is surrounded by a gate structure, which includes, for example, a gate dielectric GD, a work function metal WFM above the gate dielectric GD, and a fill metal FM above the work function metal WFM. Comparing the channel charge density curves of case #2 with those of case #1, it can be observed that, at the same given non-zero gate voltage, the channel charge density of the nanoFET with the inter-bridge channel IB is greater than that of the nanoFET without the inter-bridge channel. The simulation results show that the interbridge channel provides enhanced on-current for the nanoFET. Comparing the channel charge density of case #3 with that of case #2, it can be observed that, at the same given non-zero gate voltage, the nanoFET with the interbridge channel IB confined to the peripheral region of the nanosheet channel NS has a greater channel charge density than the nanoFET with the interbridge channel IB confined to the central region of the nanosheet channel NS. This simulation result shows that the enhanced on-current can be further increased by forming the interbridge channel IB at the peripheral region of the nanosheet channel NS.

[0034] Figure 4 The diagram illustrates the width direction W of the nanostructured channel NS in different nanoFETs according to some embodiments of the present invention. NS The simulation results of the electron density, where the electron density is in Figure 4 It is shown on the vertical axis and along the width direction W of the nanostructure channel NS. NS The location is Figure 4The diagram is shown on the horizontal axis. In case #1, the channel structure of the nanoFET comprises two separated nanostructured channels NS without an inter-bridge channel. In case #2, the channel structure of the nanoFET comprises two nanostructured channels NS and an inter-bridge channel IB confined to the central region of the nanostructured channels NS. In case #3, the channel structure of the nanoFET comprises two nanostructured channels NS and an inter-bridge channel IB confined to the peripheral region of the nanostructured channels NS. Comparing the electron density curves for cases #1-#3, it can be observed that the inter-bridge channel IB reduces the electron density; however, the inter-bridge channel IB confined to the peripheral region of the nanostructured channels NS produces a smaller reduction in electron density than the inter-bridge channel IB confined to the central region of the nanostructured channels NS.

[0035] Figure 5 The diagram illustrates the height direction H of the inter-bridge channel IB and the nanostructure channel NS in different nanoFETs according to some embodiments of the present invention. IB+NS The simulation results of the electron density, where the electron density is in Figure 5 Displayed on the vertical axis and along the height direction H IB+NS The location is Figure 5 Represented on the horizontal axis. Figure 5 Comparing the electron density curves of case #3 and case #2, it can be observed that the interbridge channel IB, which is confined to the outer region of the nanostructured channel NS, produces a higher electron density at the opposite end of the interbridge channel IB than the interbridge channel IB, which is confined to the central region of the nanostructured channel NS.

[0036] Figures 6A to 6D These are simulation results showing the electron density increase ratio of the nanoFET in case #3 to that in case #2, according to some embodiments of the present invention, wherein W IB It is the width of the inter-bridge channel IB, W NS It is the width of the nanostructured channel NS, t NS It is the thickness of the nanostructured channel NS, and H IBThis refers to the height of the interbridge channel IB. In some embodiments, W1 is in the range of about 14 nm to about 16 nm, for example, about 15 nm; H1 is in the range of about 19 nm to about 21 nm, for example, about 20 nm; W2 is in the range of about 24 nm to about 26 nm, for example, about 25 nm; and H2 is in the range of about 29 nm to about 31 nm, for example, about 30 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. As a non-limiting example, A nm is in the range of about 4 nm to about 6 nm, for example, about 5 nm; B nm is in the range of about 6 nm to about 8 nm, for example, about 7 nm; and C nm is in the range of about 9 nm to about 11 nm, for example, about 10 nm.

[0037] In case #2, the channel structure of the nanoFET includes two nanostructured channels NS and an inter-bridge channel IB confined to the central region of the nanostructured channels NS, and in case #3, the channel structure of the nanoFET includes two nanostructured channels NS and an inter-bridge channel IB confined to the peripheral region of the nanostructured channels NS. Figures 6A to 6D The simulation results show that the width W of the inter-bridge channel IB The narrower the FET, the more charge carriers are generated in the nanoFET. Figures 6A to 6D The simulation results also show that the interbridge channel IB, which is confined to the outer region of the nanostructured channel NS, produces a higher electron density in the channel structure than the interbridge channel IB, which is confined to the central region of the nanostructured channel NS. Figures 6A to 6D Simulation results also show that the thickness t of the nanostructured channel NS The thicker the FET, the more charge carriers are generated in the nanoFET, due to the increased effective transistor gate width (W). eff It originates from thickened nanostructured channels.

[0038] Figures 7A to 7D The simulation results show the electron density increase ratio of the nanoFET in case #5 to that in case #4 according to some embodiments of the present invention, where W IB It is the width of the inter-bridge channel, W NS It is the width of the nanostructured channel, t NS It is the thickness of the nanostructured channel, and H IBThis refers to the height of the inter-bridge channel. In some embodiments, W1 is in the range of about 14 nm to about 16 nm, for example, about 15 nm; H1 is in the range of about 19 nm to about 21 nm, for example, about 20 nm; W2 is in the range of about 24 nm to about 26 nm, for example, about 25 nm; and H2 is in the range of about 29 nm to about 31 nm, for example, about 30 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. As a non-limiting example, A nm is in the range of about 4 nm to about 6 nm, for example, about 5 nm; B nm is in the range of about 6 nm to about 8 nm, for example, about 7 nm; and C nm is in the range of about 9 nm to about 11 nm, for example, about 10 nm.

[0039] In case #4, the channel structure of the nanoFET includes three alternating nanostructured channels NS and two interbridge channels IB confined to the central region of the nanostructured channels NS, and in case #5, the channel structure of the nanoFET includes three alternating nanostructured channels NS and two interbridge channels IB confined to the peripheral region of the nanostructured channels NS. Figures 7A to 7D The simulation results show that, compared with the inter-bridge channel IB confined to the central region of the nanostructured channel NS, the inter-bridge channel IB confined to the peripheral region of the nanostructured channel NS increases the channel electron density by about 5% to about 12%.

[0040] In some embodiments, the interbridge channel width W of the interbridge channel IB IB Within the range of approximately 2 nm to approximately 10 nm. If the inter-bridge channel width W IB If the width is too large (e.g., greater than approximately 10 nm), a longer transistor gate length can be used to avoid short-channel effects, which could negatively impact the scaling down of the device. If the inter-bridge channel width W... IB If the diameter is too small (e.g., less than about 2 nm), the surface roughness on the sidewalls of the inter-bridge channel may increase, which could lead to decreased mobility and reduced conduction current provided by the inter-bridge channel. In some embodiments, the inter-bridge channel height H of the inter-bridge channel IB is... IB In the range from approximately 10 nm to approximately 200 nm. If the inter-bridge channel height H IB If the diameter is too small (e.g., less than about 10 nm), the inter-bridge channel may provide insufficient boost to the on-current. If the inter-bridge channel height H... IB If the area is too large (e.g., greater than approximately 200 nm), the increased vertical coverage area of ​​the device may increase gate parasitic capacitance and thus degrade device performance. Furthermore, if the inter-bridge channel height H... IB For very large structures (e.g., larger than about 200 nm), forming excessively large inter-bridge channels via etching processes can be challenging, as will be described in more detail below.

[0041] Although the inter-bridge channels in the channel structures in scenarios #4-5 are shown to have substantially the same width, in some other embodiments the inter-bridge channels may have different widths. Figure 8A Cross-sectional views of inter-bridge trench structures with different widths are shown. Figure 8A In the design, the channel structure includes alternating nanostructured channels NS1-NS3 and inter-bridge channels IB1 and IB2 surrounded by the gate structure. Inter-bridge channel IB2 is disposed above inter-bridge channel IB1 and has a width W smaller than that of inter-bridge channel IB1. IB1 Width W IB2 The width difference between inter-bridge channels may affect the electron density in the channel structure, such as... Figure 8B As shown, Figure 8B Simulation results of electron density in nanoFETs with various inter-bridge channel width differences according to some embodiments of the present invention are shown. Figure 8B In the middle, W NS It is the width of the nanostructured channels NS1-NS3, t NS It is the thickness of the nanostructured channels NS1-NS3, and H IB This refers to the heights of the interbridge channels IB1 and IB2. In some embodiments, W1 is in the range of about 14 nm to about 16 nm, for example, about 15 nm; H1 is in the range of about 19 nm to about 21 nm, for example, about 20 nm. In some embodiments, A nm is less than B nm, and B nm is less than C nm. As a non-limiting example, A nm is in the range of about 4 nm to about 6 nm, for example, about 5 nm; B nm is in the range of about 6 nm to about 8 nm, for example, about 7 nm; and C nm is in the range of about 9 nm to about 11 nm, for example, about 10 nm.

[0042] like Figure 8B As shown, the width W of the lower bridge channel IB1 When the width is C nm (e.g., approximately 10 nm), the width W of the upper interbridge channel is... IB2 The smaller the value, the higher the electron density. On the other hand, when the width W of the upper inter-bridge channel... IB2 When the width is A nm (e.g., approximately 5 nm), the width W of the lower interbridge channel is... IB1 The smaller the value, the higher the electron density.

[0043] Figure 9A The simulation results are shown, illustrating the improvements in on-current, subthreshold swing (SS), and on-current / off-current ratio of the nanoFET in Case #6 compared to the nanoFET in Case #7. In Case #6, as... Figure 9BAs shown, the channel structure of the nanoFET includes five alternating nanostructured channels NS1-NS5 and four interbridge channels IB1-IB4 confined to the peripheral region of the nanostructured channels NS1-NS5. In case #7, as... Figure 9B As shown, the channel structure of the nanoFET includes five alternating nanostructured channels NS1-NS5 and four inter-bridge channels IB1-IB4 confined to the central region of the nanostructured channels NS1-NS5. The inter-bridge channels IB1-IB4 each have a width W. IB1 W IB2 W IB3 and W IB4 .exist Figure 9A In this context, ΔIB can be represented as: ΔW IB =W IBn-1 -W IBn For example, W IB1 -W IB2 W IB2 -W IB3 or W IB3 -W IB4 In some embodiments, W2 is in the range of about 24 nm to about 26 nm, for example, about 25 nm; H1 is in the range of about 19 nm to about 21 nm, for example, about 20 nm; A nm is in the range of about 4 nm to about 6 nm, for example, about 5 nm; D nm is in the range of about 0.5 nm to about 1.5 nm, for example, about 1 nm; and E nm is in the range of about 1.5 nm to about 2.5 nm, for example, about 2 nm.

[0044] Figure 9A The simulation results of the conduction current show that in cases #6 and #7, the difference in inter-bridge channel width (ΔW) IB The increase in ) causes the conduction current (I) to on )Increase. Figure 9A It was also shown that the inter-bridge channel IB1-IB4, which is confined to the peripheral region of the nanostructured channels NS1-NS5 (i.e., case #6), can provide a higher on-current than the inter-bridge channel IB1-IB4, which is confined to the central region of the nanostructured channels NS1-NS5 (i.e., case #7), regardless of the difference in inter-bridge channel width.

[0045] Figure 9A The simulation results of the subthreshold swing show that, in cases #6 and #7, the increase in the inter-bridge channel width difference leads to an increase in the subthreshold swing (SS). Figure 9AIt was also shown that interbridge channels IB1-IB4, confined to the peripheral region of nanostructured channels NS1-NS5 (i.e., case #6), could provide higher SS than interbridge channels IB1-IB4 confined to the central region of nanostructured channels NS1-NS5 (i.e., case #7), regardless of the difference in interbridge channel width.

[0046] Figure 9A I in on / I off Ratio simulation results show that the interbridge channel IB1-IB4, confined to the peripheral region of the nanostructured channels NS1-NS5 (i.e., case #6), can provide a higher Ig than the interbridge channel IB1-IB4 located in the central region of the nanostructured channels NS1-NS5 (i.e., case #7). on / I off The ratio, regardless of the difference in width between the bridge channels. Figure 9A It also shows that in cases #6 and #7, the increased difference in the width of the inter-bridge trench leads to I on / I off The ratio decreases. This may be attributed to excessive width in the bottom inter-bridge channel IB1. An excessively wide inter-bridge channel IB1 may be attributed to under-etching during the SiGe selective etching used to form the inter-bridge channel. By confining the inter-bridge channel to the peripheral region of the nanostructured channel, the inter-bridge channel width difference can be reduced by half compared to confining the inter-bridge channel to the central region of the nanostructured channel, since only one side of the inter-bridge channel is etched, which will be discussed in more detail below. Therefore, by confining the inter-bridge channel to the peripheral region of the nanostructured channel, it is easier to control the inter-bridge channel width difference, which in turn helps to prevent excessive width in the bottom inter-bridge channel IB1. In some embodiments, the inter-bridge channel width difference (ΔW) IB The width of the inter-bridge channel is less than about 10 nm. An excessively large inter-bridge channel width (e.g., greater than about 10 nm) may lead to an increased short-channel effect.

[0047] Figures 10A to 22B These are top and cross-sectional views of intermediate stages in the fabrication of a nanoFET according to some embodiments of the present invention. It should be understood that... Figures 10A to 22B Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0048] Figure 10A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 10B It corresponds to Figure 10A The cross-sectional view of line B-B' shown. Figure 10A and Figure 10BThe image shows a semiconductor substrate 300. In some embodiments, substrate 300 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, etc. Substrate 300 may include semiconductor materials, such as elemental semiconductors including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; and combinations thereof. Substrate 100 may be doped or substantially undoped. In a specific example, substrate 100 is a bulk silicon substrate, which may be a wafer.

[0049] The substrate 300 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region. The buffer layer may be formed from an epitaxially grown single-crystal semiconductor material, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

[0050] Impurity ions (interchangeably referred to as dopants) are implanted into the silicon substrate 300 to form well regions (not shown). Ion implantation is performed to prevent punch-through effects. The substrate 300 may include individual regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). Dopants are, for example, boron (BF2) for n-type nanoFETs and phosphorus for p-type nanoFETs.

[0051] Figure 10A and Figure 10B The layer stack formed above the substrate 300 is also shown. A first semiconductor layer (first inter-bridging layer) 302A is formed above the substrate 300. A second semiconductor layer (first nanostructure layer) 304A is formed above the first semiconductor layer 302A. Another first semiconductor layer (second inter-bridging layer) 302B is formed above the second semiconductor layer 304A. Another second semiconductor layer (second nanostructure layer) 304B is formed above the other first semiconductor layer 302B. Another first semiconductor layer (third inter-bridging layer) 302C is formed above the second semiconductor layer 304B. Another second semiconductor layer (third nanostructure layer) 304C is formed above the first semiconductor layer 302C.

[0052] In some embodiments, the first semiconductor layer and the second semiconductor layer are stacked alternately, such that each of the first semiconductor layer and the second semiconductor layer exists in more than two layers. In some embodiments, each of the second semiconductor layer, which becomes a nanosheet, nanowire, nanoplate, or nanoring, may be formed of a different material. In some embodiments, the lattice constant of the second semiconductor layer is greater than the lattice constant of the first semiconductor layer. In other embodiments, the lattice constant of the second semiconductor layer is less than the lattice constant of the first semiconductor layer.

[0053] In some embodiments, the first semiconductor layer and the second semiconductor layer are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si / SiGe / Ge / GeSn, SiGeSn, and combinations thereof. In some embodiments, the first semiconductor layer and the second semiconductor layer are formed by epitaxy. In some embodiments, SiGe is Si 1-x Ge x , where 0.1≤x≤0.9.

[0054] In some embodiments, the first semiconductor layers 302A-302C (collectively referred to as the first semiconductor layer 302) are formed of a first semiconductor material. In some embodiments, the first semiconductor material includes a first group IV element and a second group IV element. The group IV element is selected from the group consisting of C, Si, Ge, Sn, and Pb. In some embodiments, the first group IV element is Si and the second group IV element is Ge. In some embodiments, the first semiconductor material is Si. 1-x Ge x Where 0.1 ≤ x ≤ 0.9. In some embodiments, the first semiconductor layer 302 has different germanium atom concentrations. For example, the bottom first semiconductor layer 302A may have a higher germanium concentration than the upper first semiconductor layers 302B and 302C, which in turn allows the bottom first semiconductor layer 302A to be removed while leaving portions of the upper first semiconductor layers 302B and 302C to be used as inter-bridge channels in a subsequent SiGe selective etching process. In some embodiments, the top first semiconductor layer 302C has a higher germanium concentration than the middle first semiconductor layer 302B, which in turn allows a wider inter-bridge channel to be formed between the nanostructure layers 302B and 302C, and a narrower inter-bridge channel to be formed above the nanostructure layer 302C, in a subsequent SiGe selective etching process.

[0055] In some embodiments, the second semiconductor layers 304A-304C (collectively referred to as the second semiconductor layer 304) are formed of a second semiconductor material. In some embodiments, the second semiconductor material is silicon. In other words, in some embodiments, the second semiconductor material is substantially free of germanium. In some embodiments, the second semiconductor material includes a first group IV element and a second group IV element. In some embodiments, the first group IV element is Si and the second group IV element is Ge. In some embodiments, the amounts of the first group IV element and the second group IV element in the second semiconductor material differ from those in the first semiconductor material. In some embodiments, the amount of Ge in the first semiconductor material is greater than the amount of Ge in the second semiconductor material. In some other embodiments, the second semiconductor material includes group III elements and group V elements.

[0056] The first semiconductor layer 302 and the second semiconductor layer 304 can be formed by one or more epitaxial or epitaxial (epi) processes. Epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The thickness of the first semiconductor layer 302 depends on the target inter-bridge channel height. For example, the thickness of the first semiconductor layer 302 is in the range of about 10 nm to about 200 nm. If the thickness of the first semiconductor layer 302 is too small (e.g., less than about 10 nm), the resulting inter-bridge channel may provide insufficient on-current enhancement. If the thickness of the first semiconductor layer 302 is too large (e.g., greater than about 200 nm), the increased device vertical coverage area may increase gate parasitic capacitance and thus degrade device performance. Furthermore, if the thickness of the first semiconductor layer 302 is too large (e.g., greater than about 200 nm), forming an excessively high inter-bridge channel by subsequent SiGe selective etching processes may be challenging.

[0057] In some embodiments, the thickness of the second semiconductor layer 304 is less than the thickness of the first semiconductor layer 302. For example, the relationship between the thickness t1 of the first semiconductor layer 302 and the thickness t2 of the second semiconductor layer 304 is t1 / t2 = 2 to 20.

[0058] After the epitaxial growth process of the stacked components is completed, a patterned mask 306 is formed above the topmost second semiconductor layer 304C. The second semiconductor layer 304C is then patterned into the patterned mask 306 using suitable photolithography and etching techniques. The patterned mask 306 includes silicon nitride (Si3N4), silicon oxide, or combinations thereof.

[0059] After forming the patterned mask 306, a patterning process is performed on the stacked components to form the fin structure FS, such as... Figure 10A and Figure 10BAs shown in the figure. In some embodiments, the patterning process includes one or more etching processes, wherein the patterned mask layer 306 serves as an etching mask. The one or more etching processes may include a wet etching process, an anisotropic dry etching process, or a combination thereof, and may use one or more etchants that etch the first semiconductor layer 302 and the second semiconductor layer 304 at an etch rate faster than they etch the patterned mask layer 306. Although Figure 10B The fin structure FS shown has vertical sidewalls, but in some other embodiments, the etching process may produce tapered sidewalls.

[0060] Once the fin structure FS has been formed, a shallow trench isolation (STI) region 308 (interchangeably referred to as an isolation insulation layer) is formed around the lower part of the fin structure FS, such as... Figure 10A and Figure 10B As shown in the diagram. The STI region 308 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin structure FS and then recessing the top surface of the dielectric material. The dielectric material of the STI region 308 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), subatmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, or combinations thereof. After deposition, an annealing process or a curing process can be performed. In some cases, the STI region 308 may include a pad, such as a thermal oxide pad grown, for example, through the oxide of the fin structure FS and the silicon or silicon-germanium surface of the substrate 100. The recessing process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) and a subsequent selective etching process (e.g., wet etching or dry etching or combinations thereof), which recesses the top surface of the dielectric material in the STI region 308, causing the upper part of the fin structure FS to protrude from the surrounding insulating STI region 308.

[0061] Figure 11A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 11B It corresponds to Figure 11A The cross-sectional view of line B-B' shown. Figure 11A and Figure 11BIn the fin structure FS, dielectric walls 310 are formed on the first longitudinal side LS1, but not on the second longitudinal side LS2 opposite to the first longitudinal side LS1. The dielectric walls 310 can be formed, for example, by depositing a dielectric layer over a substrate 300, followed by patterning the dielectric layer into dielectric walls 310 using suitable photolithography and etching techniques. For example, a photoresist material is first spin-coated onto the dielectric layer, and then irradiated (exposed) and developed to remove portions of the photoresist material. The patterned photoresist is then used as an etching mask to etch the dielectric layer. The etching step can be dry etching, wet etching, or a combination thereof. In an exemplary photolithography step, a photomask or intermediate mask (not shown) can be placed over the photoresist material, and then it can be exposed to a radiation beam, which can be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, immersion lithography tools or extreme ultraviolet (EUV) tools can be used to expose the photoresist material to increase resolution and reduce the minimum achievable pitch. Baking or curing operations can be performed to harden the exposed photoresist material, and a developer can be used to remove exposed or unexposed portions of the photoresist material, depending on whether a positive or negative resist is used. In some embodiments, the dielectric wall 310 comprises silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable dielectric materials.

[0062] Figure 12A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 12B It corresponds to Figure 12A The cross-sectional view of line B-B' shown, and Figure 12C It corresponds to Figure 12A The cross-sectional view of line C-C' shown in the diagram. Figures 12A to 12C Once the dielectric wall 310 has been formed, a dummy gate structure 312 is formed above the fin structure FS. The dummy gate structure 312 has a longitudinal direction perpendicular to the longitudinal direction of the fin structure FS. The dummy gate structure 312 includes a dummy gate dielectric layer and a dummy gate electrode layer above the dummy gate dielectric layer. The dummy gate dielectric layer can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. The dummy gate electrode layer can be deposited above the dummy dielectric layer and then planarized, for example, by a CMP process. The dummy gate electrode layer can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate electrode layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, etc. The dummy gate dielectric layer and the dummy gate electrode layer are patterned to form the dummy gate structure 312. In some embodiments, the fin mask 306 is removed from the topmost second semiconductor layer 304C before the dummy gate structure 312 is formed.

[0063] Figures 12A to 12C The formation of gate spacers 314 on the sidewalls of the dummy gate structure 312 is also shown. In some embodiments of the spacer formation step, a spacer material layer is deposited on the substrate 300. The spacer material layer may be a conformal layer subsequently etched back to form the gate sidewall spacers. In the illustrated embodiment, the spacer material layer 314 is conformally disposed on the top and sidewalls of the dummy gate structure 312. The spacer material layer 314 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. The spacer material layer 314 may be formed by depositing a dielectric material over the gate structure 312 using a process such as a CVD process, a subatmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. The deposited spacer material layer 314 is then subjected to an anisotropic etching process to expose portions of the fin structure FS not covered by the dummy gate structure 312 (e.g., in the source / drain regions of the fin structure FS). This anisotropic etching process can completely remove the portion of the spacer material layer directly above the dummy gate structure 312. The portion of the spacer material layer located on the sidewall of the dummy gate structure 312 can be retained to form a gate sidewall spacer, which, for simplicity, is designated as gate spacer 314.

[0064] Figure 13A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 13B It corresponds to Figure 13A The cross-sectional view of line B-B' shown in the figure. Figure 13C It corresponds to Figure 13A The cross-sectional view of line C-C' shown, and Figure 13D It corresponds to Figure 13A The cross-sectional view of line D-D' shown. Figures 13A to 13D In this process, an anisotropic etching process, for example using a pseudo-gate structure 312 and a gate spacer 314 as an etching mask, causes the lateral extension of the fin structure FS to extend beyond the exposed portion of the gate spacer 314 (e.g., in the source / drain region of the fin structure FS) and be recessed. In some embodiments, the anisotropic etching can be implemented by dry chemical etching utilizing a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICR) source, a transformer-coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactive gas can be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, etc.), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or combinations thereof.

[0065] Figure 14AThis is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 14B It corresponds to Figure 14A The cross-sectional view of line B-B' shown in the figure. Figure 14C It corresponds to Figure 14A The cross-sectional view of line C-C' shown, and Figure 14D It corresponds to Figure 14A The cross-sectional view of line D-D' shown. Figures 14A to 14D In this process, an inter-bridge mask 316 is formed on the sidewalls of the dielectric wall 310 and above the recessed portion of the fin structure (e.g., in the source / drain region of the fin structure). The inter-bridge mask 316 can be formed, for example, in... Figures 13A to 13D The structure shown is formed by depositing a dielectric layer on top of the structure, followed by an anisotropic etching process to remove the horizontal portion of the dielectric layer while leaving a vertical portion on the sidewall of the dielectric wall 310 to be used as an inter-bridge mask 316.

[0066] Figure 15A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 15B It corresponds to Figure 15A The cross-sectional view of line B-B' shown in the figure. Figure 15C It corresponds to Figure 15A The cross-sectional view of line C-C' shown, and Figure 15D It corresponds to Figure 15A The cross-sectional view of line D-D' shown. Figures 15A to 15D In this process, a selective etching process is performed to selectively etch the first semiconductor layer 302 exposed at the outer sidewall of the gate spacer 314. This etching step forms a sidewall recess 319A below the second semiconductor layer 304A, a sidewall recess 319B between the second semiconductor layers 304A and 304B, and a sidewall recess 319C between the second semiconductor layers 304B and 304C. In some embodiments, the etching step selectively etches the first semiconductor layer 302 at an etch rate faster than it etches the second semiconductor layer 304. Therefore, after the selective etching step is completed, the second semiconductor layer 304 can remain substantially intact.

[0067] In embodiments where the first semiconductor layer 302 comprises, for example, SiGe and the second semiconductor layer 304 comprises, for example, Si or SiC, a fluorine-based etchant capable of forming fluorine radicals (e.g., NF*, NF2*, and F*) can be used to selectively etch the SiGe layer 302. For example, this selective SiGe etching step can be an isotropic dry etching process using a fluorine-containing gas (e.g., NF3 or CF4) as the primary precursor gas, and carried out at a flow rate of the fluorine-containing gas ranging from about 1 standard cubic centimeter (sccm) per minute to about 200 sccm (e.g., 7 ccmm), at a room temperature ranging from about 0 degrees Celsius to about 200 degrees Celsius (e.g., 14 degrees Celsius), and at a pressure ranging from about 1 torr to about 100 torr (e.g., 7 torr). The SiGe selective etching step performed under the above conditions allows for a SiGe etch rate in the range of about 10 nm / min to about 20 nm / min (e.g., 15 nm / min), and a SiGe to Si etch rate ratio in the range of about 40:1 to about 100:1. Etching process conditions outside the selected ranges may result in excessively high SiGe etch rates, excessively low SiGe etch selectivity to Si, and / or non-negligible surface roughness on the sidewalls of the first semiconductor layer 302.

[0068] In some embodiments, the etching step also etches the first semiconductor layer 302A at a faster etch rate than it etches the first semiconductor layers 302B and 302C. This, in turn, allows the ends 318B and 318C of the first semiconductor layers 302B and 302C to remain below the gate spacer 314, while not leaving the ends of the first semiconductor layer 302A below the gate spacer 314. These ends 318B and 318C can be used as portions of the subsequently formed source / drain epitaxial structure for connecting the interbridge channel. In some embodiments, the interbridge mask 316 is used to protect the ends 318B and 318C of the first semiconductor layers 302B and 302C from etching in a direction perpendicular to the outer sidewall of the gate spacer 314.

[0069] In some embodiments where the first semiconductor layer 302A has a higher germanium atom concentration than the first semiconductor layers 302B and 302C, the fluorine-based etchant can etch the first semiconductor layer 302A at a faster etch rate because the SiGe etch rate increases with the percentage of germanium atoms in the etch step using the fluorine-based etchant. In some embodiments where the first semiconductor layers 302B and 302C have substantially the same germanium concentration, the ends 318B and 318C below the gate spacer 314 have substantially the same width, such as... Figure 15CAs shown in the diagram. In some embodiments where the first semiconductor layer 302C has a higher germanium atom concentration than the first semiconductor layer 302B, the end 318C of the first semiconductor layer 302C has a smaller width than the end 318B of the first semiconductor layer 302B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for width differences in the inter-bridge layers, such as... Figure 8A As shown in the image.

[0070] Figure 16A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 16B It corresponds to Figure 16A The cross-sectional view of line B-B' shown in the figure. Figure 16C It corresponds to Figure 16A The cross-sectional view of line C-C' shown, and Figure 16D It corresponds to Figure 16A The cross-sectional view of line D-D' shown. Figures 16A to 16D In this process, for example, the inter-bridge mask 316 is removed using a selective etching process, which etches the dielectric material of the inter-bridge mask 316 at a faster etch rate than it etches other materials on the substrate 300. Once the inter-bridge mask 316 has been removed, the ends 318B and 318C of the first semiconductor layers 302B and 302C are exposed at the outer sidewall of the gate spacer 314.

[0071] Figure 17A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 17B It corresponds to Figure 17A The cross-sectional view of line B-B' shown in the figure. Figure 17C It corresponds to Figure 17A The cross-sectional view of line C-C' shown, and Figure 17D It corresponds to Figure 17A The cross-sectional view of line D-D' shown. Figures 17A to 17D In the process, inner spacers 320A, 320B, and 320C (collectively referred to as inner spacers 320) are formed in sidewall grooves 319A, 319B, and 319C, respectively. The inner spacers 320 can be formed by... Figures 16A to 16D The structure shown is formed by depositing an inner spacer layer (not shown separately) over it. The inner spacer 320 serves as an isolation component between the subsequently formed source / drain epitaxial structure and the gate structure. The inner spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The inner spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material having a k value less than about 3.5. The inner spacer layer can then be anisotropically etched to form the inner spacer 320.

[0072] Figure 18AThis is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 18B It corresponds to Figure 18A The cross-sectional view of line B-B' shown. Figures 18A to 18B In this configuration, an epitaxial source / drain structure 322 is formed on the recessed portion of the fin structure. In some embodiments, stress can be applied to the ends 318B and 318C of the nanostructure layer 304 and the interbridge layer to improve device performance. Figure 18A As shown, the epitaxial source / drain structure 322 is formed such that each dummy gate structure 312 is disposed between corresponding adjacent pairs of the epitaxial source / drain structures 322. In some embodiments, a gate spacer 314 is used to separate the epitaxial source / drain structure 322 from the dummy gate structure 312, and an inner spacer 320 is used to separate the epitaxial source / drain structure 322 from portions of the interbridge layers 302B and 302C by an appropriate lateral distance, such that the epitaxial source / drain structure 322 is not short-circuited with the subsequently formed gate of the resulting nanoFET that will replace the portions of the interbridge layers 302B and 302C.

[0073] In some embodiments, the epitaxial source / drain structure 322 may include any acceptable material suitable for an n-type nanoFET. For example, if the nanostructure layer 304 is silicon, the epitaxial source / drain structure 322 may include a material on which tensile strain is applied to the nanostructure layer 304, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. In some embodiments, the epitaxial source / drain structure 322 may include any acceptable material suitable for a p-type nanoFET. For example, if the nanostructure layer 304 is silicon, the epitaxial source / drain structure 322 may include a material on which compressive strain is applied to the nanostructure layer 304, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain structure 322 may have a small facet, such as... Figure 18B As shown in the image.

[0074] The epitaxial source / drain structure 322 can be implanted with dopants to form source / drain regions, followed by annealing. In some embodiments of the invention, the source / drain regions can have a size of approximately 1 x 10⁻⁶. 17 atoms / cm 3 1x10 22 atoms / cm 3 The impurity concentrations are between [specific values]. p-type impurities include, for example, boron, boron fluoride, indium, etc. n-type impurities include, for example, phosphorus, arsenic, antimony, etc. In some embodiments, the epitaxial source / drain structure 322 can be doped in situ during growth.

[0075] Figure 19A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 19B It corresponds to Figure 19AThe cross-sectional view of line B-B' shown. Figures 19A to 19B In one or more etching steps, the dummy gate structure 312 is removed, thereby forming a gate trench GT between corresponding gate spacers 314. In some embodiments, an interlayer dielectric (ILD) layer is formed over the epitaxial source / drain structure 322 prior to the removal of the dummy gate structure 312. In some embodiments, the dummy gate structure 312 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate structure 312 at a rate faster than the gate spacers 314 and the ILD layer. The gate trench GT is exposed and / or located over the nanostructure layer 304 and the interbridge layer 302.

[0076] Figure 20A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 20B It corresponds to Figure 20A The cross-sectional view of line B-B' shown. Figures 20A to 20B In this process, a selective etching process is performed to selectively etch the interbridge layer 302 exposed in the gate trench GT between the gate spacers 314. This etching step forms an opening 325A below the nanostructure layer 304A, an opening 325B between nanostructure layers 304A and 304B, and an opening 325C between nanostructure layers 304B and 304C. In some embodiments, the etching step selectively etches the interbridge layer 302 at an etch rate faster than it etches the nanostructure layer 304. Therefore, after the selective etching step is completed, the nanostructure layer 304 can remain substantially intact.

[0077] In embodiments where the interbridging layer 302 comprises, for example, SiGe and the nanostructure layer 304 comprises, for example, Si or SiC, a fluorine-based etchant capable of forming fluorine radicals (e.g., NF*, NF2*, and F*) can be used to selectively etch the SiGe layer 302. For example, this selective SiGe etching step can be an isotropic dry etching process using a fluorine-containing gas (e.g., NF3 or CF4) as the primary precursor gas, and carried out at a flow rate of the fluorine-containing gas ranging from about 1 standard cubic centimeter (sccm) per minute to about 200 sccm (e.g., 7 ccmm), at a room temperature ranging from about 0 degrees Celsius to about 200 degrees Celsius (e.g., 14 degrees Celsius), and at a pressure ranging from about 1 torr to about 100 torr (e.g., 7 torr). The SiGe selective etching step performed under the above conditions allows for a SiGe etch rate in the range of about 10 nm / min to about 20 nm / min (e.g., 15 nm / min), and a SiGe to Si etch rate ratio in the range of about 40:1 to about 100:1. Etching process conditions outside the selected ranges may result in excessively high SiGe etch rates, excessively low SiGe etch selectivity to Si, and / or non-negligible surface roughness on the sidewalls of the inter-bridge layer 302.

[0078] In some embodiments, the etching step also etches interbridge layer 302A at a faster etch rate than it etches interbridge layers 302B and 302C. This, in turn, allows portions 324B and 324C of interbridge layers 302B and 302C to remain between gate spacers 314, while leaving portions of interbridge layer 302A unrepresented between gate spacers 314. These remaining portions 324B and 324C bridge nanostructure layers 304A-304C and thus collectively form an E-shaped semiconductor channel structure that allows current to flow between epitaxial source / drain structures 322. Therefore, the remaining portions 324B and 324C may be referred to as interbridge channels 324B and 324C (collectively referred to as 324), and nanostructure layers 304A-304C may be referred to as nanostructure channels 304A-304C (collectively referred to as 304).

[0079] exist Figure 20BIn this embodiment, the E-shaped semiconductor channel structure includes alternately stacked nanostructure channels (i.e., first semiconductor layers) 304 and inter-bridge channels (i.e., second semiconductor layers) 324. The central axis CA2 of the inter-bridge channel 324 is laterally offset from the central axis CA1 of the nanostructure channel 304. In some embodiments, the inter-bridge channel 324 does not overlap with the central axis CA1 of the nanostructure channel 304. The inter-bridge channel 324 has a smaller width than the nanostructure channel 304. In some embodiments, the width of the inter-bridge channel 324 is less than half the width of the nanostructure channel 304. In some embodiments, the nanostructure channel 304 has opposing first side 3041 and second side 3042, and the inter-bridge channel 324 has opposing third side 3241 and fourth side 3242. The first side 3041 of the nanostructure channel 304 is aligned with the third side 3241 of the inter-bridge channel 324. The fourth side 3242 of the interbridge channel 324 laterally retracts from the second side 3042 of the nanostructure channel 304. The interbridge channel 324 is made of a different material than the nanostructure channel 304. For example, the interbridge channel 324 is a germanium-containing semiconductor layer (e.g., a SiGe layer), while the nanostructure channel 304 is a germanium-free semiconductor layer (e.g., a Si layer). Therefore, the interbridge channel 324 has a larger percentage of germanium atoms than the nanostructure channel 304.

[0080] In some embodiments where interbridge layer 302A has a higher germanium atom concentration than interbridge layers 302B and 302C, fluorine-based etchants can etch interbridge layer 302A at a faster etch rate because the SiGe etch rate increases with the percentage of germanium atoms in the etch step using a fluorine-based etchant. In some embodiments where interbridge layers 302B and 302C have substantially the same germanium concentration, the resulting interbridge channels 324B and 324C between gate spacers 314 have substantially the same width, such as... Figure 20B As shown in the figure. In some embodiments where the interbridge layer 302C has a higher germanium atom concentration than the interbridge layer 302B, the resulting interbridge channel 324C has a smaller width than the resulting interbridge channel 324B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for a width difference in the interbridge channel, such as... Figure 8A As shown in the diagram. In that case, interbridge channels 324B and 324C have misaligned sides 3242. In some embodiments where the nanostructured channels 304 have substantially the same width, the width difference between the interbridge channels 324 is greater than the width difference between the nanostructured channels 304.

[0081] In some embodiments, such as Figures 20A to 20B The channel formation steps shown are as follows Figures 15A to 15DThe preceding sidewall recessing steps shown all employ a selective etching process that etches the interbridge layer 302 (e.g., SiGe) at a faster etch rate than the etching of the nanostructure layer 304 (e.g., Si), and therefore, in some embodiments, both steps can use the same etchant chemistry (e.g., a fluorine-based etchant). In this case, as... Figures 20A to 20B The etching time / duration of the channel formation step shown can be longer than that shown. Figures 15A to 15D The etching time / duration of the previous sidewall recess step is shown.

[0082] Figure 21A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 21B It corresponds to Figure 21A The cross-sectional view of line B-B' shown. Figures 21A to 21B For example, the dielectric wall 310 is removed by using a selective etching process that etches the dielectric material of the dielectric wall 310 at a faster etch rate than it etches the semiconductor material of the nanostructure channel 304 and the interbridge channel 324.

[0083] In some embodiments where the dielectric wall 310 is made of silicon oxide (SiO2), the silicon oxide wall 310 can be removed using a cyclic process that includes one or more repeated steps of plasma treatment and annealing. For example, a plasma treatment step followed by an annealing step can be performed, and then the plasma treatment and annealing steps can be repeated. The plasma treatment step is used to selectively etch the silicon oxide, and the annealing step is used to remove solid byproducts generated by the plasma treatment step. In the plasma treatment step, [the following is an example of a process where...] Figures 20A to 20BThe substrate 300 of the structure shown is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gaseous mixture of NF3 and NH3 gases, at an NF3 to NH3 gas flow rate ratio in the range of about 2 to about 100, at a temperature in the range of about 0 degrees Celsius to about 50 degrees Celsius (e.g., 35 degrees Celsius), and at a pressure in the range of about 1 to 100 torr. The annealing temperature of the annealing step is in the range of about 100 degrees Celsius to about 200 degrees Celsius (e.g., greater than 100 degrees Celsius). The SiO2 selective etching process using the aforementioned conditions has high selectivity for semiconductor materials (e.g., Si and SiGe), which in turn results in no or negligible loss in the nanostructured channels 304 and the interbridge channels 324. In some embodiments where the STI region 308 is made of silicon oxide, the etching time / duration of the SiO2 selective etching process is controlled to prevent over-etching of the STI region 308, which in turn results in no or negligible loss in the STI region 308. In some embodiments, prior to the SiO2 selective etching process, a patterned mask may be formed over portions of the STI region 308 not covered by the dielectric wall 310 to protect these portions of the STI region 308 from damage by the SiO2 selective etching process.

[0084] Figure 22A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 22B It corresponds to Figure 22A The cross-sectional view of line B-B' shown. Figures 22A to 22B In this configuration, an alternative gate structure 326 is formed in a gate trench GT between gate spacers 314 to surround a nanostructured channel 304 and an inter-bridge channel 324 suspended between the gate spacers 314. The gate structure 326 may be the final gate of a nano-FET. The final gate structure may be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each formation of the gate structure 326 is associated with a gate in a multi-channel configuration provided by the nanostructured channel 304 and the inter-bridge channel 324. For example, a high-k / metal gate structure 326 is formed in an opening 325 provided by etching the inter-bridge layer (e.g., ...). Figure 21B (As shown in the diagram). In various embodiments, the high-k / metal gate structure 326 includes a gate dielectric layer 328 formed around the nanostructure channel 304 and the inter-bridge channel 324, and a gate metal 330 formed around the gate dielectric layer 328. The gate metal 330 may include one or more work-function metal layers formed around the gate dielectric layer 328 and fill metal formed around the one or more work-function metal layers and filling the remainder of the gate trench GT.

[0085] In some embodiments, the gate dielectric layer 328 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer above the interface layer. The high-k gate dielectric (as used and described herein) includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). The work-function metal layer and / or fill metal layer used within the gate metal 330 may include metals, metal alloys, or metal silicides. Formation of the high-k / metal gate (HKMG) structure 326 may include deposition to form various gate materials and one or more CMP processes to remove excess gate material.

[0086] In some embodiments, the interface layer of the gate dielectric layer 328 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 328 may include hafnium oxide (HfO2). Optionally, the gate dielectric layer 328 may include other high-k dielectric materials, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium barium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), silicon aluminum oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0087] The power-function metal layer in the gate metal 330 may include a power-function metal to provide a suitable power function for the high-k / metal gate structure 326. For an n-type nanoFET, the power-function metal layer may include one or more n-type power-function metals (N-metals) having a power function lower than that of silicon, which is located between the valence band and conduction band (approximately 4.5 eV). Examples of n-type power-function metals include, but are not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type nanoFET, the power-function metal layer may include one or more p-type power-function metals (P-metals) having a power function higher than that of silicon, which is located between the valence band and conduction band. p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the filler metal in the gate metal 330 may include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0088] Figures 23A to 31B These are top and cross-sectional views of intermediate stages in the fabrication of nanoFETs according to some embodiments of the present invention. Typically, methods such as... Figures 23A to 31B The nanoFETs fabricated using the steps shown have spaced and symmetrical E-shaped channel structures, but share a common gate structure around the two E-shaped channel structures. It should be understood that... Figures 23A to 31B Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0089] Figure 23A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 23B It corresponds to Figure 23A The cross-sectional view of line B-B' shown. Figure 23A and Figure 23BIn this embodiment, alternating stacked first semiconductor layers (inter-bridging layers) 402A-402C and second semiconductor layers (nanostructure layers) 404A-404C are formed above the substrate 400, and an STI region 408 is formed around the lower part of the fin structure FS. The material and process details of the substrate 400, inter-bridging layers 402A-402C (collectively referred to as 402), nanostructure layers 404A-404C (collectively referred to as 404), and SIT region 408 are similar to those of the previously discussed material and process details of the substrate 300, inter-bridging layer 302, nanostructure layer 304, and SIT region 308, and therefore will not be repeated for the sake of brevity.

[0090] Figure 24A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 24B It corresponds to Figure 24A The cross-sectional view of line B-B' shown. Figure 24A and Figure 24B In this process, a patterned mask layer 409 is formed above a substrate 400, and then the fin structure is anisotropically etched using the patterned mask layer 409 as an etching mask to form trenches 409S that divide the fin structure into two separated fin structures FS1 and FS2. The fin structure FS1 includes alternating inter-bridge layers 401A-401C and nanostructure layers 405A-405C, and the fin structure FS2 includes alternating inter-bridge layers 403A-403C and nanostructure layers 407A-407C.

[0091] The separated interbridging layers 401A and 403A are made of the same material because they are both formed from interbridging layer 402A, such as Figure 23B As shown in the diagram. Separated interbridging layers 401B and 403B have the same material, as they are both formed from interbridging layer 402B. Separated interbridging layers 401C and 403C have the same material, as they are both formed from interbridging layer 402C. In some embodiments, interbridging layers 401A and 403A may have a higher germanium atom concentration than the upper interbridging layers 401B-401C and 403B-403C, which in turn allows for the removal of the bottom interbridging layers 401A and 403A, while leaving portions of the upper interbridging layers 401B-401C and 403B-403C for use as interbridging channels in subsequent SiGe selective etching processes.

[0092] The separated nanostructure layers 405A and 407A are made of the same material, as they are both formed from nanostructure layer 404A. The separated nanostructure layers 405B and 407B are made of the same material, as they are both formed from nanostructure layer 404B. The separated nanostructure layers 405C and 407C are made of the same material, as they are both formed from nanostructure layer 404C. In some embodiments, nanostructure layers 405A-405C and 407A-407C are silicon and substantially free of germanium.

[0093] Figure 25A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 25B It corresponds to Figure 25A The cross-sectional view of line B-B' shown. Figure 25A and Figure 25B In this process, dielectric walls 410 are formed in trench 409S to electrically isolate fin structures FS1 and FS2. The dielectric walls 410 can be formed by depositing dielectric material in trench 409S until trench 409S is overfilled, followed by a CMP process to remove excess dielectric material outside trench 409S. In some embodiments, the dielectric walls 410 comprise silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable dielectric materials, and are deposited using, for example, CVD, ALD, PVD, or other suitable deposition techniques.

[0094] Figure 26A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 26B It corresponds to Figure 26A The cross-sectional view of line B-B' shown. Figure 26A and Figure 26B In the middle, a dummy gate structure 412 is formed across fin structures FS1 and FS2. The dummy gate structure 412 has a longitudinal direction perpendicular to the longitudinal direction of fin structures FS1 and FS2. Next, a gate spacer 414 is formed on the sidewall of the dummy gate structure 412. The material and process details of the dummy gate structure 412 and the gate spacer 414 are similar to those of the dummy gate structure 312 and the gate spacer 314 as previously discussed, and therefore will not be repeated for the sake of brevity.

[0095] Figure 27A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 27B It corresponds to Figure 27A The cross-sectional view of line B-B' shown. Figure 27A and Figure 27BIn the process, the fin structures FS1 and FS2 extend beyond the recessed portion of the gate structure 412 and the gate spacer 414, and then epitaxial source / drain structures 416S and 416D are formed on the recessed portion of the fin structure FS1, and epitaxial source / drain structures 418S and 418D are formed on the recessed portion of the fin structure FS2. The epitaxial growth time / duration is controlled so that the top position of the epitaxial source / drain structures 416S, 416D, 418S, and 418D is lower than the top position of the dielectric wall 410, and therefore, the epitaxial source structure 416S is completely spaced from the epitaxial source structure 418S by the dielectric wall 410, and the epitaxial drain structure 416D is completely spaced from the epitaxial drain structure 418D by the dielectric wall 410. The material and process details for the epitaxial source / drain structures 416S, 416D, 418S, and 418D are similar to those for the previously discussed epitaxial source / drain structure 322, and therefore will not be repeated for the sake of brevity.

[0096] Figure 28A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 28B It corresponds to Figure 28A The cross-sectional view of line B-B' shown. Figure 28A and Figure 28B In one or more etching steps, the dummy gate structure 412 is removed, thereby forming a gate trench between the corresponding gate spacers 414. In some embodiments, an ILD layer is formed over the epitaxial source / drain structures 416S, 416D, 418S, 418D before removing the dummy gate structure 412. In some embodiments, the dummy gate structure 412 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate structure 412 at a rate faster than the gate spacers 414 and the ILD layer. The gate trench exposes the nanostructure layer 405 and the interbridge layer 401 on the left side of the dielectric wall 410 and the nanostructure layer 407 and the interbridge layer 403 on the right side of the dielectric wall 410. The gate trench also exposes the portion of the dielectric wall 410 located between the gate spacers 414.

[0097] Figure 29A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 29B It corresponds to Figure 29A The cross-sectional view of line B-B' shown. Figure 29A and Figure 29BIn this embodiment, a selective etching process is performed to selectively etch the interbridge layers 401 and 403 exposed in the gate trenches between the gate spacers 414. On the left side of the dielectric wall 410, this selective etching step forms an opening 421A below the nanostructure layer 405A, an opening 421B between nanostructure layers 405A and 405B, and an opening 421C between nanostructure layers 405B and 405C. On the right side of the dielectric wall 410, this selective etching step forms an opening 423A below the nanostructure layer 407A, an opening 423B between nanostructure layers 407A and 407B, and an opening 423C between nanostructure layers 407B and 407C. In some embodiments where the interbridge layers are SiGe, this etching step uses a SiGe selective etchant. Process details regarding the SiGe selective etching step are similar to those previously described. Figures 20A to 20B The process details discussed will not be repeated for the sake of brevity.

[0098] In some embodiments, the etching step selectively etches inter-bridge layers 401 and 403 at a faster etch rate than it etches nanostructure layers 405 and 407. Therefore, nanostructure layers 405 and 407 can remain substantially intact after the selective etching step is completed. In some embodiments, the etching step also etches inter-bridge layers 401A and 403A at a faster etch rate than it etches inter-bridge layers 401B-401C and 403B-403C, which in turn leaves portions 420B and 420C of inter-bridge layers 401B and 401C on the left side of dielectric wall 410, and portions 422B and 422C of inter-bridge layers 403B and 403C on the right side of dielectric wall 410, while leaving no portion of inter-bridge layer 401A on the left side of dielectric wall 410 and no portion of inter-bridge layer 403A on the right side of dielectric wall 410.

[0099] The remaining portions 420B-420C bridge the nanostructure layers 405A-405C, and together form an inverted E-shaped semiconductor channel structure that allows current to flow between the epitaxial source / drain structures 416S and 416D. Therefore, the remaining portions 420B-420C can be referred to as the inter-bridge channel on the left side of the dielectric wall 410, and the nanostructure layers 405A-405C can be referred to as the nanostructure channel on the left side of the dielectric wall 410. The remaining portions 422B-422C bridge the nanostructure layers 407A-407C, and together form an E-shaped semiconductor channel structure that allows current to flow between the epitaxial source / drain structures 418S and 418D. Therefore, the remaining portions 422B-422C can be referred to as the inter-bridge channel on the right side of the dielectric wall 410, and the nanostructure layers 407A-407C can be referred to as the nanostructure channel on the right side of the dielectric wall 410. The inverted E-shaped channel structure is symmetrical to the E-shaped channel structure about the dielectric wall 410, such as Figure 29B As shown in the cross-sectional view.

[0100] In some embodiments where interbridge layers 401A and 403A have a higher germanium atom concentration than interbridge layers 401B-401C and 403B-403C, fluorine-based etchants can etch interbridge layers 401A and 403A at a faster etch rate because the SiGe etch rate increases with the percentage of germanium atoms in the etch step using fluorine-based etchants. In some embodiments where interbridge layers 401B and 401C have substantially the same germanium concentration, the resulting interbridge channels 420B and 420C have substantially the same width, such as... Figure 29B As shown in the figure. In some embodiments where the interbridge layer 401C has a higher germanium atom concentration than the interbridge layer 401B, the resulting interbridge channel 420C has a smaller width than the resulting interbridge channel 420B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for a width difference in the interbridge channel, such as... Figure 8A As shown in the figure. Similarly, in some embodiments where the interbridging layers 403B and 403C have substantially the same germanium concentration, the resulting interbridging channels 422B and 422C have substantially the same width, as shown in the figure. Figure 29B As shown in the figure. In some embodiments where the interbridge layer 403C has a higher germanium atom concentration than the interbridge layer 403B, the resulting interbridge channel 422C has a smaller width than the resulting interbridge channel 422B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for a width difference in the interbridge channel, such as... Figure 8A As shown in the image.

[0101] Figure 30A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 30B It corresponds to Figure 30A The cross-sectional view of line B-B' shown. Figures 30A to 30B In some embodiments, for example, the dielectric wall 410 is removed using a selective etching process. This selective etching process etches the dielectric material of the dielectric wall 410 at a faster etch rate than it etches the semiconductor material of the nanostructured channels 405, 407 and the inter-bridge channels 420, 422. Therefore, after the selective etching process is complete, the nanostructured channels 405, 407 and the inter-bridge channels 420, 422 remain substantially intact. In some embodiments where the dielectric wall 410 is made of silicon oxide (SiO2), the silicon oxide wall 410 can be removed using one or more repeated cyclic processes including plasma treatment and annealing steps. (Previous information regarding...) Figures 21A to 21B The process details of the SiO2 selective etching process were discussed, and therefore will not be repeated for the sake of brevity.

[0102] Figure 31A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 31B It corresponds to Figure 31A The cross-sectional view of line B-B' shown. Figures 31A to 31B In this configuration, an alternative gate structure 424 is formed in the gate trenches between the gate spacers 414 to surround the nanostructure channels 405, 407 and the inter-bridge channels 420, 422 suspended between the gate spacers 314. Therefore, the inverted E-shaped channel structures of the alternating nanostructure channels 405 and 420 share the same gate structure 424 with the E-shaped channel structures of the alternating nanostructure channels 407 and 422. The gate structure 424 may be a high-k / metal gate structure comprising a gate dielectric layer 426 formed around the nanostructure channels 405, 407 and the inter-bridge channels 420, 422, and a gate metal 428 formed around the gate dielectric layer 426. The gate metal 428 may include one or more work-function metal layers formed around the gate dielectric layer 426 and fill metal formed around the one or more work-function metal layers and filling the remaining portion of the gate trench. The material and process details for gate structure 424 are similar to those for gate structure 326, and therefore will not be repeated for the sake of brevity.

[0103] Figures 32A to 40B These are top and cross-sectional views of intermediate stages in the fabrication of nanoFETs according to some embodiments of the present invention. Typically, methods such as... Figures 32A to 40B The nanoFETs fabricated using the steps shown have a spaced E-shaped channel structure surrounded by spaced gate structures. It should be understood that... Figures 32A to 40B Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0104] Figure 32A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 32B It corresponds to Figure 32A The cross-sectional view of line B-B' shown. Figure 32A and Figure 32B In this embodiment, alternating stacked first semiconductor layers (inter-bridging layers) 502A-502C and second semiconductor layers (nanostructure layers) 504A-504C are formed above the substrate 500, and an STI region 508 is formed around the lower part of the fin structure FS. The material and process details of the substrate 500, inter-bridging layers 502A-502C (collectively referred to as 502), nanostructure layers 504A-504C (collectively referred to as 504), and SIT region 508 are similar to those of the previously discussed material and process details of the substrate 300, inter-bridging layer 302, nanostructure layer 304, and SIT region 308, and therefore will not be repeated for the sake of brevity.

[0105] Figure 33A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 33B It corresponds to Figure 33A The cross-sectional view of line B-B' shown. Figure 33A and Figure 33B In this process, a patterned mask layer 509 is formed above a substrate 500, and then the fin structure is anisotropically etched using the patterned mask layer 509 as an etching mask to form trenches 509S that divide the fin structure into two separated fin structures FS1 and FS2. The fin structure FS1 includes alternating inter-bridge layers 501A-501C and nanostructure layers 505A-505C, and the fin structure FS2 includes alternating inter-bridge layers 503A-503C and nanostructure layers 507A-507C.

[0106] The separated interbridging layers 501A and 503A are made of the same material because they are both formed from interbridging layer 502A, such as Figure 32B As shown in the diagram. Separated interbridging layers 501B and 503B have the same material, as they are both formed from interbridging layer 502B. Separated interbridging layers 501C and 503C have the same material, as they are both formed from interbridging layer 502C. In some embodiments, interbridging layers 501A and 503A may have a higher germanium atom concentration than the upper interbridging layers 501B-501C and 503B-503C, which in turn allows for the removal of the bottom interbridging layers 501A and 503A, while leaving portions of the upper interbridging layers 501B-501C and 503B-503C for use as interbridging channels in subsequent SiGe selective etching processes.

[0107] The separated nanostructure layers 505A and 507A are made of the same material, as they are both formed from nanostructure layer 504A. The separated nanostructure layers 505B and 507B are made of the same material, as they are both formed from nanostructure layer 504B. The separated nanostructure layers 505C and 507C are made of the same material, as they are both formed from nanostructure layer 504C. In some embodiments, nanostructure layers 505A-505C and 507A-507C are silicon and substantially free of germanium.

[0108] Figure 34A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 34B It corresponds to Figure 34A The cross-sectional view of line B-B' shown. Figure 34A and Figure 34BIn the trench 509S, an outer dielectric wall 510 is formed to electrically isolate the fin structures FS1 and FS2, and an inner dielectric wall 511 is formed above the outer dielectric wall. The outer dielectric wall 510 and the inner dielectric wall 511 can be formed, for example, by sequentially depositing a first dielectric layer and a second dielectric layer in the trench 509S until the trench 509S is overfilled, followed by a CMP process to remove excess dielectric material outside the trench 509S, while leaving a portion of the first dielectric layer in the trench 509S as the outer dielectric wall 510 and a portion of the second dielectric layer in the trench 509S as the inner dielectric wall 511.

[0109] In some embodiments, dielectric walls 510 and 511 comprise silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable dielectric materials, and are deposited using, for example, CVD, ALD, PVD, or other suitable deposition techniques. In some embodiments, the outer dielectric wall 510 has a different material than the inner dielectric wall 511 and therefore has a different etch selectivity. For example, the outer dielectric wall 510 comprises silicon oxide, and the inner dielectric wall 511 comprises silicon nitride (Si3N4) or other dielectric materials besides silicon oxide.

[0110] Figure 35A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 35B It corresponds to Figure 35A The cross-sectional view of line B-B' shown. Figure 35A and Figure 35B In the next step, a dummy gate structure 512 is formed above the fin structures FS1 and FS2. The dummy gate structure 512 has a longitudinal direction perpendicular to the longitudinal direction of the fin structures FS1 and FS2. Next, a gate spacer 514 is formed on the sidewall of the dummy gate structure 512. The material and process details of the dummy gate structure 512 and the gate spacer 514 are similar to those of the dummy gate structure 312 and the gate spacer 314 discussed previously, and therefore will not be repeated for the sake of brevity.

[0111] Figure 36A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 36B It corresponds to Figure 36A The cross-sectional view of line B-B' shown. Figure 36A and Figure 36BIn the process, the fin structures FS1 and FS2 extend beyond the recessed portions of the gate structure 512 and the gate spacer 514, and then epitaxial source / drain structures 516S and 516D are formed on the recessed portions of the fin structure FS1, and epitaxial source / drain structures 518S and 518D are formed on the recessed portions of the fin structure FS2. The epitaxial growth time / duration is controlled so that the top positions of the epitaxial source / drain structures 516S, 516D, 518S, and 518D are lower than the top positions of the dielectric walls 510, 511, and 518D. Therefore, the epitaxial source structure 516S is completely spaced from the epitaxial source structure 518S by the dielectric walls 510 and 511, and the epitaxial drain structure 516D is completely spaced from the epitaxial drain structure 518D by the dielectric walls 510 and 511. The material and process details for the epitaxial source / drain structures 516S, 516D, 518S, and 518D are similar to those for the previously discussed epitaxial source / drain structure 322, and therefore will not be repeated for the sake of brevity.

[0112] Figure 37A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 37B It corresponds to Figure 37A The cross-sectional view of line B-B' shown. Figure 37A and Figure 37B In one or more etching steps, the dummy gate structure 512 is removed, thereby forming a gate trench between the corresponding gate spacers 514. In some embodiments, an ILD layer is formed over the epitaxial source / drain structures 516S, 516D, 518S, 518D before the dummy gate structure 512 is removed. In some embodiments, the dummy gate structure 512 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate structure 512 at a rate faster than the gate spacers 514 and the ILD layer. The gate trench exposes the nanostructure layer 505 and the interbridge layer 501 on the left side of the dielectric walls 510, 511 and the nanostructure layer 507 and the interbridge layer 503 on the right side of the dielectric walls 510, 511. The gate trench also exposes the portions of the dielectric walls 510, 511 located between the gate spacers 514.

[0113] Figure 38A This is a top view of an intermediate stage in the fabrication of nanoFETs, and Figure 38B It corresponds to Figure 38A The cross-sectional view of line B-B' shown. Figure 38A and Figure 38BIn this embodiment, a selective etching process is performed to selectively etch the interbridge layers 501 and 503 exposed in the gate trenches between the gate spacers 514. On the left side of the dielectric walls 510, 511, this selective etching step forms an opening 521A below the nanostructure layer 505A, an opening 521B between nanostructure layers 505A and 505B, and an opening 521C between nanostructure layers 505B and 505C. On the right side of the dielectric wall 510, this selective etching step forms an opening 523A below the nanostructure layer 507A, an opening 523B between nanostructure layers 507A and 507B, and an opening 523C between nanostructure layers 507B and 507C. In some embodiments where the interbridge layers are SiGe, this etching step uses a SiGe selective etchant. Process details regarding the SiGe selective etching step are similar to those previously described. Figures 20A to 20B The process details discussed will not be repeated for the sake of brevity.

[0114] In some embodiments, the etching step selectively etches inter-bridge layers 501 and 503 at a faster etch rate than it etches nanostructure layers 505 and 507. Therefore, nanostructure layers 505 and 507 can remain substantially intact after the selective etching step is completed. In some embodiments, the etching step also etches inter-bridge layers 501A and 503A at a faster etch rate than it etches inter-bridge layers 501B-501C and 503B-503C, which in turn leaves portions 520B and 520C of inter-bridge layers 501B and 501C on the left side of dielectric walls 510 and 511, and portions 522B and 522C of inter-bridge layers 503B and 503C on the right side of dielectric walls 510 and 511, while leaving no portion of inter-bridge layer 501A on the left side of dielectric walls 510 and 511, and no portion of inter-bridge layer 503A on the right side of dielectric walls 510 and 511.

[0115] The remaining portions 520B-520C bridge the nanostructure layers 505A-505C, and together form an inverted E-shaped semiconductor channel structure that allows current to flow between the epitaxial source / drain structures 516S and 516D. Therefore, the remaining portions 520B-520C can be referred to as the inter-bridge channel on the left side of the dielectric walls 510 and 511, and the nanostructure layers 505A-505C can be referred to as the nanostructure channel on the left side of the dielectric walls 510 and 511. The remaining portions 522B-522C bridge the nanostructure layers 507A-507C, and together form an E-shaped semiconductor channel structure that allows current to flow between the epitaxial source / drain structures 518S and 518D. Therefore, the remaining portions 522B-522C can be referred to as inter-bridge channels on the right side of dielectric walls 510 and 511, and the nanostructure layers 507A-507C can be referred to as nanostructure channels on the right side of dielectric walls 510 and 511. The inverted E-shaped channel structure is symmetrical to the E-shaped channel structure about dielectric walls 510 and 511, as shown below. Figure 38B As shown in the cross-sectional view.

[0116] In some embodiments where interbridge layers 501A and 503A have a higher germanium atom concentration than interbridge layers 501B-501C and 503B-503C, fluorine-based etchants can etch interbridge layers 501A and 503A at a faster etch rate because the SiGe etch rate increases with the percentage of germanium atoms in the etch step using fluorine-based etchants. In some embodiments where interbridge layers 501B and 501C have substantially the same germanium concentration, the resulting interbridge channels 520B and 520C have substantially the same width, such as... Figure 38B As shown in the figure. In some embodiments where the interbridge layer 501C has a higher germanium atom concentration than the interbridge layer 501B, the resulting interbridge channel 520C has a smaller width than the resulting interbridge channel 520B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for a width difference in the interbridge channel, such as... Figure 8A As shown in the figure. Similarly, in some embodiments where the interbridging layers 503B and 503C have substantially the same germanium concentration, the resulting interbridging channels 522B and 522C have substantially the same width, as shown in the figure. Figure 38B As shown in the figure. In some embodiments where the interbridge layer 503C has a higher germanium atom concentration than the interbridge layer 503B, the resulting interbridge channel 522C has a smaller width than the resulting interbridge channel 522B. This is due to the difference in etching rate caused by the fluorine-based etchant, which in turn allows for a width difference in the interbridge channel, such as... Figure 8A As shown in the image.

[0117] Figure 39A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 39B It corresponds to Figure 39AThe cross-sectional view of line B-B' shown. Figures 39A to 39B In some embodiments, the outer dielectric wall 510 is recessed using a selective etching process. This selective etching process etches the dielectric material of the outer dielectric wall 510 at a faster etch rate than it etches the dielectric material of the inner dielectric wall 511 and the semiconductor material of the nanostructured channels 505, 507 and the interbridge channels 520, 522, and 522. Therefore, after the selective etching process is complete, the inner dielectric wall 511, the nanostructured channels 505, 507, and the interbridge channels 520, 522 remain substantially intact. In some embodiments where the outer dielectric wall 510 is made of silicon oxide (SiO2), the silicon oxide wall 510 can be selectively etched using one or more repeated cyclic processes including plasma treatment and annealing steps. Previous discussions on... Figures 21A to 21B Process details regarding the SiO2 selective etching process have been discussed and will therefore not be repeated for the sake of brevity. In some embodiments of the SiO2 selective etching process, the etching rate ratio of the outer dielectric wall 510 (SiO2) to the inner dielectric wall 511 (Si3O4) is in the range of about 3:1 to about 8:1 (e.g., about 4:1). After the SiO2 selective etching process is completed, a portion 524 of the outer dielectric wall 510 remains in the substrate 500, and the remaining portion 524 may have a position above the top of the STI region 508.

[0118] Figure 40A This is a top view of an intermediate stage in the fabrication of nanoFETs. Figure 40B It corresponds to Figure 40A The cross-sectional view of line B-B' shown. Figures 40A to 40B In this configuration, two separate, alternating gate structures 526A and 526B are formed in a gate trench between gate spacers 514. Gate structure 526A is formed on the left side of the inner dielectric wall 511 to surround the nanostructure channel 505 and the inter-bridge channel 520. Gate structure 526B is formed on the right side of the inner dielectric wall 511 to surround the nanostructure channel 507 and the inter-bridge channel 522. Thus, the alternating left-side channel structures of the nanostructure channel 505 and the inter-bridge channel 520, and the alternating right-side channel structures of the nanostructure channel 507 and the inter-bridge channel 522, are controlled by different gate structures 526A and 526B. Gate structures 526A and 526B are each high-k / metal gate structures comprising a gate dielectric layer 528 and a gate metal 530 formed around the gate dielectric layer 528. The gate metal 530 may include one or more function metal layers formed around the gate dielectric layer 528 and fill metal formed around the one or more function metal layers and filling the remaining portion of the gate trench. The materials of the gate structures 526A and 526B are similar to those of the gate structure 326, and therefore will not be repeated for the sake of brevity.

[0119] In some embodiments, forming gate structures 526A and 526B may include: depositing one or more dielectric material layers and one or more metal material layers; and performing a CMP process on the one or more dielectric material layers and one or more metal material layers until the inner dielectric wall 511 is exposed, thereby leaving a first portion of one or more dielectric material layers and one or more metal material layers on the left side of the inner dielectric wall 511 for use as gate structure 526A, and leaving a second portion of one or more dielectric material layers and one or more metal material layers on the right side of the inner dielectric wall 511 for use as gate structure 526B. In such embodiments, gate structures 526A and 526B may comprise the same material.

[0120] Figure 41 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention. Figure 41 In this embodiment, a nano-FET is formed on a substrate 600 and includes a channel structure CH6 and a gate structure 610 extending above the channel structure CH6 and the STI region 608. The channel structure CH6 includes alternating nanostructured channels NS1-NS3 and interbridge channels IB1 and IB2, and also includes a foot channel FT extending from the bottommost nanostructured channel NS1 to the fin of the substrate 600. The foot channel FT may be the remainder of the bottommost interbridge layer 302A, such as... Figure 19B As shown in the image.

[0121] In some embodiments, the base channel FT has a germanium atom concentration and width substantially the same as the inter-bridge channels IB1 and IB2. In some embodiments, the base channel FT has a higher germanium atom concentration and a smaller width than the inter-bridge channels IB1 and IB2. In some other embodiments, the base channel FT has a lower germanium atom concentration and a larger width than the inter-bridge channels IB1 and IB2. The gate structure 610 includes a gate dielectric layer 612 above the channel structure CH6 and a gate metal 614 above the gate dielectric layer 612.

[0122] Figure 42 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention. Figure 42 In this design, a nano-FET is formed on a substrate 700 and includes a channel structure CH7 and a gate structure 710 extending above the channel structure CH7 and the STI region 708. The channel structure CH7 includes alternating nanostructured channels NS1-NS3 and inter-bridge channels IB1 and IB2, and also includes a fin-based foot channel FT extending from the bottommost nanostructured channel NS1 to the substrate 700, and a hair-like channel HR extending upward from the topmost nanostructured channel NS3. The hair-like channel HR can be, for example, in... Figure 10B An additional interbridging layer is formed on top of the nanostructured layer 304C shown, and then, as shown... Figure 20B In the steps shown, additional interbridge layers are selectively etched to form the HR (Hair Channel) to create the channel.

[0123] In some embodiments, the humeral channel HR has a germanium atom concentration and width substantially the same as the interbridge channels IB1 and IB2 and the base channel FT. In some embodiments, the humeral channel HR has a higher germanium atom concentration and a smaller width than the interbridge channels IB1 and IB2 and the base channel FT. In some other embodiments, the humeral channel HR has a lower germanium atom concentration and a larger width than the interbridge channels IB1 and IB2 and the base channel FT. The gate structure 710 includes a gate dielectric layer 712 above the channel structure CH7 and a gate metal 714 above the gate dielectric layer 712.

[0124] Figure 43 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention. Figure 43 In this embodiment, a nano-FET is formed on a substrate 800 and includes a channel structure CH8 and a gate structure 810 extending above the channel structure CH8 and the STI region 808. The gate structure 810 includes a gate dielectric layer 812 above the channel structure CH8 and a gate metal 814 above the gate dielectric layer 812. The channel structure CH8 includes alternating nanostructure channels NS1-NS3 and inter-bridge channels IB1 and IB2, and also includes a hair channel HR extending upward from the topmost nanostructure channel NS3, and a fin-type base channel FT extending downward from the bottommost nanostructure NS1 to the substrate 800. The base channel FT may be the remainder of the bottommost inter-bridge layer 302A, such as... Figure 19B As shown in the diagram. The HR channel can be, for example, in... Figure 10B An additional interbridging layer is formed on top of the nanostructured layer 304C shown, and then, as shown... Figure 20B In the steps shown, additional interbridge layers are selectively etched to form the HR (Hair Channel) to create the channel.

[0125] exist Figure 43 In the diagram, the left sides of the interbridge channels IB1, IB2, the foot channel FT, and the pore channel HR laterally retract from the left sides of the nanostructure structures NS1-NS3. This lateral offset profile can be formed, for example, by selectively etching the interbridge channels IB1, IB2, the foot channel FT, and the pore channel HR after removing the dielectric wall 310 from the left sides of the interbridge channels IB1, IB2, the foot channel FT, and the pore channel HR, as shown below. Figure 21B The steps are shown below.

[0126] Figure 44 This is a cross-sectional view of a nanoFET according to some embodiments of the present invention. Figure 44In this embodiment, a nano-FET is formed on a substrate 900 and includes a channel structure CH9 and a gate structure 910 extending above the channel structure CH9 and the STI region 908. The gate structure 910 includes a gate dielectric layer 912 above the channel structure CH9 and a gate metal 914 above the gate dielectric layer 912. The channel structure CH9 includes alternating nanostructure channels NS1-NS3 and inter-bridge channels IB11-IB32, and also includes hair channels HR1-HR3 extending upward from the topmost nanostructure channel NS3, and fin-based channels FT1-FT3 extending downward from the bottommost nanostructure channel NS1 to the substrate 900. The base channel FT1, inter-bridge channels IB11, IB12, and pore channel HR1 are confined to a first region R1 of the nanostructure channels NS1-NS3; the base channel FT2, inter-bridge channels IB21, IB22, and pore channel HR2 are confined to a second region R2 of the nanostructure channels NS1-NS3, spaced apart from the first region R1; and the base channel FT3, inter-bridge channels IB31, IB32, and pore channel HR3 are confined to a third region R3 of the nanostructure channels NS1-NS3, spaced apart from the first region R1 and the second region R2. The channel structure CH9 can be formed, for example, by forming an alternating stack of first and second semiconductor layers, forming a patterned mask covering the regions R1-R3, selectively etching the portion of the second semiconductor layer exposed by the patterned mask, and then removing the patterned mask from the regions R1-R3.

[0127] Based on the above discussion, it can be seen that the present invention provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be disclosed herein, and no specific advantage is necessary for all embodiments. One advantage is that the on-state current of the transistor can be enhanced by adding inter-bridge channels between adjacent nanostructure channels. Another advantage is that the on-state current enhancement can be further increased by forming inter-bridge channels confined to the peripheral or eccentric regions of the nanostructure channels.

[0128] In some embodiments, the device includes: source / drain regions located above a substrate and spaced apart along a first direction; a first gate structure located between the source / drain regions; and a first channel structure surrounded by the first gate structure. The first channel structure includes alternately stacked first and second semiconductor layers. When viewed in a cross-section taken along a second direction perpendicular to the first direction, the central axis of the second semiconductor layer is laterally offset from the central axis of the first semiconductor layer. In some embodiments, the second semiconductor layer has a smaller width than the first semiconductor layer. In some embodiments, the second semiconductor layer is made of a different material than the first semiconductor layer. In some embodiments, the second semiconductor layer has a larger percentage of germanium atoms than the first semiconductor layer. In some embodiments, the second semiconductor layers have substantially the same width. In some embodiments, the upper portion of the second semiconductor layer has a smaller width than the lower portion of the second semiconductor layer. In some embodiments, the width difference between the second semiconductor layers is greater than the width difference between the first semiconductor layers. In some embodiments, the second semiconductor layers have different percentages of germanium atoms. In some embodiments, the upper portion of the second semiconductor layer has a larger percentage of germanium atoms than the lower portion of the second semiconductor layer. In some embodiments, the device further includes: a second channel structure surrounded by the first gate structure, and the second channel structure being symmetrical to the first channel structure when viewed in a cross-section taken along a second direction. In some embodiments, the device further includes: a second channel structure symmetrical to the first channel structure when viewed in a cross-section taken along a second direction; a second gate structure surrounding the second channel structure; and a dielectric wall separating the first gate structure from the second gate structure.

[0129] In some embodiments, the device includes: a source region; a drain region separated from the source region along a first direction; and a channel structure between the source and drain regions. The channel structure includes alternately stacked first and second semiconductor layers. When viewed in a cross-section taken along a second direction perpendicular to the first direction, the first semiconductor layer has opposing first and second sides, and the second semiconductor layer has opposing third and fourth sides, the third side of the second semiconductor layer being aligned with the first side of the first semiconductor layer, and the fourth side of the second semiconductor layer laterally receding from the second side of the first semiconductor layer. In some embodiments, the central axis of the second semiconductor layer does not overlap with that of the first semiconductor layer. In some embodiments, the width of the second semiconductor layer is less than half the width of the first semiconductor layer. In some embodiments, the fourth sides of the second semiconductor layer are not aligned with each other. In some embodiments, the first semiconductor layer is a germanium-free semiconductor layer, and the second semiconductor layer is a germanium-containing semiconductor layer.

[0130] In some embodiments, the method includes: forming a fin structure having alternating first and second semiconductor layers over a substrate; forming a dielectric wall on a first longitudinal side of the fin structure but not on a second longitudinal side of the fin structure; performing a first etching process to etch the second semiconductor layer at an etch rate faster than etching the first semiconductor layer; performing a second etching process after performing the first etching process to remove the dielectric wall; and forming a gate structure over the first and second semiconductor layers after removing the dielectric wall. In some embodiments, the first etching process etches the bottommost one of the second semiconductor layers at an etch rate faster than etching the upper semiconductor layer. In some embodiments, the second etching process etches the dielectric wall at an etch rate faster than etching the first and second semiconductor layers. In some embodiments, the method further includes: recessing a portion of the fin structure after forming the dielectric wall; and forming an epitaxial source / drain structure on the recessed portion of the fin structure that contacts the side of the dielectric wall.

[0131] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: Source / drain regions are located above the substrate and spaced apart along a first direction; A first gate structure is located between the source and drain regions; Multiple gate spacers are located on multiple sidewalls of the first gate structure; as well as A first channel structure is surrounded by the first gate structure. The first channel structure includes alternating stacked first and second semiconductor layers, wherein, when viewed in cross-section, the central axis of the second semiconductor layer is laterally offset from the central axis of the first semiconductor layer, and the cross-section cuts through the first gate structure and the first channel structure along a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein, The second semiconductor layer has a smaller width than the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein, The second semiconductor layer is made of a different material than the first semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The second semiconductor layer has a higher percentage of germanium atoms than the first semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The second semiconductor layer has the same width.

6. The semiconductor device according to claim 1, wherein, The upper second semiconductor layer in the second semiconductor layer has a smaller width than the lower second semiconductor layer in the second semiconductor layer.

7. The semiconductor device according to claim 1, wherein, The width difference between the second semiconductor layers is greater than the width difference between the first semiconductor layers.

8. The semiconductor device according to claim 1, wherein, The second semiconductor layer has a different percentage of germanium atoms.

9. The semiconductor device according to claim 1, wherein, The upper second semiconductor layer in the second semiconductor layer has a larger percentage of germanium atoms than the lower second semiconductor layer in the second semiconductor layer.

10. The semiconductor device according to claim 1, further comprising: The second channel structure, surrounded by the first gate structure, is symmetrical to the first channel structure when viewed in a cross-section taken along the second direction.

11. The semiconductor device according to claim 1, further comprising: The second channel structure is symmetrical to the first channel structure when viewed in a cross-section taken along the second direction; A second gate structure, surrounding the second channel structure; and A dielectric wall separates the first gate structure from the second gate structure.

12. A semiconductor device, comprising: Source region; The drain region is separated from the source region along a first direction; as well as A channel structure, situated between the source region and the drain region, comprising alternately stacked first and second semiconductor layers, wherein, when viewed in a cross-section taken along a second direction perpendicular to the first direction, the first semiconductor layer has opposing first and second sides, the second semiconductor layer has opposing third and fourth sides, the third side of the second semiconductor layer being aligned with the first side of the first semiconductor layer, and the fourth side of the second semiconductor layer laterally retracting from the second side of the first semiconductor layer.

13. The semiconductor device according to claim 12, wherein, The central axis of the second semiconductor layer does not overlap with that of the first semiconductor layer.

14. The semiconductor device according to claim 12, wherein, The width of the second semiconductor layer is less than half the width of the first semiconductor layer.

15. The semiconductor device according to claim 12, wherein, The fourth sides of the second semiconductor layer are not aligned with each other.

16. The semiconductor device according to claim 12, wherein, The first semiconductor layer is a germanium-free semiconductor layer, and the second semiconductor layer is a germanium-containing semiconductor layer.

17. A method of forming a semiconductor device, comprising: A fin structure with alternating first and second semiconductor layers is formed above a substrate; A dielectric wall is formed on the first longitudinal side of the fin structure, rather than on the second longitudinal side of the fin structure; A first etching process is performed to etch the second semiconductor layer at a faster etching rate than the first semiconductor layer. After performing the first etching process, a second etching process is performed to remove the dielectric wall; as well as After removing the dielectric walls, a gate structure is formed over the first semiconductor layer and the second semiconductor layer.

18. The method according to claim 17, wherein, The first etching process etches the bottommost second semiconductor layer in the second semiconductor layer at a faster etching rate than the etching of the upper semiconductor layer.

19. The method of claim 17, wherein, The second etching process etches the dielectric wall at a faster etching rate than etching the first semiconductor layer and the second semiconductor layer.

20. The method of claim 17, further comprising: After the dielectric wall is formed, a portion of the fin structure is recessed; as well as An epitaxial source / drain structure is formed on the recessed portion of the fin structure, and the epitaxial source / drain structure contacts the side of the dielectric wall.

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