A GaN-based double-layer passivation recessed gate enhancement MIS-HEMT device and a preparation method thereof

Abstract

The application discloses a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof. The device comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer, wherein the two sides of the barrier layer are respectively provided with a first isolation area and a second isolation area; the inner sides of the first isolation area and the second isolation area are respectively provided with a drain electrode and a source electrode, at least a part of the drain electrode and the source electrode are embedded in the barrier layer, and the lower surfaces of the drain electrode and the source electrode are in contact with the channel layer; a gate area groove is formed on the barrier layer between the drain electrode and the source electrode; the inner surface of the gate area groove and the upper surface of the barrier layer are coated with a double-layer passivation layer; and a gate electrode is arranged on the double-layer passivation layer in the gate area groove. The double-layer passivation layer forms an insulating layer in the vertical channel direction, blocks the transportation of carriers in the vertical direction, and makes the device have the characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and particularly relates to a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof. BACKGROUND

[0002] High Electron Mobility Transistors (HEMT) based on AlGaN / GaN have excellent characteristics of high temperature resistance and high voltage resistance, and are widely used in the fields of power electronics, wireless communication and radio frequency. With the increasing requirements of device performance in various application fields, there are still some problems of gate electrode reliability of AlGaN / GaN-based HEMT devices to be solved.

[0003] The gate electrode of a conventional GaN-based Schottky HEMT has serious leakage, and since the GaN material itself has a large number of dislocations and defects, the charges are compounded by the surface state, thereby causing a serious current collapse phenomenon. In order to solve this problem, people have proposed a method of using Al2O3, SiN4 and SiO2 dielectric passivation layer as the gate insulating layer of MIS (metal-insulator-semiconductor)-HEMT, which has inhibited the gate electrode leakage of the device to a certain extent and improved the current collapse problem, but the insulating layer medium under the gate electrode also causes certain reliability problems of the device, resulting in a decrease in the current cutoff frequency of the device and an increase in the PBTI (positive bias temperature instability) effect, thereby limiting the wide application of the GaN-based MIS-HEMT device. SUMMARY

[0004] In order to solve the above problems in the prior art, the application provides a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical scheme:

[0005] One aspect of the application provides a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer, wherein,

[0006] The first isolation region and the second isolation region are respectively arranged on both sides of the barrier layer, and the first isolation region and the second isolation region extend from the upper surface of the barrier layer to the upper surface of the buffer layer;

[0007] The inner sides of the first isolation region and the second isolation region are respectively provided with a drain electrode and a source electrode, at least a part of the drain electrode and at least a part of the source electrode are embedded in the barrier layer, and the lower surfaces of the drain electrode and the source electrode are in contact with the channel layer and form ohmic contact;

[0008] A gate region groove is formed in the barrier layer between the drain electrode and the source electrode, the inner surface of the gate region groove and the upper surface of the barrier layer are coated with a double-layer passivation layer, and a gate electrode is arranged on the double-layer passivation layer in the gate region groove.

[0009] In an embodiment of the present application, the double-layer passivation layer comprises a Si passivation layer and a SiO2 passivation layer, wherein,

[0010] The Si passivation layer is located in the gate region groove and grows outward along the mesa of the gate region groove, so that the cross section is U-shaped.

[0011] The SiO2 passivation layer covers the upper surface of the Si passivation layer and the upper surface of the barrier layer between the drain electrode and the source electrode, and is in contact with the source electrode and the drain electrode respectively.

[0012] In an embodiment of the present application, the thickness of the Si passivation layer is 1-5 nm, and the thickness of the SiO2 passivation layer is 5-100 nm.

[0013] In an embodiment of the present application, the lower end of the gate region groove extends to the upper surface of the channel layer.

[0014] In an embodiment of the present application, the barrier layer is an Al x Ga 1-x N barrier layer with a thickness of 10-30 nm, and x=0.1-0.5.

[0015] In an embodiment of the present application, the nucleation layer is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer is an AlGaN buffer layer with a thickness of 200-8000 nm, and the channel layer is a GaN channel layer with a thickness of 50-500 nm.

[0016] Another aspect of the present application provides a preparation method of a GaN-based double-layer passivation groove gate enhanced MIS-HEMT device, comprising:

[0017] S1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence;

[0018] S2: performing ion implantation on both sides of the barrier layer to form a first isolation region and a second isolation region extending to the upper surface of the buffer layer respectively;

[0019] S3: etching in the middle of the upper surface of the barrier layer to form a gate region groove extending to the upper surface of the channel layer;

[0020] S4: growing a double-layer passivation layer in the gate region groove and on the remaining upper surface area of the barrier layer;

[0021] S5: depositing a gate electrode metal on the double-layer passivation layer above the gate region groove to form a gate electrode;

[0022] S6: forming a source electrode and a drain electrode on both sides of the gate electrode respectively, and the lower surface of the source electrode and the lower surface of the drain electrode both contact the upper surface of the channel layer.

[0023] In an embodiment of the present application, the S1 comprises:

[0024] S11: selecting a Si, SiC or sapphire substrate, and performing plasma cleaning and surface pretreatment on the surface of the substrate to keep the surface of the substrate clean;

[0025] S12: sequentially epitaxially growing an AlN nucleation layer with a thickness of 50-500 nm, an AlGaN buffer layer with a thickness of 200-8000 nm, an intrinsic GaN channel layer with a thickness of 50-500 nm, an Al x Ga 1-x N barrier layer with a thickness of 10-30 nm and x=0.1-0.5 on the substrate.

[0026] In an embodiment of the present application, the S4 comprises:

[0027] S41: growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer and in the gate region groove by using a CVD technique;

[0028] S42: etching away the Si passivation layer on the surface of the barrier layer away from the gate region groove to form a U-shaped Si passivation layer in the gate region groove;

[0029] S43: depositing a 5-100 nm SiO2 layer on the Si passivation layer and the upper surface of the barrier layer by using a PECVD process to form a SiO2 passivation layer.

[0030] In an embodiment of the present application, the S6 comprises:

[0031] S61: etching a source region groove and a drain region groove extending to the upper surface of the channel layer on both sides of the gate electrode by using a photolithography process;

[0032] S62: Metal deposition is performed in the source region recess and the drain region recess using a sputtering or e-beam evaporation process, followed by a lift-off process and annealing, to form the source electrode and the drain electrode.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] 1. The present application provides a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device, which comprises a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, a double-layer passivation layer, a gate electrode, a source electrode and a drain electrode, wherein the double-layer passivation layer is composed of a Si passivation layer and a SiO2 passivation layer, there is a gate region recess on the side of the barrier layer close to the source electrode, the Si passivation layer is grown in the recess and partially grown outward along the mesa of the barrier layer recess, and the cross section is U-shaped, and the SiO2 passivation layer is grown on the upper surface of the Si passivation layer and the barrier layer. The double-layer passivation layer structure is formed by the Si passivation layer grown in the barrier layer recess and partially grown outward along the mesa of the barrier layer recess, and the SiO2 layer on the upper surface of the barrier layer and the Si passivation layer. The double-layer passivation layer forms an insulating layer in the vertical channel direction, thereby blocking the transport of carriers in the vertical direction, and the device has the significant characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

[0035] 2. The present application provides a preparation method of a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device, which uses Si and SiO2 as the double-layer passivation layer, avoids the problems of high surface trap concentration, reduced device output current and current collapse effect caused by a series of interface state problems of the traditional gate electrode insulating layer, and effectively improves the gate electrode voltage resistance and the reliability of the device.

[0036] 3. The present application provides a preparation method of a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device, which uses the double-layer passivation structure of the Si passivation layer and the SiO2 passivation layer to reduce the surface state of the passivation layer, and has better passivation effect than the HEMT structure without a passivation layer and the single-layer passivation layer structure.

[0037] 4. The process of the present application is relatively simple and compatible with the current traditional GaN HEMT process.

[0038] The present application will be further described in detail below with reference to the accompanying drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a structure schematic diagram of a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device provided by an embodiment of the present application;

[0040] Figure 2A flow chart of a preparation method of a GaN-based double-layer passivation recessed gate enhanced MIS-HEMT device is provided in the embodiments of the present application.

[0041] Figures 3a to 3h A preparation process schematic diagram of a GaN-based double-layer passivation recessed gate enhanced MIS-HEMT device is provided in the embodiments of the present application.

[0042] Explanation of reference signs:

[0043] 1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-first isolation region; 6-potential barrier layer; 7-drain electrode; 8-gate electrode; 9-source electrode; 10-double-layer passivation layer; 101-Si passivation layer; 102-SiO2 passivation layer; 11-second isolation region; 12-gate region recess. DETAILED DESCRIPTION

[0044] In order to further illustrate the technical means and effects taken by the present application to achieve the predetermined purposes, the GaN-based double-layer passivation recessed gate enhanced MIS-HEMT device and the preparation method thereof according to the present application are described in detail below in combination with the drawings and specific embodiments.

[0045] The foregoing and other technical contents, features and effects of the present application can be clearly presented in the detailed description of the specific embodiments below in combination with the drawings. Through the description of the specific embodiments, the technical means and effects taken by the present application to achieve the predetermined purposes can be understood more deeply and specifically. However, the attached drawings are provided for reference and illustration only, and are not intended to limit the technical solutions of the present application.

[0046] It should be noted that, in this document, relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by an utterance "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0047] Embodiment one

[0048] Please refer to Figure 1 , Figure 1is a structure schematic diagram of a GaN-based double-passivation groove gate enhanced MIS-HEMT device provided by an embodiment of the present application. The device comprises, from bottom to top, a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 6, wherein the barrier layer 6 is provided with a first isolation region 5 and a second isolation region 11 on both sides thereof, the first isolation region 5 and the second isolation region 11 extend from the upper surface of the barrier layer 6 to the upper surface of the buffer layer 3; the inner side of the first isolation region 5 and the second isolation region 11 is provided with a drain electrode 7 and a source electrode 9 respectively, at least a part of the drain electrode 7 and at least a part of the source electrode 9 are embedded in the barrier layer 6, the lower surface of the drain electrode 7 and the lower surface of the source electrode 9 are in contact with the channel layer 4 and form an ohmic contact; a gate region groove 12 is formed on the barrier layer 6 between the drain electrode 7 and the source electrode 9, the inner surface of the gate region groove 12 and the upper surface of the barrier layer 6 are coated with a double-passivation layer 10; the double-passivation layer 10 located in the gate region groove 12 is provided with a gate electrode 8.

[0049] In the embodiment, the material of the substrate 1 is n + GaN, SiC, sapphire or Si. Further, the nucleation layer 2 is an AlN nucleation layer with a thickness of 50-400 nm, the buffer layer 3 is an AlGaN buffer layer with a thickness of 200-8000 nm, the channel layer 4 is a GaN channel layer with a thickness of 50-500 nm, and the barrier layer 5 is an AlGaN barrier layer with a thickness of 10-30 nm. x Ga 1-x N barrier layer, wherein x=0.1-0.5.

[0050] The first isolation region 5 and the second isolation region 11 are N ion implantation regions formed by N ion implantation in the barrier layer 6 and the channel layer 4. N ion implantation is performed in the first isolation region 5 and the second isolation region 11 to form a high resistance region, so as to realize device isolation.

[0051] Further, the double-passivation layer 10 comprises a Si passivation layer 101 and a SiO2 passivation layer 102, wherein the Si passivation layer 101 is located in the gate region groove 12 and grows outward along the mesa of the gate region groove 12, so that the cross section is U-shaped; the SiO2 passivation layer 102 covers the upper surface of the Si passivation layer 101 and the upper surface of the barrier layer 6 between the drain electrode 7 and the source electrode 9, and is in contact with the source electrode 9 and the drain electrode 7 on both sides. Preferably, the thickness of the Si passivation layer 101 is 1-5 nm, and the thickness of the SiO2 passivation layer is 5-100 nm.

[0052] Further, the lower end of the gate region recess 12 extends to the upper surface of the channel layer 4. The outer side of the drain electrode 7 contacts the inner surface of the first isolation region 5, and the outer side of the source electrode 9 contacts the inner surface of the second isolation region 11. The lower surface of the drain electrode 7 forms an ohmic contact through the barrier layer 6 and the channel layer 4, and the lower surface of the source electrode 9 forms an ohmic contact through the barrier layer 6 and the channel layer 4.

[0053] Preferably, the source electrode 9, the gate electrode 8 and the drain electrode 7 are made of the same material, which is a Ti / Al-containing metal combination.

[0054] The embodiment of the present application provides a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device, which comprises a substrate, a nucleation layer, a buffer layer, a device isolation region, a channel layer, a barrier layer, a double-layer passivation layer, a gate electrode, a source electrode and a drain electrode. The double-layer passivation layer is composed of a Si passivation layer and a SiO2 passivation layer. There is a gate region recess on the side of the barrier layer close to the source electrode. The Si passivation layer is grown in the recess and partially grown outward along the mesa of the recess of the barrier layer, and the cross section of the Si passivation layer is U-shaped. The SiO2 passivation layer is grown on the upper surface of the Si passivation layer and the barrier layer. The double-layer passivation layer structure is formed by the Si passivation layer which is respectively formed in the recess of the barrier layer and partially grown outward along the mesa of the recess of the barrier layer, and the SiO2 layer on the upper surface of the barrier layer and the Si passivation layer. The double-layer passivation layer forms an insulating layer in the vertical direction of the channel, thereby blocking the transport of carriers in the vertical direction, so that the device has the significant characteristics of low interface state defect density, small PBTI effect and stable threshold voltage.

[0055] Embodiment two

[0056] On the basis of the embodiment one, the embodiment provides a preparation method of the GaN-based double-layer passivation recess gate enhanced MIS-HEMT device, please refer to Figure 2 、 Figures 3a to 3g , the preparation method comprises the following steps:

[0057] S1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence.

[0058] Selecting an n + -GaN, Si, SiC or sapphire substrate 1, and performing plasma cleaning and surface pretreatment on the surface of the substrate 1 to keep the surface of the substrate clean; then, epitaxially growing an AlN nucleation layer 2 with a thickness of 50-500 nm, an AlGaN buffer layer 3 with a thickness of 200-8000 nm, an intrinsic GaN channel layer 4 with a thickness of 50-500 nm and an Al x Ga 1-x N barrier layer 6 with a thickness of 10-30 nm and x=0.1-0.5 on the substrate 1 in sequence, as shown in Figure 3a .

[0059] S2: ion implantation is performed on both sides of the barrier layer to form a first isolation region and a second isolation region extending to the upper surface of the buffer layer, respectively.

[0060] Specifically, N ions are implanted into the isolation regions of the barrier layer 6 and the intrinsic GaN channel layer 4 on both sides of the upper surface of the barrier layer 6 by using an ion implantation process, and the N ion implantation concentration is 10 18 ~ 10 20 cm -3 , forming high resistance regions, i.e. the first isolation region 5 and the second isolation region 11, to achieve device isolation, as shown in FIG. 2. Figure 3b

[0061] S3: etching is performed in the middle of the upper surface of the barrier layer to form a gate region recess extending to the upper surface of the channel layer.

[0062] Specifically, the gate region recess 12 is formed by slow etching in the gate region of the barrier layer 6 close to the second isolation region 11, and the gate region recess 12 extends downward through the barrier layer 6 to the upper surface of the GaN channel layer 4, as shown in FIG. 3. The slow etching suppresses the interface state phenomenon caused by etching to some extent. Figure 3b

[0063] S4: growing a double-layer passivation layer in the gate region recess and on the remaining upper surface region of the barrier layer.

[0064] In this embodiment, step S4 includes:

[0065] S41: growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer 6 and in the gate region recess 12 by using a CVD (chemical vapor deposition) technique.

[0066] Specifically, the epitaxial wafer obtained in step S3 is cleaned by using SF6 plasma, NH3, SiH4 and N2 reaction gases are introduced into the CVD reaction chamber, and a 1-5 nm dense Si film is deposited on the surface of the epitaxial wafer as the Si passivation layer 101, as shown in FIG. 4. Figure 3d

[0067] S42: slow etching is performed to remove the Si passivation layer on the surface of the barrier layer away from the gate region recess, forming a U-shaped Si passivation layer 101 located in the gate region recess, as shown in FIG. 5. Figure 3e

[0068] S43: depositing a 5-100 nm SiO2 layer on the Si passivation layer and the upper surface of the barrier layer by using a PECVD (plasma enhanced chemical vapor deposition) process to form a SiO2 passivation layer.

[0069] ​​​​Specifically, the epitaxial wafer after the above steps is put into a PECVD reaction chamber, and a 5-100nm SiO2 layer is deposited on the surface of the epitaxial wafer as a SiO2 passivation layer, using NH3, SiH4 and N2 as reaction gases, as shown in Figure 3f .

[0070] S5: A gate electrode 8 is formed by depositing a metal on the double-layer passivation layer above the gate recess, thereby forming a gate MIS (metal-insulator-semiconductor) structure, as shown in Figure 3g .

[0071] S6: A source electrode and a drain electrode are respectively formed on both sides of the gate electrode 9, and the lower surface of the source electrode and the lower surface of the drain electrode are both in contact with the upper surface of the channel layer.

[0072] Specifically, a source recess and a drain recess extending to the upper surface of the channel layer are etched on both sides of the gate electrode 9 by using a photolithography process; a metal is deposited in the source recess and the drain recess by using a sputtering or electron beam evaporation process, thereby forming a source electrode 9 and a drain electrode 7, and then a stripping process and annealing are performed to realize a low-resistance ohmic contact of the source electrode and the drain electrode, as shown in Figure 3h . Preferably, the source electrode 9 and the drain electrode 7 are made of the same material, i.e., a Ti / Al-containing metal combination.

[0073] The embodiment provides a preparation method of a GaN-based double-layer passivation recess gate enhanced MIS-HEMT device. The double-layer passivation structure of the Si passivation layer and the SiO2 passivation layer can reduce the surface state of the passivation layer, and has a better passivation effect than the HEMT structure without the passivation layer and the single-layer passivation layer structure. The method process of the embodiment is relatively simple and compatible with the current traditional GaN HEMT process.

[0074] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application should not be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or replacements can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.

Claims

1. A GaN-based double-layer passivation recessed gate enhancement MIS-HEMT device, characterized in that, The barrier layer (6) is provided with a first isolation area (5) and a second isolation area (11) on both sides respectively, the first isolation area (5) and the second isolation area (11) extend from the upper surface of the barrier layer (6) to the upper surface of the buffer layer (3). The inner side of the first isolation area (5) and the second isolation area (11) is respectively provided with a drain electrode (7) and a source electrode (9), at least a part of the drain electrode (7) and at least a part of the source electrode (9) are embedded in the barrier layer (6), the lower surface of the drain electrode (7) and the source electrode (9) are in contact with the channel layer (4) and form ohmic contact. The barrier layer (6) between the drain electrode (7) and the source electrode (9) is provided with a gate area groove (12), the inner surface of the gate area groove (12) and the upper surface of the barrier layer (6) are coated with a double-layer passivation layer (10); the gate electrode (8) is arranged on the double-layer passivation layer (10) in the gate area groove (12). The double-layer passivation layer (10) includes a Si passivation layer (101) and a SiO2 passivation layer (102), wherein the Si passivation layer (101) is located in the gate area groove (12) and grows outward along the mesa of the gate area groove (12) so that the cross section is U-shaped. The SiO2 passivation layer (102) covers the upper surface of the Si passivation layer (101) and the upper surface of the barrier layer (6) between the drain electrode (7) and the source electrode (9), and contacts the source electrode (9) and the drain electrode (7) on both sides respectively. The thickness of the Si passivation layer (101) is 1-5nm, and the thickness of the SiO2 passivation layer is 5-100nm.

2. The GaN-based double-layered-passivated recessed-gate-enhancement MIS-HEMT device according to claim 1, wherein The lower end of the gate area groove (12) extends to the upper surface of the channel layer (4).

3. The GaN-based double-passivation recessed-gate-enhancement MIS-HEMT device of claim 1, wherein, The barrier layer (5) is an AlxGa1-xN barrier layer with a thickness of 10-30nm, wherein x=0.1-0.

5.

4. The GaN-based double-passivation recessed-gate-enhancement MIS-HEMT device of claim 1, wherein, The nucleation layer (2) is an AlN nucleation layer with a thickness of 50-400nm, the buffer layer (3) is an AlGaN buffer layer with a thickness of 200-8000nm, and the channel layer (4) is a GaN channel layer with a thickness of 50-500nm.

5. The GaN-based double-passivation recessed-gate-enhancement MIS-HEMT device according to any one of claims 1 to 4, characterized in that, It includes:

6. A method for fabricating a GaN-based double-layer passivated recessed gate enhancement mode MIS-HEMT device, characterized in that, S1: selecting a substrate and growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate in sequence; S2: ion implantation is carried out on both sides of the barrier layer to form a first isolation area and a second isolation area extending to the upper surface of the buffer layer respectively; S3: etching is carried out in the middle of the upper surface of the barrier layer to form a gate area groove extending to the upper surface of the channel layer; ​ S4: growing a double-layer passivation layer in the gate region recess and on the rest of the upper surface of the barrier layer; wherein the double-layer passivation layer (10) comprises a Si passivation layer (101) and a SiO2 passivation layer (102), wherein the Si passivation layer (101) is located in the gate region recess (12) and grows outward along the mesa of the gate region recess (12) to form a U-shaped cross section; the SiO2 passivation layer (102) covers the upper surface of the Si passivation layer (101) and the upper surface of the barrier layer (6) between the drain electrode (7) and the source electrode (9), and contacts the source electrode (9) and the drain electrode (7) on both sides, respectively; S5: depositing a gate electrode metal on the double-layer passivation layer above the gate region recess to form a gate electrode; S6: forming a source electrode and a drain electrode on both sides of the gate electrode, respectively, and the lower surface of the source electrode and the lower surface of the drain electrode both contact the upper surface of the channel layer.

7. The method of manufacturing a GaN-based double-passivation recessed gate enhanced MIS-HEMT device according to claim 6, wherein, The S1 comprises: S11: selecting a Si, SiC or sapphire substrate, and performing plasma cleaning and surface pretreatment on the surface of the substrate to keep the surface of the substrate clean; S12: sequentially epitaxially growing an AlN nucleation layer with a thickness of 50-500 nm, an AlGaN buffer layer with a thickness of 200-8000 nm, an intrinsic GaN channel layer with a thickness of 50-500 nm, and an AlxGa1-xN barrier layer with a thickness of 10-30 nm on the substrate, wherein x=0.1-0.

5.

8. The method of manufacturing a GaN-based double-layer-passivated recessed-gate-enhancement MIS-HEMT device according to claim 6, wherein The S4 comprises: S41: growing a 1-5 nm Si passivation layer on the upper surface of the barrier layer and in the gate region recess by using a CVD technique; S42: etching away the Si passivation layer on the surface of the barrier layer away from the gate region recess to form a U-shaped Si passivation layer located in the gate region recess; S43: depositing a 5-100 nm SiO2 on the Si passivation layer and the upper surface of the barrier layer by using a PECVD process to form a SiO2 passivation layer.

9. The method of producing a GaN-based double-layered passivation-recessed gate enhanced MIS-HEMT device according to claim 6, wherein The S6 comprises: S61: etching a source region recess and a drain region recess extending to the upper surface of the channel layer on both sides of the gate electrode by using a photolithography process; S62: depositing a metal in the source region recess and the drain region recess by using a sputtering or electron beam evaporation process, and then performing a stripping process and annealing to form a source electrode and a drain electrode.

Images