Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate and a manufacturing method thereof and a display panel. The array substrate comprises a substrate, a first active layer, a first gate, a second active layer and a second gate which are arranged in a stack. The first active layer comprises a first channel part corresponding to the first gate. The second active layer comprises a second channel part corresponding to the second gate. The first active layer and the second active layer are connected in parallel. The first channel part and the second channel part are arranged separately. The application sets the double-layer active layer connected in parallel on the substrate and uses the double-layer gate structure to conduct the double-layer active layer. The common conduction of the first active layer and the second active layer increases the conduction channel of the device. The two active layers arranged separately can accurately control the film thickness of each active layer. In the case of ensuring the electron mobility of the device, the device uniformity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and particularly relates to an array substrate, a manufacturing method thereof and a display panel. BACKGROUND

[0002] The material of the active layer in the common thin film transistor generally comprises amorphous silicon, low-temperature polysilicon and oxide. The oxide TFT is widely applied to the TFT device in the display industry due to its lower leakage current and higher mobility.

[0003] For the existing oxide TFT with the top gate structure, the mobility upper limit of the device is small, so the double gate structure or the double active layer structure is usually adopted to improve the mobility of the oxide TFT. The double gate structure can only improve the mobility of the oxide TFT by 1.4 times of the single gate structure, and the thickness of each active layer in the double active layer structure is difficult to control, the device uniformity is poor, and the demand of the high-resolution product cannot be met. SUMMARY

[0004] The present application provides an array substrate, a manufacturing method thereof and a display panel, so as to provide an array substrate with good device uniformity and high mobility.

[0005] To solve the above problems, the technical scheme provided by the present application is as follows:

[0006] The present application provides an array substrate, which comprises:

[0007] a substrate;

[0008] a first active layer disposed on the substrate, the first active layer comprising a first channel portion;

[0009] a first gate disposed on the first active layer, the first gate being disposed in correspondence with the first channel portion;

[0010] a second active layer disposed on the first gate, the second active layer comprising a second channel portion;

[0011] a second gate disposed on the second active layer, the second gate being disposed in correspondence with the second channel portion;

[0012] wherein the first active layer and the second active layer are connected in parallel, and the first channel portion and the second channel portion are disposed separately.

[0013] In the array substrate of the present application, the first active layer further comprises a first conductor portion located on both sides of the first channel portion, and the second active layer further comprises a second conductor portion located on both sides of the second channel portion;

[0014] wherein the first conductor portion and the corresponding second conductor portion are electrically connected.

[0015] In the array substrate of the present application, the array substrate further comprises:

[0016] An interlayer insulating layer is disposed on the first active layer, the interlayer insulating layer comprises a plurality of first vias, and the first vias expose part of the first conductor portions;

[0017] The second active layer is disposed on the interlayer insulating layer, the second conductor portion is overlapped on the inner wall of the first via, and the second conductor portion is connected with the first conductor portion through the first via;

[0018] A passivation layer is disposed on the interlayer insulating layer and covers the second gate, the passivation layer comprises a plurality of second vias, and the second vias expose part of the second conductor portions.

[0019] In the array substrate of the present application, the array substrate further comprises:

[0020] A source-drain layer is disposed between the substrate and the first active layer, the source-drain layer comprises a source and a drain which are separately disposed, and the source and the drain are respectively electrically connected with the first conductor portions on both sides of the first active layer.

[0021] In the array substrate of the present application, in the direction of the top view of the array substrate, the orthographic projection of the first channel portion on the source is located in the source.

[0022] In the array substrate of the present application, the length of the first channel portion is less than the length of the second channel portion.

[0023] In the array substrate of the present application, the mass ratio of oxygen element in the first channel portion is less than the mass ratio of oxygen element in the second channel portion.

[0024] In the array substrate of the present application, the first channel portion comprises a first sub-channel close to one side of the substrate and a second sub-channel away from the other side of the substrate, and the mass ratio of narrow band gap element in the first sub-channel is greater than the mass ratio of narrow band gap element in the second sub-channel.

[0025] In the array substrate of the present application, in the direction from the substrate to the first active layer, the mass ratio of narrow band gap element in the first channel portion gradually decreases.

[0026] The present application provides a manufacturing method of an array substrate, which comprises:

[0027] Providing a substrate;

[0028] Forming a first active layer on the substrate;

[0029] A first gate is formed on the first active layer, and the first gate is arranged correspondingly to the first channel part of the first active layer;

[0030] A second active layer is formed on the first gate, the first active layer and the second active layer are connected in parallel, and the second channel part of the second active layer is arranged separately from the first channel part;

[0031] A second gate is formed on the second active layer, and the second gate is arranged correspondingly to the second channel part.

[0032] The application further provides a display panel, which comprises the array substrate and a light-emitting component arranged on one side of the array substrate, and the array substrate and the light-emitting component are combined into one body.

[0033] Beneficial effects: The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate, a first active layer, a first gate, a second active layer and a second gate which are arranged in layers. The first active layer comprises a first channel part corresponding to the first gate. The second active layer comprises a second channel part corresponding to the second gate. The first active layer and the second active layer are connected in parallel. The first channel part and the second channel part are arranged separately. The application connects the double-layer active layers in parallel on the substrate, and uses the double-layer gate structure to conduct the double-layer active layers. The first active layer and the second active layer are conducted together, thereby increasing the conducting channel of the device. The two active layers arranged separately can accurately control the film thickness of each active layer, thereby improving the device uniformity while ensuring the electron mobility of the device. BRIEF DESCRIPTION OF DRAWINGS

[0034] The technical scheme and other beneficial effects of the application will be apparent to those skilled in the art from the following detailed description of the specific embodiments of the application with reference to the accompanying drawings.

[0035] Figure 1 FIG. 1 is a first structure diagram of the array substrate of the application;

[0036] Figure 2 FIG. 2 is a second structure diagram of the array substrate of the application;

[0037] Figure 3 FIG. 3 is a third structure diagram of the array substrate of the application;

[0038] Figure 4 FIG. 4 is a step diagram of the manufacturing method of the array substrate of the application;

[0039] Figures 5A to 5H FIG. 5 is a process step diagram of the manufacturing method of the array substrate of the application. DETAILED DESCRIPTION

[0040] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0041] The existing array substrate usually adopts a double-gate structure or a double-active layer structure to improve the mobility of the oxide TFT. The double-gate structure can only improve the mobility of the oxide TFT by 1.4 times of the single-gate structure. In the double-active layer structure, two layers of active layers are stacked, and the thickness of each layer of active layer is difficult to control, and the device uniformity is poor. Therefore, the present application provides an array substrate to solve the above technical problems.

[0042] The present application provides an array substrate 100, which comprises a substrate 110, a first active layer 140 arranged on the substrate 110, a first gate 160 arranged on the first active layer 140, a second active layer 180 arranged on the first gate 160, and a second gate 210 arranged on the second active layer 180.

[0043] In the present embodiment, the first active layer 140 comprises a first channel portion 141, the second active layer 180 comprises a second channel portion 181, the first gate 160 is arranged corresponding to the first channel portion 141, and the second gate 210 is arranged corresponding to the second channel portion 181.

[0044] In the present embodiment, the first active layer 140 and the second active layer 180 can be connected in parallel, and the first channel portion and the second channel portion 181 are arranged separately.

[0045] In the present embodiment, the present application arranges double-layer active layers connected in parallel on the substrate 110, and uses a double-layer gate structure to turn on the double-layer active layers, so that the first active layer 140 and the second active layer 180 are turned on together. The two layers of active layers arranged separately can accurately control the film thickness of each active layer, which improves the device uniformity while ensuring the electron mobility of the device.

[0046] Please refer to Figure 1 , the array substrate 100 can comprise a substrate 110 and a driving circuit layer 200 arranged on the substrate 110. The driving circuit layer 200 can comprise a thin film transistor, which can be an etch-stop type, a back channel etch type, or a bottom-gate thin film transistor, a top-gate thin film transistor, etc. according to the position of the gate and the active layer. The technical solutions of the present application will be described below with the back channel etch type thin film transistor as an example.

[0047] In the embodiment, the material of the substrate 110 can be glass, quartz, polyimide or the like.

[0048] In the embodiment, referring to Figure 1 , the array substrate 100 can include:

[0049] The first active layer 140 is disposed on the substrate 110, and the first active layer 140 includes a first channel portion 141 and a first conductor portion 142 located on both sides of the first channel portion 141. The material of the first active layer 140 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides. The following embodiments of the present application take IGZO as an example for description.

[0050] The first gate insulating layer 150 is disposed on the first active layer 140, and the first gate insulating layer 150 is used to insulate the upper metal layer from the first active layer 140. In the embodiment, the material of the first gate insulating layer 150 can include a compound composed of nitrogen element, silicon element and oxygen element.

[0051] The first gate electrode 160 is disposed on the first gate insulating layer 150, and the material of the first gate electrode 160 can include Cr, W, Ti, Ta, Mo, Al, Cu or other metals or alloys. The pattern of the first gate electrode 160 is the same as that of the first gate insulating layer 150, and the first gate electrode 160 corresponds to the first channel portion 141, that is, the orthographic projection of the first channel portion 141 on the first gate electrode 160 can be located in the first gate electrode 160, so as to protect the first channel portion 141 from being affected by external light.

[0052] The interlayer insulating layer 170 is disposed on the first gate electrode 160, and the interlayer insulating layer 170 is entirely laid and covers the first gate electrode 160 and the first active layer 140. In the embodiment, the material of the interlayer insulating layer 170 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide film layer or a laminated structure of silicon oxide-silicon nitride-silicon oxide. The interlayer insulating layer 170 in the embodiment is provided with a plurality of first vias 171, and the first vias 171 make part of the first conductor portion 142 exposed.

[0053] A second active layer 180 is disposed on the interlayer insulating layer 170, and the second active layer 180 includes a second channel portion 181 and second conductor portions 182 located on both sides of the second channel portion 181. The first conductor portion 142 is electrically connected to the corresponding second conductor portion 182 through the first via hole 171. In the embodiment, the material of the second active layer 180 can be the same as that of the first active layer 140.

[0054] A second gate insulating layer 190 is disposed on the second active layer 180, and the second gate insulating layer 190 is used to insulate the upper metal layer from the second active layer 180. In the embodiment, the material of the second gate insulating layer 190 can include a compound composed of nitrogen, silicon and oxygen.

[0055] A second gate electrode 210 is disposed on the second gate insulating layer 190, and the material of the second gate electrode 210 can be the same as that of the first gate electrode 160. The pattern of the second gate electrode 210 is the same as that of the second gate insulating layer 190, and the second gate electrode 210 corresponds to the second channel portion 181, that is, the orthographic projection of the second channel portion 181 on the second gate electrode 210 can be located in the second gate electrode 210, so as to protect the second channel portion 181 from being affected by external light.

[0056] A passivation layer 220 is disposed on the second gate electrode 210, and the passivation layer 220 is entirely disposed and covers the second gate electrode 210 and the second active layer 180. In the embodiment, the material of the passivation layer 220 can include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film or a stacked structure of silicon oxide-silicon nitride. In the embodiment, the passivation layer is provided with a plurality of second via holes 221, and the second via holes 221 expose part of the second conductor portions 182.

[0057] A pixel electrode layer 230 is disposed on the passivation layer 220, and the pixel electrode layer 230 is electrically connected to the second conductor portions 182 through the second via holes 221. The material of the pixel electrode layer 230 can be a transparent metal material such as indium tin oxide.

[0058] In the embodiment, referring to Figure 1 , the array substrate 100 can further include a source-drain electrode layer 120 disposed between the substrate 110 and the first active layer 140, and a buffer layer 130 disposed between the source-drain electrode layer 120 and the first active layer 140.

[0059] In the embodiment, the source-drain layer 120 includes a source electrode 121 and a drain electrode 122 arranged separately, and the source electrode 121 and the drain electrode 122 are electrically connected to the first conductor portion 142 on both sides of the first active layer 140, respectively.

[0060] In the embodiment, the material of the source-drain layer 120 can include Cr, W, Ti, Ta, Mo, Al, Cu or other metal or alloy.

[0061] In the embodiment, the material of the buffer layer 130 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide film layer or a silicon oxide-silicon nitride stacked structure.

[0062] In the array substrate 100 of the present application, please refer to Figure 1 In the plan view of the array substrate 100, the orthographic projection of the first channel portion 141 on the source electrode 121 is located in the source electrode 121.

[0063] In the prior art array substrate 100, the channel of the thin film transistor will be affected by the light, which will affect the mobility of the active layer and further cause the performance of the thin film transistor to drift. In the embodiment, the first active layer 140 is arranged close to the substrate 110, and if the array substrate 100 of the present application is applied to a liquid crystal display panel, the backlight source will pass through the substrate 110 into the thin film transistor, which will affect the mobility of the active layer.

[0064] In the embodiment, the source electrode 121 can continue to extend to the drain electrode 122, and the orthographic projection of the first channel portion 141 on the source electrode 121 is located in the source electrode 121; in addition to being used as a signal input end, the source electrode 121 of the embodiment can also be used as a light shielding layer. The present application extends the source electrode 121 to the drain electrode 122 and shields the first channel portion 141, so that the first channel portion 141 is not affected by external light.

[0065] In the embodiment, the source electrode 121 and the drain electrode 122 are interchangeable, so the orthographic projection of the first channel portion 141 on the drain electrode 122 is also located in the drain electrode 122 in the embodiment.

[0066] In the embodiment, since the first gate 160 is arranged between the first active layer 140 and the second active layer 180, the voltage of the first gate 160 can act on the second active layer 180 in addition to turning on the first active layer 140, and since the second gate 210 is arranged on the side of the second active layer 180 away from the first active layer 140, the second gate 210 can only act on the second active layer 180, that is, the first active layer 140 is turned on by the voltage of the first gate 160, and the second active layer 180 is turned on by the voltage of the first gate 160 and the second gate 210, that is, there is a certain difference in the opening speed between the first active layer 140 and the second active layer 180, that is, the opening speed of the channel part in the first active layer 140 can be less than that of the channel part in the second active layer 180, resulting in a delay in data transmission.

[0067] In the embodiment, referring to Figure 2 , the length L1 of the first channel part 141 can be less than the length L2 of the second channel part 181. Since the first channel part 141 is only driven by the first gate 160 and the second channel part 181 is driven by the first gate 160 and the second gate 210, the length L1 of the first channel part 141 is reduced in the embodiment, that is, the distance between the two first conductor parts 142 is reduced, and the turn-on speed of the two first conductor parts 142 is increased, that is, the difference in the number of gate driving between the first channel part 141 and the second channel part 181 is balanced, the technical problem of the difference in the opening speed between the first active layer 140 and the second active layer 180 is solved, and the consistency of the transmission rate of data signals from different active layers is ensured.

[0068] In the array substrate 100 of the present application, the mass ratio of oxygen in the first channel part 141 is less than the mass ratio of oxygen in the second channel part 181. The electron mobility of the channel part is related to the material properties of the channel part in addition to the effect of the external electric field, for example, the material in the channel part is generally IGZO, and the mass ratio of oxygen in the first channel part 141 is reduced in the embodiment, that is, the mass ratio of oxygen in the metal oxide in the first channel part 141 is reduced, the mass ratio of the metal is increased, the electron mobility of the first channel part 141 is improved, the difference in the number of gate driving between the first channel part 141 and the second channel part 181 is balanced, the technical problem of the difference in the opening speed between the first active layer 140 and the second active layer 180 is solved, and the consistency of the transmission rate of data signals from different active layers is ensured.

[0069] In the embodiment, the first gate 160 can serve as a light shielding member of the first channel portion 141, and the second gate 210 can serve as a light shielding member of the second channel portion 181, in addition to serving as a switch for the first active layer 140 and the second active layer 180, respectively. External light can also enter the panel through one side of the pixel electrode layer 230 of the array substrate 100 and then irradiate the first channel portion 141 and the second channel portion 181. Therefore, to avoid the irradiation of external light on the corresponding channel portion, the area of the first gate 160 and the second gate 210 can be greater than the area of the corresponding channel portion.

[0070] In the existing display panel, the oxide of the narrow band element combined with oxygen is a narrow band oxide, and the narrow band oxide has poor stability. Under the working environment of long-time light irradiation or abnormal temperature, the performance of the thin film transistor is prone to drift.

[0071] In the array substrate 100 of the present application, referring to Figure 3 , the first channel portion 141 includes a first sub-channel 141a close to one side of the substrate 110 and a second sub-channel 141b away from the other side of the substrate 110, and the mass fraction of the narrow band element in the first sub-channel 141a is greater than that in the second sub-channel 141b.

[0072] In the embodiment, the oxide doped in the channel portion is composed of an oxide of a narrow band element and a wide band element, and the second sub-channel 141b is disposed close to the light emitting side, and the first sub-channel 141a is located between the substrate 110 and the second sub-channel 141b. When external light enters the display panel, it only irradiates the second sub-channel 141b. Since the mass fraction of the narrow band element in the second sub-channel 141b is small, the oxide in the second sub-channel 141b is mainly composed of a wide band metal oxide, so the influence of light irradiation on the second sub-channel 141b is small under long-time light irradiation conditions. The first sub-channel 141a is shielded by the second sub-channel 141b, so the influence of light irradiation on the first sub-channel 141a is weak, which ensures the stability of the thin film transistor device.

[0073] In the embodiment, taking IGZO as an example, the indium element is a narrow band element, and the gallium element and the zinc element are wide band elements. Therefore, the present application needs to reduce the mass fraction of the indium element in the second sub-channel 141b.

[0074] In the embodiment, although the first gate 160 shields the first channel portion 141, there is still some light leakage into the first channel portion 141 from the edge region of the first channel portion 141. Similarly, the second channel portion 181 can be provided in the same manner as the first channel portion 141, and only the electron mobility of the first channel portion 141 and the second channel portion 181 needs to be balanced.

[0075] In the embodiment, in addition to the stability factor, because the first channel portion 141 and the second channel portion 181 are driven by different numbers of gates, the application improves the light and thermal stability of the first channel portion 141 by reducing the proportion of the narrow-band element in the narrow-band oxide in the first channel portion 141, thereby ensuring the improvement of the electron mobility of the first active layer 140, and solving the technical problem of the difference in the opening rate between the first active layer 140 and the second active layer 180.

[0076] In the array substrate 100 of the application, the proportion of the mass of the narrow-band element in the first channel portion 141 gradually decreases in the direction from the substrate 110 to the first active layer 140.

[0077] In the embodiment, when external light shines on the first channel portion 141, the closer the first channel portion 141 is to the light-out side of the array substrate 100, the greater the light intensity it receives, and the farther the first channel portion 141 is from the light-out side of the array substrate 100, the smaller the light intensity it receives. Therefore, according to the different light intensities received by different positions in the first channel portion 141, the proportion of the mass of the narrow-band element in the first channel portion 141 is set in a gradient manner, that is, the closer to the light-out side of the array substrate 100, the smaller the proportion of the mass of the narrow-band element in the first channel portion 141, thereby improving the stability of the thin film transistor under light conditions.

[0078] In the embodiment, the second channel portion 181 can be provided in the same manner as the first channel portion 141, and only the electron mobility of the first channel portion 141 and the second channel portion 181 needs to be balanced.

[0079] In the embodiment, the difference in the proportion of the narrow-band element between the first sub-channel 141a and the second sub-channel 141b can be achieved by treating the surface of the second sub-channel 141b with an acid solution containing fluoride ions to precipitate indium elements from the channel.

[0080] In the embodiment, because the acid solution containing fluoride ions has a certain etching effect on the metal oxide in the channel portion, the surface of the second sub-channel 141b may be etched after the indium elements are precipitated.

[0081] The application further provides a display panel, which comprises the array substrate 100 and a light-emitting component arranged on one side of the array substrate 100, and the array substrate 100 and the light-emitting component are combined into one body.

[0082] For example, when the display panel is a liquid crystal display panel, the light-emitting component can be a backlight module; when the display panel is a self-luminous display panel, the light-emitting component can be an organic light-emitting device or a Micro-LED, which is not limited in the application.

[0083] The application provides a manufacturing method of the array substrate 100, please refer to Figure 4 , which comprises the following steps.

[0084] S10, providing a substrate 110;

[0085] Please refer to Figure 5A , the material of the substrate 110 can be glass, quartz or polyimide.

[0086] S20, forming a first active layer 140 on the substrate 110;

[0087] In the embodiment, before the step S20, the method further comprises the following steps.

[0088] forming a source-drain layer 120 on the substrate 110;

[0089] forming a buffer layer 130 on the source-drain layer 120.

[0090] In the embodiment, please refer to Figure 5A , the source-drain layer 120 comprises a source electrode 121 and a drain electrode 122 arranged separately, and the source electrode 121 and the drain electrode 122 are respectively electrically connected with the first conductor part 142 on both sides of the first active layer 140.

[0091] In the embodiment, the material of the source-drain layer 120 can comprise Cr, W, Ti, Ta, Mo, Al, Cu or other metal or alloy.

[0092] In the embodiment, the source-drain layer 120 is generally arranged above the active layer in the conventional structure, and the lower active layer and the upper pixel electrode layer 230 are conducted, but due to the double active layer and double gate structure of the application, arranging the source-drain layer 120 above the active layer will further increase the complexity of the topography of the thin film transistor; and in the embodiment, the source-drain layer 120 is arranged between the substrate 110 and the first active layer 140, and since the surface of the substrate 110 is flat, the topography of the thin film transistor is improved, and the risk of disconnection of the source-drain and drain electrode 122 is avoided.

[0093] In the embodiment, referring to Figure 5B The material of the buffer layer 130 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide film or a stacked structure of silicon oxide-silicon nitride.

[0094] In step S20, referring to Figure 5C The material of the first active layer 140 can be metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxide. The following embodiments take IGZO as an example for illustration.

[0095] In step S20, the two ends of the first active layer 140 are electrically connected to the corresponding source electrode 121 and drain electrode 122 through the via hole on the buffer layer 130.

[0096] S30, a first gate 160 is formed on the first active layer 140, and the first gate 160 is arranged corresponding to the first channel part 141 of the first active layer 140.

[0097] In the embodiment, referring to Figure 5D Step S30 can include:

[0098] A first gate insulating material layer and a first gate material layer are formed on the first active layer 140.

[0099] The first gate insulating material layer and the first gate material layer are patterned to form the first gate 160 and the first gate insulating layer 150 corresponding to the first channel part 141.

[0100] The first active layer 140 is processed by plasma to form the first conductor part 142 in the region not covered by the first gate 160 and the first gate insulating layer 150, and the structure between the first conductor parts 142 is the first channel part 141.

[0101] An interlayer insulating layer 170 is formed on the first gate 160, and a plurality of first via holes 171 are formed on the interlayer insulating layer 170, which exposes part of the first conductor part 142.

[0102] In the embodiment, when the first gate insulating material layer and the first gate material layer are patterned, the first gate material layer is first patterned to form the first gate 160, and then the first gate insulating material is patterned in a self-alignment manner with the first gate 160 to form the first gate insulating layer 150.

[0103] In the embodiment, the first gate 160 can be formed by a wet etching process, and the first gate insulating layer 150 can be formed by a dry etching process.

[0104] In the embodiment, the first gate insulating layer 150 is used to insulate the upper metal layer from the first active layer 140. The material of the first gate insulating layer 150 in the embodiment can include a compound composed of nitrogen, silicon, and oxygen.

[0105] In the embodiment, the material of the first gate 160 can include Cr, W, Ti, Ta, Mo, Al, Cu, or the like. The first gate 160 and the first gate insulating layer 150 have the same pattern, and the first gate 160 corresponds to the first channel portion 141, that is, the orthographic projection of the first channel portion 141 on the first gate 160 can be located in the first gate 160 to protect the first channel portion 141 from external light.

[0106] In the embodiment, referring to Figure 5E , the interlayer insulating layer 170 is laid in an entire layer and covers the first gate 160 and the first active layer 140. The material of the interlayer insulating layer 170 in the embodiment can include a compound composed of nitrogen, silicon, and oxygen, such as a single-layer silicon oxide film layer or a stacked structure of silicon oxide-silicon nitride-silicon oxide.

[0107] S40, a second active layer 180 is formed on the first gate 160, the first active layer 140 and the second active layer 180 are connected in parallel, and the first channel portion and a second channel portion 181 of the second active layer 180 are separately arranged;

[0108] In this step, referring to Figure 5F , the second active layer 180 is electrically connected to the first conductor portion 142 in the first active layer 140 through the first via hole 171, that is, the first active layer 140 and the second active layer 180 are connected in parallel at the two ends.

[0109] S50, a second gate 210 is formed on the second active layer 180, and the second gate 210 is arranged corresponding to the second channel portion 181.

[0110] In the embodiment, referring to Figure 5G , step S50 can include:

[0111] forming a second gate insulating material layer and a second gate material layer on the second active layer 180;

[0112] patterning the second gate insulating material layer and the second gate material layer to form a second gate 210 and a second gate insulating layer 190 corresponding to the second channel part 181;

[0113] processing the second active layer 180 by plasma to form a second conductor part 182 in the region not covered by the second gate 210 and the first gate insulating layer 150, and the structure between the second conductor parts 182 is the second channel part 181.

[0114] In the embodiment, when the second gate insulating material layer and the second gate material layer are patterned, the second gate material layer is first patterned to form the second gate 210, and then the second gate insulating material is patterned in a second gate self-alignment manner to form the second gate insulating layer 190.

[0115] In the embodiment, the second gate 210 can be formed by a wet etching process, and the second gate insulating layer 190 can be formed by a dry etching process. In the embodiment, the second gate insulating layer 190 is used to isolate the second gate 210 from the second active layer 180. The material of the second gate insulating layer 190 in the embodiment can include a compound composed of nitrogen, silicon and oxygen elements.

[0116] In the embodiment, the material of the second gate 210 can be the same as that of the first gate 160. The patterns of the second gate 210 and the second gate insulating layer 190 are the same, and the second gate 210 corresponds to the second channel part 181, that is, the orthographic projection of the second channel part 181 on the second gate 210 can be located in the second gate 210 to protect the second channel part 181 from being affected by external light.

[0117] S60, forming a passivation layer 220 on the second gate 210, and forming a plurality of second vias 221 on the passivation layer 220, the second vias 221 exposing part of the second conductor part 182.

[0118] Referring to Figure 5HThe passivation layer 220 is integrally laid and covers the second gate 210 and the second active layer 180. In the embodiment, the material of the passivation layer 220 can include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film or a stacked structure of silicon oxide-silicon nitride.

[0119] S70, forming a pixel electrode layer 230 on the passivation layer 220, so that the pixel electrode layer 230 is electrically connected through the second via hole 221 and the second conductor part 182.

[0120] In the embodiment, referring to Figure 5H The material of the pixel electrode layer 230 can be transparent metal material such as indium tin oxide.

[0121] The application further provides a mobile terminal including a terminal body and the display panel, and the terminal body and the display panel are combined into one. The terminal body can be a circuit board or other device bound to the display panel and a cover plate or the like covering the display panel. The mobile terminal can include a mobile phone, a television, a notebook computer or other electronic equipment.

[0122] The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate, a first active layer, a first gate, a second active layer and a second gate which are arranged in a stack. The first active layer includes a first channel part corresponding to the first gate. The second active layer includes a second channel part corresponding to the second gate. The first active layer and the second active layer are connected in parallel. The first channel part and the second channel part are arranged separately. The application connects the double-layer active layers in parallel on the substrate, and uses the double-layer gate structure to turn on the double-layer active layers. The first active layer and the second active layer are turned on together, which increases the turn-on channel of the device and improves the electron mobility of the device.

[0123] In the above embodiments, the description of each embodiment focuses on different aspects. The parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0124] The array substrate and the manufacturing method thereof and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a first active layer disposed on the substrate, the first active layer comprising a first channel portion; a first gate disposed on the first active layer, the first gate being disposed in correspondence with the first channel portion; a second active layer disposed on the first gate, the second active layer comprising a second channel portion, the first active layer and the second active layer being connected in parallel, the first channel portion and the second channel portion being disposed separately; a second gate disposed on the second active layer, the second gate being disposed in correspondence with the second channel portion; wherein a mass ratio of oxygen in the first channel portion is less than a mass ratio of oxygen in the second channel portion; or the first channel portion comprises a first sub-channel close to a side of the substrate and a second sub-channel away from the side of the substrate, a mass ratio of a narrow band gap element in the first sub-channel being greater than a mass ratio of the narrow band gap element in the second sub-channel.

2. The array substrate of claim 1, wherein, The first active layer further comprises first conductor portions located on both sides of the first channel portion, and the second active layer further comprises second conductor portions located on both sides of the second channel portion; wherein the first conductor portions and the corresponding second conductor portions are electrically connected.

3. The array substrate of claim 2, wherein, The array substrate further comprises: an interlayer insulating layer disposed on the first active layer, the interlayer insulating layer comprising a plurality of first vias, the first vias exposing part of the first conductor portions; the second active layer is disposed on the interlayer insulating layer, the second conductor portions are overlapped on inner walls of the first vias, and the second conductor portions are connected with the first conductor portions through the first vias; a passivation layer disposed on the interlayer insulating layer and covering the second gate, the passivation layer comprising a plurality of second vias, the second vias exposing part of the second conductor portions.

4. The array substrate of claim 2, wherein, The array substrate further comprises: a source-drain layer disposed between the substrate and the first active layer, the source-drain layer comprising a source and a drain disposed separately, the source and the drain being electrically connected with the first conductor portions on both sides of the first active layer respectively.

5. The array substrate of claim 4, wherein, In a top view direction of the array substrate, a normal projection of the first channel portion on the source is located in the source.

6. The array substrate of claim 2, wherein, A length of the first channel portion is less than a length of the second channel portion.

7. The array substrate of claim 2, wherein, In a direction from the substrate to the first active layer, a mass ratio of a narrow band gap element in the first channel portion gradually decreases.

8. A manufacturing method of an array substrate, characterized by, The array substrate comprises: providing a substrate; forming a first active layer on the substrate; forming a first gate on the first active layer, the first gate being disposed in correspondence with a first channel portion of the first active layer; forming a second active layer on the first gate, the first active layer and the second active layer being connected in parallel, and the first channel portion and a second channel portion of the second active layer being disposed separately; forming a second gate on the second active layer, the second gate being disposed in correspondence with the second channel portion; wherein a mass ratio of oxygen in the first channel portion is less than a mass ratio of oxygen in the second channel portion; or the first channel portion comprises a first sub-channel close to a side of the substrate and a second sub-channel away from the side of the substrate, a mass ratio of a narrow band gap element in the first sub-channel being greater than a mass ratio of the narrow band gap element in the second sub-channel. The first channel portion includes a first sub-channel close to the substrate side and a second sub-channel away from the substrate side, and the mass proportion of the narrow band gap element in the first sub-channel is greater than the mass proportion of the narrow band gap element in the second sub-channel.

9. A display panel, characterized by, The display panel includes the array substrate as claimed in any one of claims 1 to 7 and a light emitting component located on one side of the array substrate, and the array substrate and the light emitting component are combined into one body.

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